Low Intermediate Frequency Receiver Research Articles

A Sub-1-V, 350-$\mu$ W, 6.5-dB Integrated NF Low-IF Receiver Front-End for IoT in 28-nm CMOS

This letter presents a highly efficient low-intermediate frequency receiver front-end for Internet-of-Things applications. The low-noise trans-impedance amplifier (LNTA) combines a transformer-based network for scaling up the source impedance together with passive gm -boosting and current-reuse techniques to achieve better noise and $12\times $ current saving compared with a common-gate (CG) stage. A complex channel-selection filter with center frequency and passband of 2 and 1.4 MHz, respectively, is implemented after the passive mixer with a gm -boosted CG stage. Built in 28-nm CMOS, the proposed receiver occupies an active area of 0.1 mm2, it is supplied with 0.9 V and consumes only 350 $\mu \text{W}$ , while showing a minimum NF of 6.2 dB at the channel of interest. The RF performance of the proposed receiver is very competitive with the state-of-the-art ultralow-power receivers, while it consumes the lowest power.

Concurrent Dual-Band Low Intermediate Frequency Receiver Based on the Multiport Correlator and Single Local Oscillator

A concurrent dual-band low intermediate frequency receiver, which is based on the multiport correlator, is proposed in this letter. Only one single local oscillator signal is used to demodulate the dual-band RF signals at the same time, which greatly reduce the receiver complexity. The system configuration, output power theory, as well as the power spectrum are analyzed in detail, and then an appropriate baseband signal recovery theory is put forward. Finally, a concurrent dual-band six-port receiver is tested under the long-term evolution signals with 3- and 5-MHz bandwidths. The measured error vector magnitudes are all lower than 2%, which verify the proposed system structure and the signal recovery theory.

A 70-mW ISDB-T Tuner for VHF and UHF Bands

This brief presents a highly integrated low-Intermediate Frequency receiver for use in UHF/VHF channel 7 and Channel 8 Integrated Services Digital Broadcasting-Terrestrial (ISDB-T) systems (90-220 MHz). It features an ultralow power consumption of 68 mW (55 mW in attenuator mode) with a noise figure of 3 dB. The device fully complies with the ISDB-T standard and is implemented in 0.13-μm CMOS technology with fully integrated low-noise amplifier/matching networks, a voltage-controlled oscillator, a phase-locked loop/loop filter, a crystal oscillator, baseband filters, and Variable Gain Amplifier. The tuner only requires a prefiltering RF surface acoustic wave filter to notch out cellular frequencies and a biasing inductor to implement a fully compliant ISDB-T tuner. The full characterization of the tuner and the comparison with previous implementation are presented. The chip area is 2.1 mm × 2.1 mm.

CRLB-Achieving I/Q Mismatch Estimator for Low-IF Receiver Using Repetitive Training Sequence in the Presence of CFO

This paper presents a method for estimating the in-phase/quadrature-phase (I/Q) mismatch in low-intermediate frequency receivers for orthogonal frequency division multiplexing (OFDM) signals in the presence of carrier-frequency offset. The proposed estimator operates on the repetitive training sequence of the OFDM packet preamble. To derive a practical maximum-likelihood estimator, an invertible mapping operation is applied on the observation vectors, so that a closed-form expression of the likelihood function can be obtained. The proposed estimator is shown to achieve the Cramer Rao lower bound at high image signal power levels. The error variance of the estimator is analyzed, which closely matches simulation results. The uncoded bit-error-rate is shown via simulation to be approximately that of an ideal receiver without I/Q mismatch.

Self-Shielded Quad-Band EGPRS Transceiver With Spur Avoidance

The next generation of global system for mobile communications/EDGE large signal polar modulation transceivers from RF micro devices (RFMD), Greensboro, NC, is described. The transceiver is realized as a single die in 0.18-mum CMOS. A very low intermediate frequency receiver architecture at 175 kHz is implemented with automatic image calibration. A novel fractional-N offset phase-locked loop with digital automatic frequency correction allows wider bandwidth operation, as well as the ability to change the IF to avoid channel-dependent spurious responses. An AM loop is added to reduce variations in total radiated power, as well as to limit power amplifier current and voltage. The solution is realized as two self-shielded modules using conformal shielding. Only one additional external capacitor is required to realize the entire radio from the DigRF interface to the antenna.

Decorrelating Compensation Scheme for Coefficient Errors of a Filter Bank Parallel A/D Converter

In this letter, a parallel analog-digital (A/D) conversion scheme with a filter bank for low intermediate-frequency receivers is presented. The analysis filters of the filter bank divide the frequency components of the received signal, and achieve parallel A/D conversion. Therefore, the required conversion rates and the resolution of the A/D converters can be reduced and the receiver can demodulate wideband signals. As the analysis filters consist of analog components, their coefficients include errors. These errors cause mutual interference between signals in orthogonal frequencies. In order to remove this interference, a decorrelating compensation scheme is proposed.