Low Gate Leakage Current Research Articles

(Invited) Where Are the Best Insulators for 2D Field-Effect Transistors?

Two-dimensional (2D) semiconductors are very promising for applications in next-generation field-effect transistors (FETs) which could overcome scaling limitations of Si technologies and thus extend the life of Moore’s law. The success at achieving this ambitious goal will depend on the availability of compatible insulators which are always required to separate the gate from the channel. Ideally, these insulators should go along with 2D semiconductors as well as SiO2 goes with Si. However, the research community is mostly focused on 2D semiconductors while not paying enough attention to finding suitable insulators for 2D FETs. In order to shed some light on this problem, here we formulate general requirements for insulators in 2D FETs and discuss the potential of already used and promising materials.The scaling potential of 2D FETs can be fully exploited only if high quality insulators with an equivalent oxide thickness (EOT) below 1nm are available, as required for low subthreshold swings and reduced power consumption. This results in the following requirements for gate insulators: First, dielectric properties have to be good enough to maintain low tunnel and thermionic leakage currents to achieve high on/off current ratios. This implies high dielectric constants, wide band gaps and large band offsets with the channel material. Second, the insulator must form a well-defined interface with the channel, which is primarily required for a high mobility. Third, the number of active insulator defects within a few nanometers from the interface has to be low, in order to reduce charge trapping and thus maintain high stability of device operation. Finally, the insulators have to be electrically stable when scaled and survive electric fields of at least 10MV/cm.Most previously reported 2D FETs employ conventional oxides (e.g. SiO2, HfO2, Al2O3) known from Si technologies. High-k oxides HfO2 and Al2O3 appear to be the most promising, as they in principle satisfy the requirement on low leakage currents. However, they are amorphous when grown in thin layer, thus forming poor-quality interfaces with 2D channels, and contain numerous unavoidable insulator defects which lead to hysteresis and long-term drifts of the gate transfer characteristics. As a result, it appears to be unlikely that these materials can be considered promising for applications in future fully scalable 2D FETs.In the spirit of Si technologies, a possible alternative to conventional oxides could be oxidation of 2D semiconductors to form native oxides, such as MoO3 from MoS2. While this may improve the interface quality, native oxides are still amorphous and sometimes non-stoichiometric, which leads to high densities of insulator defects and limited electric strength. Thus, considerable research efforts are still required to understand their potential.Another possible solution is the use of layered 2D insulators. Their main advantage is their crystalline structure which leads to well-defined interface with 2D semiconductors and a low density of insulator defects. However, the most widely used 2D insulator is hexagonal boron nitride (hBN) which has a narrow bandgap (6eV) and a small dielectric constant (less than 5). This makes it difficult to maintain low gate leakage currents for hBN with sub-1nm EOT. Thus, alternative 2D insulators have to be urgently identified and characterized. Among these materials are mica, which outperforms hBN in terms of dielectric properties, and 2D oxide nanosheets. However, considerable processing advances are required to result in the demonstration of real devices.Finally, another interesting option would be the use of ionic crystals, such as epitaxial fluorides (e.g. CaF2, BaF2, and LaF3). Similar to 2D insulators, fluorides ideally contain a small number of defects and form well-defined interfaces with 2D semiconductors. Also, in contrast to hBN, they have good dielectric properties, e.g. a bandgap of 12.1 eV and a dielectric constant of 8.43 for CaF2. Recently, excellent performance of MoS2 FETs with 2nm thick epitaxial CaF2 (0.9nm EOT) has been achieved, which is currently impossible with any other insulator discussed above. Thus, further research on these insulators appears a very promising way for the development of scalable 2D FETs.In summary, the question about the most promising insulators for 2D FETs is still open. However, already now it is clear that successful integration of amorphous oxides into these devices appears problematic. Thus, it can be concluded that high-quality 2D FETs require crystalline insulators. These can be either layered 2D or ionic crystals with chemically inert surfaces, which generally address the fundamental limitations of oxides. Further research on these materials should target those which have the best dielectric properties and can be synthesized using fully scalable methods.

Performance analysis of HfO2/InAlN/AlN/GaN HEMT with AlN buffer layer for high power microwave applications

We present a performance enhancement evaluation of n + doped graded InGaN drain/source region-based HfO 2 /InAlN/AlN/GaN/AlN on SiC metal-oxide-semiconductor high electron mobility transistor (MOS-HEMTs) with a T-shaped gate. Impact on the device characteristics with the inclusion of a HfO 2 surface passivation layer and an AlN buffer layer in the MOS-HEMT structure as a performance booster has been analyzed for the HEMT device with 30 nm gate length using Silvaco ATLAS TCAD. The proposed MOS-HEMT exhibits an outstanding performance, with an enhanced power gain cut-off frequency (f max ) of 366 GHz, a current gain cut-off frequency (f t ) of 426 GHz, and a off-state breakdown voltage (V br ) of 81 V. The high -k (high permittivity) HfO 2 based metal oxide semiconductor HEMT device experiences a low off-state gate leakage current (I g ~ 10 −11 A/mm) and a high I on /I off ratio of 10 9 . The InAlN/GaN/AlN heterostructures demonstrate improved two-dimensional electron gas (2DEG ~ 5.3 × 10 13 cm −2 ), carrier mobility (μ) of 1256 Cm 2 /V-s and drain current density of (I ds ) 2.7 A/mm. A large signal analysis performed at 30 GHz yielded a maximum of 28% power-added efficiency. The high JFoM of 34.506 THz V (Johnson Figure of Merit = f t × V br ) and (f t .f max ) 1/2 of 394.86 GHz indicate the potential applicability of the HfO 2 /InAlN/GaN MOS-HEMTs in high-frequency and high-power applications.

Surface Improvement of InAlAs/InGaAs InP-Based HEMT Through Treatments of UV/Ozone and TMAH

In this paper, we introduce novel surface treatments of UV/Ozone and TMAH to solve the surface problem of gate recess of InAlAs/InGaAs InP-based HEMTs. The problem of nonstoichiometric surface of InP etch stopper layer was found to be the result of donor-like surface defects brought by HF damage, bringing troubles like kink effect, high gate leakage current and deteriorated noise performance. Through the method of surface treatments, the InAlAs/InGaAs InP-based HEMTs exhibit excellent DC performances, demonstrating a low gate leakage currents of 10 -8 A/um, a peak transconductance of 1100mS/mm, an improved subthreshold swing of 92.5mV/decade at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> = 1.0V, and a positive threshold voltage shift of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> = 300 mV. The ft of 260GHz and fmax of 440GHz were hardly influenced by the surface treatments while the noise performances were improved obviously. Two orders of magnitude smaller input noise spectral density shows the method of surface treatment can effectively reduce the surface defects and significantly improve the surface of gate recess of InAlAs/InGaAs InP-based HEMTs.

Improved interfacial properties of HfGdON gate dielectric Ge MOS capacitor by optimizing Gd content**Project supported by the National Key Research and Development Program of China (Grant No. 2018YFB2200500) and the National Natural Science Foundation of China (Grant Nos. 61851406 and 61274112).

High-quality dielectric/Ge interface and low gate leakage current are crucial issues for high-performance nanoscaled Ge-based complementary metal–oxide–semiconductor (CMOS) device. In this paper, the interfacial and electrical properties of high-k HfGdON/LaTaON stacked gate dielectric Ge metal–oxide–semiconductor (MOS) capacitors with different gadolinium (Gd) contents are investigated. Experimental results show that when the controlling Gd content is a suitable value (e.g., ∼ 13.16%), excellent device performances can be achieved: low interface-state density (6.93 × 1011 cm−2 · eV−1), small flatband voltage (0.25 V), good capacitance–voltage behavior, small frequency dispersion, and low gate leakage current (2.29× 10−6 A/cm2 at Vg = Vfb + 1 V). These could be attributed to the repair of oxygen vacancies, the increase of conduction band offset, and the suppression of germanate and suboxide GeOx at/near the high k/Ge interface by doping suitable Gd into HfON.

Robust sandwiched fluorinated graphene for highly reliable flexible electronics

The high sensitivity of graphene to the surface condition of the gate dielectric layer and its poor van der Waals adhesion with a flexible substrate result in interfacial sliding and fracturing of graphene at low strains, making the successful utilization of pristine graphene (PG) in flexible electronics challenging. Here, we report a facile method for the fabrication of flexible graphene field effect transistors (F-GFETs) using sandwiched fluorinated graphene (FG). The “FG-PG-FG” sandwich structure shows a high optical transparency (>94%) with an average carrier mobility above 340 cm2/V·s, higher than that obtained when GO and Ion gel were used as gate dielectric materials on F-GFETs and a relatively low gate leakage current of ~160 pA. Furthermore, we observed a high mechanical stability, retaining >88% of the original current output against bending deformation of up to 6 mm and >77% after 200 bending cycles by applying a tensile strain of 1.56%, compared to the control sample. This improved performance is attributed to the fact that the sandwiched FG provides a good dielectric environment by tuning the C/F ratio, which tightly fixes the PG under strain. These findings provide a new route for the future development of graphene-based flexible electronics.

High-performance InAlN/GaN HEMTs on silicon substrate with high fT × Lg

We report an 80 nm gate-length In0.17Al0.83N/GaN high-electron mobility transistor (HEMT) on silicon substrate with a record low gate leakage current of 7.12 × 10−7 A mm−1, a record high on/off current ratio of 1.58 × 106, and a steep subthreshold swing of 65 mV dec−1, which are excellent features among the reported InAlN/GaN HEMTs on Si. Due to the excellent DC performance, a current gain cutoff frequency fT of 200 GHz is achieved, resulting in fT × Lg = 16 GHz μm for GaN HEMTs on Si which to the best of our knowledge is a new record.

Post-Annealing on the Ohmic Contact and Gate Recess Simultaneously in AlGaN/GaN MIS-Hemt

AlGaN/GaN HEMTs have been widely used in RF power amplifiers and power switching circuits. The primary reasons are because of high electron mobility and high breakdown electric field in GaN materials. Moreover, a 2DEG formed from polarization effects at the AlGaN/GaN heterojunction enables a low channel resistance and thus a low on-resistance. However, devices fabricated with the inherent 2DEG channel are depletion-mode FETs. For practical applications, it prefers an enhancement-mode (E-mode) device with the threshold voltage > 0 V. The common approaches to implement an E-mode device include gate recess, p-GaN layer, and F-ion treatment. The p-GaN layer used to deplete the channel underneath the gate at 0V and induce 2DEG with positive gate bias. But the gate swing voltage is limited due to the gate leakage current. The F-ion treatment under the gate has a reliability issue. The gate recess combined an insulator layer device (MIS-HEMT) is practical for E-mode operation to achieve the high gate voltage swing and low gate leakage current. However, the damage from gate recess and the relatively poor MOS interface between GaN and the insulators are problems to be overcome. Conventional E-mode MIS-HEMT fabrication starts with high-temperature annealing to ohmic contact then gate recess for gate metallization. Second annealing is required to reduce the gate recess damage. In this study, we did not anneal the device for ohmic contact first but anneal the device after the gate recess with suitable conditions to achieve a good ohmic contact and reduce recess damage. By the post-annealing on the ohmic contact and gate recess simultaneously, the interfacial density of state (Dit) of MIS in the E-mode MIS-HEMT was improved with low contact resistance. The epitaxial layers were grown by MOCVD including a ~3900-nm buffer layer, a 325-nm GaN channel layer, a 1-nm AlN spacer layer, a 21.5-nm Al0.25Ga0.75N barrier, and a 4.1-nm in-situ SiN cap layer. First, device isolation was implemented by ICP etching down to the buffer layer. The ohmic contact was made by the deposition of Ti/Al/Ni/Au (25/125/45/55 nm) without annealing. Using ICP to perform gate recess, and then annealed by RTA at 875 °C in an N2 circumstance for 40 s. The gate dielectric SiN was deposited at 300 °C by PECVD, then annealed by RTA at 450 °C for 1 min in an N2 circumstance. Ni/Ti/Al/Ti/Au (30/25/250/25/200 nm) metal stack was used to form gate metal contact. Finally, the devices were passivated by a 200-nm SiN deposited by PECVD. The C-V and I-V characteristics of fabricated devices were measured by the Agilent B1500A and B1505A. The leakage current was reduced in the devices with proposed annealing. Double sweep C-V characteristics at 100-kHz of devices with proposed annealing step show a smaller hysteresis and lower flat band voltage shift than devices with traditional ohmic annealing. Moreover, the frequency dependent C-V measurements show that device with proposed annealing step effectively reduces the dispersion phenomenon. Conductivity method was applied to extract interface trap density as a commonly used analytical method for the III-V materials [3]. The calculated Dit of the device with proposed annealing step shows lower interface trap density than the device with traditional ohmic annealing. The calculated Dit was reduced from 7.1E12 to 4.8E12 eV-1cm-2. As a result, annealing after gate recess can really improve the interface quality and reduce the damage from dry etching, and form good ohmic contact without the extra annealing step. Figure 1

H2 High Pressure Annealed Y-Doped ZrO2 Gate Dielectric With an EOT of 0.57 nm for Ge MOSFETs

We report on the impact of H2 high pressure annealing (H2-HPA) on a Y-doped ZrO2 (Y-ZrO2)/GeOx/Ge gate stack. In this paper, compared to conventional forming gas annealing (FGA), the H2-HPA increased the k-value of the Y-doped ZrO2 gate dielectric to as high as 47.8 by enhancing the crystallization of the Y-ZrO2. This process can achieve an aggressively scaled equivalent oxide thickness (EOT) of 0.57 nm with an extremely low gate leakage current (Jg) of $ {4.5} \times {10}^{- {6}}$ A/cm2. In addition, the H2-HPA effectively passivated the dangling bonds and reduced the interface trap density (Dit) to as low as ${3.4} \times {10}^{ {11}}$ eV−1cm−2. The Ge pMOSFETs of the Y-ZrO2 with H2-HPA led to a ~ 70% improvement in the effective hole mobility compared to the counterpart device with the conventional FGA. The device with H2-HPA also showed an improved subthreshold swing (SS) value of 93 mV/dec compared to that with the FGA (135 mV/dec).

Self-Aligned Top-Gate Amorphous InGaZnO TFTs With Plasma Enhanced Chemical Vapor Deposited Sub-10 nm SiO2 Gate Dielectric for Low-Voltage Applications

In this letter, self-aligned top-gate (SATG) amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) with an 8.62-nm SiO2 gate dielectric grown by conventional plasma enhanced chemical vapor deposition (PECVD) at 300 °C are fabricated. The results show that the ultrathin PECVD SiO2 film has excellent dielectric properties, such as a low leakage current density of 10−8 A/cm2 at 2 MV/cm, a high breakdown electric field of 9.3 MV/cm, and an almost independent capacitance of bias frequency. The fabricated SATG a-IGZO TFTs with the ultrathin SiO2 gate dielectric exhibit high electrical performances, with major parameters, including a low gate leakage current of 10−13 A, a small subthreshold swing value of 124 mV/decade, a decent field-effect mobility of 10.13 cm2/ $\text{V}\cdot \text{s}$ , and a high ON/OFF current ratio up to 108. Furthermore, the TFTs also show a good electrical stability under positive and negative gate bias stresses.

MOCVD grown β-Ga2O3 metal-oxide-semiconductor field effect transistors on sapphire

We fabricated β-Ga2O3:Si metal-oxide field-effect transistors (MOSFETs) on c-plane sapphire substrates which typically showed maximum drain current of 100 mA mm−1. β-Ga2O3:Si thin films were realized on c-plane sapphire substrates through a combination of metalorganic chemical vapor deposition and post-annealing. The MOSFET device presented excellent on/off drain current ratio of ∼1011 with very low gate leakage current, sharp pinch off behavior, and a breakdown voltage of 400 V at VG = −40 V. The growth and fabrication of β-Ga2O3:Si MOSFETs on c-plane sapphire is valuable to its demonstration of the great potential for future high-power electronic devices.

Probing the Field-Effect Transistor with Monolayer MoS2 Prepared by APCVD.

The two-dimensional materials can be used as the channel material of transistor, which can further decrease the size of transistor. In this paper, the molybdenum disulfide (MoS2) is grown on the SiO2/Si substrate by atmospheric pressure chemical vapor deposition (APCVD), and the MoS2 is systematically characterized by the high-resolution optical microscopy, Raman spectroscopy, photoluminescence spectroscopy, and the field emission scanning electron microscopy, which can confirm that the MoS2 is a monolayer. Then, the monolayer MoS2 is selected as the channel material to complete the fabrication process of the back-gate field effect transistor (FET). Finally, the electrical characteristics of the monolayer MoS2-based FET are tested to obtain the electrical performance. The switching ratio is 103, the field effect mobility is about 0.86 cm2/Vs, the saturation current is 2.75 × 10−7 A/μm, and the lowest gate leakage current is 10−12 A. Besides, the monolayer MoS2 can form the ohmic contact with the Ti/Au metal electrode. Therefore, the electrical performances of monolayer MoS2-based FET are relatively poor, which requires the further optimization of the monolayer MoS2 growth process. Meanwhile, it can provide the guidance for the application of monolayer MoS2-based FETs in the future low-power optoelectronic integrated circuits.

Room‐Temperature Fabrication of High‐Quality Lanthanum Oxide High‐κ Dielectric Films by a Solution Process for Low‐Power Soft Electronics

AbstractHigh‐quality dielectric films are indispensable for field‐effect electronic devices to provide high electrical performance. However, deposition of high‐quality dielectric films on flexible substrate remains a challenging task, which greatly limits the electrical performance of flexible or organic field‐effect devices. A room‐temperature deep ultraviolet (DUV) irradiation process is proposed for densification of solution‐processed La2O3 films. It is found that room‐temperature DUV‐La2O3 films not only exhibit leakage and dielectric properties that are comparable to those of high‐temperature annealed‐La2O3 films, but also have very smooth and clean surfaces and excellent bending strain tolerance. The fabricated La2O3 films exhibit a wide band gap (5.78 eV), high dielectric constant (12.68), low leakage density (8.8 × 10−7 A cm−2 at 2 MV cm−1), and high breakdown field strength (3.5 MV cm−1). Organic thin‐film transistors (OTFTs) based on high‐quality solution‐processed La2O3 gate dielectrics show a low operation voltage (≤3 V), low gate leakage current (&lt;10−9 A), and high Ion/Ioff ratio (&gt;105). Based on these room‐temperature‐fabricated high‐performance OTFTs, low‐voltage complementary integrated circuits are successfully fabricated, including complementary inverters and NAND gate circuits. The results demonstrate that room‐temperature DUV‐processed La2O3 films are ideal gate dielectric materials for future flexible and low‐power‐consumption electronic devices.

Ga2O3 metal-oxide-semiconductor field effect transistors on sapphire substrate by MOCVD

Si-doped gallium oxide (Ga2O3) thin films were grown on a c-plane sapphire substrate by metalorganic chemical vapor deposition (MOCVD) and fabricated into metal oxide semiconductor field effect transistors (MOSFETs). The Ga2O3 MOSFETs exhibited effective gate modulation of the drain current with a complete channel pinch-off for VG < −25 V, and the three-terminal off-state breakdown voltage was 390 V. The device shows a very low gate leakage current (∼50 pA mm−1), which led to a high on/off ratio of ∼108. These transistor characteristics were stable from room temperature to 250 °C.

Gate Current Reduction and Improved DC/RF Characteristics in GaN-Based MOS-HEMTs Using Thermally Grown TiO2 as a Dielectric

This paper demonstrates a reduction in the gate leakage current and improvement in transistor characteristics in thermally grown TiO2/AlGaN/GaN heterostructure-based metal–oxide–semiconductor high-electron-mobility transistors (MOS-HEMTs). In contrast to the conventional AlGaN/GaN HEMTs, thermionic field emission through gate is not the dominant current transport mechanism for the thermally grown TiO2/AlGaN interface. The gate current is greatly affected by the properties of the oxide material and oxide–semiconductor interface in addition to the property of the barrier layer. The MOS-HEMTs with a 3.4-nm-thick TiO2 gate insulator exhibits a low gate leakage current of 10−8 Acm−2, which leads to superior device performances in terms of saturation drain current, peak transconductance, subthreshold swing, and unity gain frequency of 620 mA/mm, 158 mS/mm, 75 mV/decade, and 7 GHz, respectively, for a 400-nm gate length device. This is further augmented by an increase in ON/OFF ratio to ${5}\times {10}^{{8}}$ and a large reduction in the subthreshold leakage current by at least two orders of magnitude in comparison to that of a control HEMT. Trap-assisted tunneling (TAT) and Poole–Frenkel (PF) emission are found to be the dominant current mechanisms for gate leakage at high temperatures and moderate electric field. The activation energy of traps in PF emission is found to be 0.49 eV, and the extracted trap energy levels for the TAT are found to be in the range of 1.7–2.2 eV. The reverse bias current is found to saturate at high voltages when the field across the diode also saturates. The transistor characteristics improvement is largely ascribed to an increase in 2-D electron gas (2DEG) density.

Enhanced Device Stability of Ionic Gating Molybdenum Disulfide Transistors

The application of ion gels as gate dielectrics having an excellent mechanical flexibility and high capacitance to molybdenum disulfide (MoS2) devices has been extensively studied; however, some issues remain unaddressed with regard to device stability such as gate leakage current, hysteresis, and bias stress instability. This study suggests a fabrication process for the ionic gating of the MoS2 device to enhance the device stability by laminating the ion gel film onto the MoS2 transistor using a cut‐and‐stick method and adding a passivation layer to remove unintentional parasitic capacitances generated by the capacitive coupling effect. The ionic gating MoS2 transistor fabricated via this process operates at a low voltage (&lt;1 V) and exhibits superior electrical characteristics such as low gate leakage currents (≈10−11 A), high on–off ratio (&gt;106), and low hysteresis (&lt;0.05 V). To further investigate the device stability, bias stress instability of the ionic gating MoS2 transistor is examined. The charge‐trapping mechanism is the main cause of threshold voltage shifts under gate bias stress.

Normally-off AlGaN/GaN MIS-HEMT with low gate leakage current using a hydrofluoric acid pre-treatment

We demonstrate the electrical performances of an AlGaN/GaN metal–insulator–semiconductor high electron mobility transistor (MIS-HEMT) with low gate leakage current (Ig). A low gate leakage current as low as the order of 10−11 A/mm was achieved from normally-off MIS-HEMT device (Vth = 2.16 V) with a partially recessed gate, fluorine treatment, and ALD Al2O3 gate dielectric layer. The gate leakage current decrease is attributed to the pre-treatment of the gate region with hydrofluoric acid (HF) and deionized water (DI) solution, which acts to remove the native oxide layer and thus decrease interface traps. X-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM) analyses demonstrate that the AlGaN surfaces are modified such that the surface roughness and native oxide introduced by the treatments used to achieve normally-off operation are remedied with the use of the pre-treatment.

A Planar Distributed Channel AlGaN/GaN HEMT Technology

This brief presents AlGaN/GaN high electron mobility transistor (HEMT) devices with improved thermal and dc current–voltage ( ${I}$ – ${V}$ ) performance using a novel method of obtaining a distributed channel device, i.e., the total semiconductor area between the ohmic contacts comprise conducting and nonconducting regions. A novel oxygen (O2) plasma treatment technique is used to realize the inactive or nonconducting regions. Multifinger devices with 1-mm gate periphery exhibit extremely low gate leakage currents below $0.2~\mu \text{A}$ /mm at a gate voltage of −20 V and an increase in the saturated output current by 14% at 20-V drain voltage. Moreover, performed dc ${I}$ – ${V}$ measurements at various ambient temperatures show that the proposed method not only increases the saturated output currents by over 10% for ${1} \times {100}\,\,\mu \text{m}^{{2}}$ gate devices but also significantly reduces their knee walkout voltage from 6 to 3 V at 300 K. These results show that this device design approach can exploit further the potential of the GaN material system for transistor applications.

Enhancement-mode AlGaN channel high electron mobility transistor enabled by p-AlGaN gate

This work exhibits the ability to shift the threshold voltage of an Al0.45Ga0.55N/Al0.3Ga0.7N high electron mobility transistor through the implementation of a 100 nm thick p-Al0.3Ga0.7N gate. A maximum threshold voltage of +0.3 V was achieved with a 3 μm gate length. In addition to achieving enhancement-mode operation, this work also shows the capability to obtain high saturated drain current (&amp;gt;50 mA/mm), no gate hysteresis, high ION,MAX/IOFF,MIN ratio of &amp;gt;109, and exceptionally low gate leakage current of 10−6 mA/mm even under high forward bias of Vgs = 8 V.

Reactive evaporation of SiOx films for passivation of GaN high-electron-mobility transistors

The surface passivation effects of silicon suboxide (SiOx) prepared by the reactive evaporation of silicon monoxide in oxygen atmosphere on the performance of AlGaN/AlN/GaN high-electron-mobility transistors (HEMTs) have been investigated. SiOx films with different oxygen contents (1.10 ≤ x ≤ 1.71) and root-mean-square (RMS) roughnesses (0.55 ≤ RMS ≤ 1.01 nm) were prepared under residual pressures from 1 × 10−6 to 6 × 10−4 Torr. Hall measurements revealed obvious increases in the product of sheet carrier concentration and electron mobility after the passivation. Accordingly, increases in drain current and transconductance were observed for all the SiOx passivated HEMTs. Both the gate and drain leakage currents first decreased and then increased with the increase of oxygen content. The lowest gate leakage current was observed in the devices with SiO1.23 passivation, and it was almost 20 times lower than that of the unpassivated devices. The same devices also exhibited the lowest current collapse and off-state drain current. The variations in leakage currents as a function of the residual pressure were found to correlate with the surface roughness of the passivation layer. Finally, the breakdown voltage of the SiO1.23 passivated HEMTs increased to 151 V, up from 99 V in unpassivated devices.

Electrical Characteristics and pH Response of a Parylene-H Sensing Membrane in a Si-Nanonet Ion-Sensitive Field-Effect Transistor.

We report the electrical characteristics and pH responses of a Si-nanonet ion-sensitive field-effect transistor with ultra-thin parylene-H as a gate sensing membrane. The fabricated device shows excellent DC characteristics: a low subthreshold swing of 85 mV/dec, a high current on/off ratio of ~107 and a low gate leakage current of ~10−10 A. The low interface trap density of 1.04 × 1012 cm−2 and high field-effect mobility of 510 cm2V−1s−1 were obtained. The pH responses of the devices were evaluated in various pH buffer solutions. A high pH sensitivity of 48.1 ± 0.5 mV/pH with a device-to-device variation of ~6.1% was achieved. From the low-frequency noise characterization, the signal-to-noise ratio was extracted as high as ~3400 A/A with the lowest noise equivalent pH value of ~0.002 pH. These excellent intrinsic electrical and pH sensing performances suggest that parylene-H can be promising as a sensing membrane in an ISFET-based biosensor platform.