Low-frequency Pole Research Articles

A Low-Power Capacitorless LDO Regulator with Transient Enhancement Structure

In this paper, a portable low-power low dropout regulator (LDO) with no output capacitance has been designed in 0.18-[Formula: see text]m CMOS technology. In this paper, a PMOS power transistor is used and combined with an overshoot and undershoot suppression circuit to improve the transient response of the circuit. A modified Class-AB operational transconductance amplifier (OTA) is used to reduce power consumption and act as an error amplifier to eliminate low frequency poles. At the same time, a super source follower and a Miller capacitor are used for frequency compensation of the system. Finally, the system can provide a stable voltage for a load step from 0.2 to 25[Formula: see text]mA in 500[Formula: see text]ns edge-time for 140[Formula: see text]pF-load capacitance. The test results show that the circuit achieves a good voltage regulation rate and high transient response.

Wideband SiGe-HBT Low-Noise Amplifier with Resistive Feedback and Shunt Peaking.

In this work, the design of a wideband low-noise amplifier (LNA) using a resistive feedback network is proposed for potential multi-band sensing, communication, and radar applications. For achieving wide operational bandwidth and flat in-band characteristics simultaneously, the proposed LNA employs a variety of circuit design techniques, including a voltage-current (shunt-shunt) negative feedback configuration, inductive emitter degeneration, a main branch with an added cascode stage, and the shunt-peaking technique. The use of a feedback network and emitter degeneration provides broadened transfer characteristics for multi-octave coverage and a real impedance for input matching, respectively. In addition, the cascode stage pushes the band-limiting low-frequency pole, due to the Miller capacitance, to a higher frequency. Lastly, the shunt-peaking approach is optimized for the compensation of a gain reduction at higher frequency bands. The wideband LNA proposed in this study is fabricated using a commercial 0.13 μm silicon-germanium (SiGe) BiCMOS process, employing SiGe heterojunction bipolar transistors (HBTs) as the circuit's core active elements in the main branch. The measurement results show an operational bandwidth of 2.0-29.2 GHz, a noise figure of 4.16 dB (below 26.5 GHz, which was the measurement limit), and a total power consumption of 23.1 mW under a supply voltage of 3.3 V. Regarding the nonlinearity associated with large-signal behavior, the proposed LNA exhibits an input 1-dB compression (IP1dB) point of -5.42 dBm at 12 GHz. These performance numbers confirm the strong viability of the proposed approach in comparison with other state-of-the-art designs.

Tunable CMOS Pseudo-Resistors for Resistances of Hundreds of GΩ

This paper presents the design of tunable CMOS pseudo-resistors aimed at achieving large and predictable resistance values. Instrumental to the proposed pseudo-resistor is the design of current sources of extremely low currents and transistors operating in subthreshold. The effects of the leakage currents of reverse-biased pn-junctions on the pseudo-resistor resistance are also evaluated. The proposed pseudo-resistor circuit was validated while in use as part of a filter integrated in a 180 nm CMOS process. Pseudo-resistors with resistances between 180 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{G}\Omega $ </tex-math></inline-formula> and 700 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{G}\Omega $ </tex-math></inline-formula> were employed to obtain low-frequency poles of a band-pass filter adjustable from 0.6 Hz to 2 Hz.

Research and Improvement on Active Compliance Control of Hydraulic Quadruped Robot

This paper focuses on active compliance control of hydraulic quadruped robot, especially the analysis of the inner-loop of the coupled system. Current researches on active compliance control regard the bandwidth of the inner loop of the system as infinite, while ignoring that the extra-load will cause the inner-loop response characteristics to deteriorate when the leg is in the stance phase. In this work, we first briefly introduced the structure of the robot, and its kinematics and dynamics are analyzed. Next, the robot’s active compliance control framework is established, and the inner-loop two-cylinder coupling system is analyzed in depth. It can be concluded that the existence of low frequency poles in the system is the main reason for the poor response characteristics. Then through the analysis of the state equation and transfer function matrix of the multi-input multi-output system, we show that the equivalent hydraulic spring stiffness (EHSS) is the main factor affecting the zero-pole distribution. Furthermore, we optimize the structure to increase the EHSS to improve the response characteristics of the system. Finally, the co-simulation platform and single-leg experiment bench are introduced. The simulation and experimental results show that the response speed of the inner-loop control is significantly improved after optimization, and the robot with active compliance control strategies can significantly reduce the impact of the foot.

An Improved Linear Model for High-Frequency Class-DE Resonant Converter Using the Generalized Averaging Modeling Technique

As the operating frequency of power converters increases, the passive component values likewise decrease. This results in the effect of the parasitic components becoming more prominent, leading to significant modeling errors if not considered. For resonant converters, this especially becomes a problem at high frequencies. This article presents a reduced model for a class-DE series resonant converter based on generalized averaging that incorporates the relevant parasitics and uses multiple harmonics to obtain an accurate linear model. Comparison between the proposed model, a prior art, and a prototype converter running at 1 MHz is conducted, and a PI controller is designed based on each model and tested. The results show that the parasitics have a significant impact on the dc gain and dynamics of the converter and that the proposed model improves on the prior art by reducing the dc-gain error by more than 7 dB, and the error in the low-frequency pole from 168% to 16.9%. Furthermore, the PI controller designed on the prior art was found to have more than 40 times larger overshoot in the control signal when measured compared with the model prediction, while the controller based on the proposed model showed correct performance when simulated and measured.

Enhanced Positioning Bandwidth in Nanopositioners via Strategic Pole Placement of the Tracking Controller

Tracking triangular or staircase trajectories is a challenge for a piezo-driven nanopositioner due to vibration problems. The piezo-driven nanopositioner is a lightly-damped system because of its mechanical construction. These reference trajectories are high-frequency components that tend to excite the mechanical resonance of the nanopositioner, causing vibration and thus affecting the accuracy. The Integral Resonant Controller (IRC) is employed to damp the resonance and thereby furnish a larger gain margin for a high-gain tracking controller to be implemented. The IRC, however, introduces a low-frequency pole. Due to other control issues, such as hysteresis nonlinearity, Integral (I) or Proportional Integral (PI) tracking control is used as a tracking loop to address uncertainties (hysteresis). The traditional method using a PI controller has a limited positioning bandwidth. This paper presents the strategic zero placement of the PI controller to enhance the positioning bandwidth, thereby overcoming the limitations of tracking error. Using experimental validations to confirm the feasibility of the proposed method, it is shown that significant improvement regarding bandwidth and disturbance rejection are reported.

A Simplified Equivalent Model for the Analysis of Low-Frequency Stability of Multi-Bus DC Microgrids

In this paper, a simplified equivalent model is proposed to investigate low-frequency (LF) stability of dc microgrids. This is done by using an impedance-based approach considering exact models of microgrid components. In order to apply the impedance-based stability criterion, a multi-bus dc microgrid is first categorized as multiple interconnected single-bus dc microgrids. Then, each single-bus system is classified into two subsystems: subsystem#1 which only includes voltage-controlled (VC) DGs and subsystem#2 which includes the rest of the dc microgrid components. It is shown that due to the absence of LF interaction between subsystems, the dominant LF modes of a single-bus dc microgrid are mainly determined by the droop controllers of VC-DGs. The studies also show that the droop controller of each VC-DG accounts for the LF complex conjugate zeros at the output impedance of each VC-DG; and the internal interaction among these zeros can result in LF poles, which are the origin of LF current/power oscillations in dc microgrids. Through further analyses, it is shown that our findings for single-bus dc microgrids can be extended to any multi-bus dc microgrid as well. Owing to this fact, a simplified equivalent model, which can lead to the order reduction of the overall system, is proposed for the analysis of LF stability of dc microgrids. Thanks to the simplicity and generality of the proposed equivalent model, the effect of different parameters, such as number of VC-DGs, internal voltage controller of VC-DGs, and the microgrid line impedances on the LF stability of dc microgrids is comprehensively investigated. The studies also show that the LF stability of a dc microgrid is approximately independent of droop types (current or power). A complete set of simulation studies are provided which further supports the effectiveness of the proposed model.

Pole/Zero Design of Agonist/Antagonist Actuation

Objective: This brief analyzes the open-loop dynamics of coupled (dedicated) and decoupled tendon tension control methods in an agonist/antagonist (AA) actuator pair, a fundamental control unit used in orthopedic testbeds known as joint motion simulators (JMSs). Methods: A linear mathematical model of an AA actuator pair is derived. Transfer functions from tendon tension control signal to tendon tension and joint position are derived. Sources of key dynamics are explained. Results: The system’s dynamic model shows that both the dedicated and decoupled approaches have a low-frequency pole pair, a low-frequency zero pair, and a mid-range zero pair. A frequency domain identification of the flexion/extension axis of an existing elbow JMS validates the locations of these dynamics. The interaction between tendon tension control and joint position is shown to be controllable in decoupled control, but not in dedicated control. The bandwidth reduction due to the low-frequency pole pair and low-frequency zero pair are shown to be controllable in decoupled control, but not in dedicated control. Conclusion: Decoupled control is superior to dedicated control for AA actuator pairs in JMS designs because it reduces actuator interaction and has a larger tension control bandwidth. Significance: This analysis describes the sources of the dynamics seen in the open-loop frequency response of both methods and shows the superiority of the decoupled method in tension control bandwidth and in lack of interactions with position control.

Low quiescent current capacitorless small gain stages LDO with controlled pass transistors

A low quiescent current 180-nm output-capacitorless low-dropout regulator with small-gain stages (SGSs) is presented in this paper. The proposed technique permits the regulator to distribute the load current into two power transistors depending on the demand of the load using a controller based on load variation criterion. SGSs are introduced to enhance loop gain without low-frequency poles. The proposed architecture does not require compensation capacitor. Thus, the active chip area is reduced to 73.59 µm × 36 µm. The measured results have shown that the fabricated circuit consumes a quiescent current of 1.8 µA at no load, regulating the output at 1 V with maximum output current of 50 mA from a voltage supply of 1.2 V. It achieves full range stability from 0 to 50 mA load current at a maximum 100 pF load capacitor.

Capacitive cancellation technique in design of CMOS low noise amplifier for ultrasound applications

In this paper active capacitive cancellation technique, is proposed for alleviating the side effects of the parasitic capacitance of the ultrasound piezoelectric probe and cable. This parasitic capacitance imposes a low frequency pole at the input of the circuit, which deteriorates the noise and the transient response of the circuit, crucial parameters for ultrasound imaging systems. Employing a capacitor in a positive feedback loop of a well-defined gain amplifier actively cancels the parasitic capacitance at the input of the amplifier. Making use a binary weighted capacitor bank keeps the circuit safely away from the instability problems due to the variations of process and corner cases. For verification of the proposed technique, the circuit was designed and simulated in a 0.18 µm, 1.8 V CMOS technology. Simulation results show that this technique for equal power consumption presents a better noise performance and more than 100% higher bandwidth compared to the conventional active resistive termination approach.

Low-Order Damping and Tracking Control for Scanning Probe Systems

This article describes an improvement to integral resonance damping control (IRC) for reference tracking applications such as Scanning Probe Microscopy and nanofabrication. It is demonstrated that IRC control introduces a low-frequency pole into the tracking loop which is detrimental for performance. In this work, the location of this pole is found analytically using Cardano's method then compensated by parameterizing the tracking controller accordingly. This approach maximizes the closed-loop bandwidth whilst being robust to changes in the resonance frequencies. The refined IRC controller is comprehensively compared to other low-order methods in a practical environment.

Detection of Secondary-Path Irregularities in Active Noise Control Headphones

Headphones with adaptive feedback ANC show a good performance if the secondary-path is well known. The secondary-path however changes considerably if the headphones are lifted. In this paper, it is shown that these changes mainly affect the low frequencies of the secondary-path and that the resulting low-frequency poles of the system cause instabilities. However, the changes in the secondary-path can be detected via low-frequency changes of the adaptive filter. A cost-efficient algorithm in the time-domain is developed to detect and react to these changes in order to keep the ANC system stable. Experimental results show that the algorithm yields the desired ANC performance in the regular use case and still avoids instabilities even during sudden changes in the secondary-path.

Adaptive high‐bandwidth digitally controlled buck converter with improved line and load transient response

Digitally controlled switching converter suffers from bandwidth limitation because of the additional phase delay in the digital feedback control loop. To overcome the bandwidth limitation without using a high sampling rate, this study presents an adaptive third-order digital controller for regulating a voltage-mode buck converter with a modest 2× oversampling ratio. The phase lag because of the analogue-to-digital converter (ADC) conversion time delay is virtually compensated by providing an early estimation of the error voltage for the next sampling time instant, enabling a higher unity-gain bandwidth without compromising stability. An additional pair of low-frequency pole and zero in the third-order controller increases the low-frequency gain, resulting in faster settling time and smaller output voltage deviation during line transient. Both simulation and experimental results demonstrate that the proposed adaptive third-order controller reduces the settling time by 50% in response to a 1 V line transient and 30% in response to a 600 mA load transient, compared to the baseline static second-order controller. The fastest settling time is measured to be about 11.70 μs, surpassing the transient performance of conventional digital controllers and approaching that of the state-of-the-art analogue-based controllers.

A LDO REGULATOR WITH PRE-REGULATOR AND MULTI-ZERO AND MULTI-POLE FREQUENCY COMPENSATION

A low dropout (LDO) linear regulator with pre-regulator is presented in this paper. The LDO is suitable for wide power supply of 4.5–28 V for smart battery system applications to generate a stable 1.8 V output. The proposed LDO provides high stability by pre-regulator for a rough 3.3 V as internal power supply and multi-zero and multi-pole frequency compensation. The scheme of combining of using output capacitor to set a dominant pole, utilizing a buffer stage to avoid generation of low-frequency pole, introducing an additional zero, is presented to stabilize the regulator loop for various load conditions and wide supply range. Besides, parasitic poles in high frequency can be compensated by feed-forward compensation and mirror-pole compensation.

A Low-Power Fast-Transient 90-nm Low-Dropout Regulator With Multiple Small-Gain Stages

A power-efficient 90-nm low-dropout regulator (LDO) with multiple small-gain stages is proposed in this paper. The proposed channel-resistance-insensitive small-gain stages provide loop gain enhancements without introducing low-frequency poles before the unity-gain frequency (UGF). As a result, both the loop gain and bandwidth of the LDO are improved, so that the accuracy and response speed of voltage regulation are significantly enhanced. As no on-chip compensation capacitor is required, the active chip area of the LDO is only 72.5 μm × 37.8 μm. Experimental results show that the LDO is capable of providing an output of 0.9 V with maximum output current of 50 mA from a 1-V supply. The LDO has a quiescent current of 9.3 μA, and has significantly improvement in line and load transient responses as well as performance in power-supply rejection ratio (PSRR).

Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture

A supply-regulated phase-locked loop (PLL) employs a split-tuned architecture to decouple the tradeoff between supply-noise rejection performance and power consumption. By placing the regulator in the low-bandwidth coarse loop, the proposed PLL architecture allows us to maximize its bandwidth to suppress the oscillator phase noise with neither the power supply-noise rejection nor the power dissipation of the regulator being affected. A replica-based regulator introduces a low-frequency pole in its supply-noise transfer function and avoids degradation of supply-noise rejection beyond the regulator-loop's dominant pole frequency. The prototype PLL fabricated in a 0.18 mum digital CMOS process operates from 0.5 to 2.5 GHz. At 1.5 GHz, the proposed PLL achieves 1.9 ps long-term rms jitter and a worst case supply-noise sensitivity of -28 dB (0.5 rad/V), an improvement of 20 dB over conventional solutions, while consuming 2.2 mA from a 1.8 V supply.

A Methodology for Fast VSWR Protection Implemented in a Monolithic 3-W 55% PAE RF CMOS Power Amplifier

In this paper, the protection of CMOS power amplifiers against load mismatch is addressed. To this purpose, a closed-loop protection circuit is proposed, which is based on a novel current-mode detection and comparison technique. The circuit allows a faster protection lock-in, by enabling peak detection and loop frequency compensation to be performed at the same circuit node, thus reducing the number of low-frequency poles and improving loop bandwidth. The effectiveness of the method is demonstrated through the implementation of a monolithic 0.25-mum 2-V CMOS power amplifier for GSM applications, which can deliver a 3-W output power with 55% overall PAE. The amplifier is able to sustain a 20:1 load VSWR at full power. Excellent RF performance and VSWR ruggedness are hence attained simultaneously, despite a simple common-emitter power stage is used. An experimental reliability assessment allowed the cognizant choice of the maximum drain-gate stress that could be tolerated. Device degradation was characterized by operating a power gain cell at RF, under real-world load and power conditions. Analysis of the degradation data enabled the design of an efficient, yet provably reliable, power amplifier.

A Charge-Based Low-Power High-SNR Capacitive Sensing Interface Circuit

This paper describes a low-power approach to capacitive sensing that achieves a high signal-to-noise ratio. The circuit is composed of a capacitive feedback charge amplifier and a charge adaptation circuit. Without the adaptation circuit, the charge amplifier only consumes 1 μW to achieve the audio band SNR of 69.34dB. An adaptation scheme using Fowler-Nordheim tunneling and channel hot electron injection mechanisms to stabilize the DC output voltage is demonstrated. This scheme provides a very low frequency pole at 0.2Hz. The measured noise spectrums show that this slow-time scale adaptation does not degrade the circuit performance. The DC path can also be provided by a large feedback resistance without causing extra power consumption. A charge amplifier with a MOS-bipolar pseudo-resistor feedback scheme is interfaced with a capacitive micromachined ultrasonic transducer to demonstrate the feasibility of this approach for ultrasound applications.

An adaptive clutter rejection method based on AR model in color flow imaging

The ultrasound Doppler signal scattered from blood is heavily corrupted by the clutter signal reflected from slowly moving muscular tissue. The Doppler frequency shift of blood flow and clutter in different parts of human body greatly changes. Therefore, if a fixed wall filter is selected, the optimal filtering effect can not be attained. An adaptive clutter rejection method is proposed in this paper, which consists of a weak clutter rejector and a 2-order AR estimator. The clutter and blood power thresholds were preliminary defined in the weak clutter rejector. The echo power is compared with the two pre-defined thresholds, and the result was used to select an appropriate wall filter. The output of the weak clutter rejector is estimated by a 2-order AR estimator and two poles are acquired. The low frequency pole denotes the clutter signal and the high frequency pole denotes the blood signal. Before the AR estimation, a static signal is added to avoid producing split spectral peaks. It is illustrated in the simulation that the proposed method can detect the slower blood flow with smaller variance compared with the traditional wall filtering method.

Realization of an adaptive voltage driver for voice coil motor

In this paper we describe a head servo-positioning system for hard disk drives (HDDs), in which the usual current command for the voice coil motor has been replaced by a simpler voltage command. This solution has proven advantages in terms of cost, since the voltage driver does not require any resistive shunt for current measurement and phase-shaping passive networks for the current controller. Also, it requires a lower pin count and can be easily implemented with a PWM power stage. The voltage driver consists of a voltage-controlled power stage, with a pre-filter placed at its input, plus a back e.m.f. feed-forward compensator. The role of the pre-filter is to provide a transfer function between input signal and VCM current as close as possible to that of a standard current loop, so providing a one-to-one replacement to standard current drivers. To achieve this, it can be shown that the filter must cancel out the low-frequency pole of the VCM, located in a position which depends on the electrical impedance of the VCM itself. This, however, may change by ±30% during HDD operations, due to self-heating and consequent variation of the VCM resistance. Such variation may lead to an unsatisfactory performance of the voltage driver, so an adaptation mechanism, capable of tracking variations of VCM coil resistance, must be set up. This paper presents an on-line estimation procedure, based on an extended Kalman filter (EKF), capable of estimating the VCM coil resistance with a high degree of accuracy. EKF, however, usually brings a high computational load, making it unsuitable for real-time, low-cost embedded applications. The paper presents two reduced-order model of the VCM, for which the EKF can be implemented with 30 and 50% less computational effort, respectively, while maintaining a good estimate of the VCM coil resistance. The paper reports experimental results of VCM resistance estimation, obtained with the proposed algorithm, running in 30 μS on a 25 MHz, fixed-point DSP. Also, the on-line estimation is used to adapt the pre-filter. Experimental results show that the servo performance with adaptive voltage driver is not affected by resistance variation and equivalent to that of the standard current driver.