Low-frequency Noise Of nMOSFETs Research Articles

Impact of RF stress on the low-frequency noise in nMOSFETs

Impact of RF stress on the low-frequency noise in nMOSFETs

DC Performance and Low Frequency Noise in n-MOSFETs using Self-Aligned Poly-Si/SiGe Gate

The characterization of an n-MOS transistor with poly-Si/SiGe Gate fabricated with the CMOS process entirely developed in the Center for Semiconductor Components (CCS) at UNICAMP is presented. The Gate layer was grown by vertical LPCVD at 800 {degree sign}C. The resultant transistor has a channel region with oxide thickness of 30 nm and self-aligned thick S/D region. The DC and Gm characteristics of poly-Si/SiGe n-MOS transistor are reported. The turn-on in the I-V characteristics increases and at a drain-to-source bias VDS of +0.1 V nMOSFETs with 3 µm gate length had peak transconductance (µS) increased as well, compared with conventional n-MOS with poly-Si gate. The Gm characteristics and low frequency noise 1/f of the n-MOS transistors are studied using devices sizes with width of 20 µm and several lengths. Promising devices for RF and microwave circuit applications, show low 1/f and high values of transconductance.

Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics

This paper focuses on the noise behavior of nMOSFETs with high- k gate dielectrics (SiON/HfO 2) with an equivalent oxide thickness of 0.92 nm and using metal (TiN/TaN) as gate material. From the linear dependence of the normalized drain noise on the gate voltage overdrive we conclude that the 1/ f noise is dictated by mobility fluctuations. This behavior is mainly ascribed to the reduced mobility due to the low interfacial thickness of 0.4 nm and the Hf-related defects. The gate current is more sensitive to RTS noise with respect to the drain current noise. Cross-correlation measurements between drain and gate noise are used as a tool for discriminating between noise mechanisms which generate different fluctuation levels at the gate and drain terminal.

WITHDRAWN: Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics

The Publisher regrets that this article is an accidental duplication of an article that has already been published in; MR 47/12 (2007) 2109-2113, doi:10.1016/j.microrel.2006.11.001 . The duplicate article has therefore been withdrawn.

Processing aspects in the low-frequency noise of nMOSFETs on strained-silicon substrates

The impact of different processing factors on the low-frequency (LF) noise of nMOSFETs fabricated in strained-silicon (SSi) substrates will be described. It is shown that the use of an SSi substrate can yield improved LF noise performance compared with standard Czochralski silicon material. This is demonstrated for both full-wafer and selective epitaxial SSi material. The lower 1/f noise points to an improved gate oxide quality, i.e., with a lower interface and bulk defect density, and is correlated with the low-field mobility or transconductance of the transistors. At the same time, it will be demonstrated that there exist defect-related LF noise mechanisms, which generally give rise to excess generation-recombination (GR) noise. Associated with this GR noise, a degradation of either the OFF-state leakage current or the mobility (transconductance) of the devices is observed. It is clear that noise is a sensitive parameter to local defectiveness and may be a useful tool for both materials' characterization and the analysis of processing-related device degradation mechanisms.

Comparative study of drain and gate low-frequency noise in nMOSFETs with hafnium-based gate dielectrics

In this paper, complementary measurements of the drain and the gate low-frequency noise are used as a powerful probe for sensing the hafnium-related defects in nMOSFETs with high-k gate stacks and polysilicon gate electrode. Drain noise measurements indicate that for low hafnium content (23%) and thin high-k thickness (2nm), the defect density at the substrate/dielectrics interface is similar to the case of conventional SiO/sub 2/. Gate-noise measurements suggest that the defect density in the bulk of the high-k gate stacks and at the gate/dielectrics interface is strongly degraded by the hafnium content.

The Low-frequency Noise in n-MOSFETs on Strained Silicon: Is There Room for Improvement?

not Available.

Impact of the device scaling on the low-frequency noise in n-MOSFETs

The impact of device scaling on modern MOS technology is discussed in terms of the random telegraph signals (RTSs) and low-frequency noise in n-MOSFETs with gradually decreased channel widths. RTSs with very large amplitude (>60%) are observed in the devices with ultra-narrow channels at room temperature for the first time. Furthermore, low-frequency noise spectra having both 1/f′ and Lorentzian type are found separately in the same ultra-narrow channel at different gate bias voltage, whereas only 1/f′ noise is observed in relatively wide channels. The observations strongly suggest that low-frequency noise in weak inversion dominantly suffer from carrier mobility fluctuation rather than carrier number fluctuation in ultra-narrow channels, which is confirmed by numerical simulations.