Low-frequency Feedback Loop Research Articles

Analysis and Design of a Foam-Cladded PMF Link With Phase Tuning in 28-nm CMOS

This paper presents a fully packaged 140-GHz dielectric waveguide (DWG) communication link using a foam-cladded fiber. A novel frequency shift keying (FSK) demodulator topology is proposed with a low-frequency feedback loop for optimal FSK demodulation under process, voltage, and temperature variation. The introduction of phase shifters and an on-chip local oscillator relaxes the design requirements and the IF-stage benefits from larger gain. The transmitter is based on a fundamental oscillator at 140 GHz with a transformer-coupled buffer to decrease capacitive loading. Both chips are implemented in a 28-nm bulk CMOS design with a nominal supply of 0.9 V and a combined power consumption of 230 mW. An analysis of the DWG data capacity limitations is presented and compared with measurement results. Data rates of 12 Gb/s/10 Gb/s/7 Gb/s over 1 m/2 m/4 m of touchable polytetrafluoroethylene (PTFE) fiber are achieved.

A Harmonic Class-C CMOS VCO-Based on Low Frequency Feedback Loop: Theoretical Analysis and Experimental Results

A novel harmonic Class-C CMOS VCO architecture with improved phase noise performance and power efficiency is presented in this paper. The VCO is based on the widely adopted topology consisting in a crossed pair of NMOS devices refilling a symmetric resonator with a center tapered inductor and biased by a top PMOS current generator. The Class-C operation mode is obtained through a low frequency feedback loop constituted by an operational transconductance amplifier operating the difference between the inductor center tap voltage and a reference voltage, pushing gate polarization voltage of VCO crossed pair devices well below their threshold voltage. The Class-C VCO achieves a theoretical 2.9 dB phase noise improvement compared to the standard differential-pair LC-tank oscillator for the same current consumption. A prototype of the VCO is implemented in a standard RF 55 nm CMOS technology and compared to both a standard and an optimized VCO implemented in the same technology. All these VCOs share a copy of a unique resonator. The Class-C VCO is tunable over the frequency band 6.5-7.8 GHz and displaying an average phase noise lower than -127 dBc/Hz @ 1 MHz offset with a power consumption of 18 mW, for a state-of-the-art figure-of-merit of -187 dBc/Hz @ 1 MHz and -191 dBc/Hz @ 10 MHz offsets, respectively.

High-rate X-ray spectroscopy using a Silicon Drift Detector and a charge preamplifier

In this work, we present the results achieved in the experimental characterization of a Silicon Drift Detector (SDD) in X-ray spectroscopy measurements at high counting rates. The main goal of the work is to verify that high peak stability can be achieved when using an SDD with the input JFET and when the feedback capacitor directly integrated on the detector and a charge preamplifier configuration. In the proposed circuit, the SDD anode voltage is stabilized by means of a low-frequency feedback loop which operates according to the ‘drain feedback’ technique. The stabilization of the anode voltage is necessary to guarantee the stabilization of the feedback capacitor; moreover, the implemented design allows to obtain a sufficiently fixed decay time constant of the preamplifier with respect to rate variations. In the characterization of the preamplifier with an SDD, a Mn-Kalpha peak shift within ±0.05% (i.e. below 6 eV) has been achieved changing the rate from few kcounts/s up to several hundred kcounts/s. The same circuit has been modified and then employed to be used with an SDD without feedback capacitor, exploiting a parasitic capacitor between anode and a neighbour ring as feedback capacitor. The results achieved with this configuration are also presented in this work.

A low-power high-psrr current-mode microphone preamplifier

Bionic implants for the deaf require wide-dynamic-range low-power microphone preamplifiers with good wide-band rejection of the supply noise. Widely used low-cost implementations of such preamplifiers typically use the buffered voltage output of an electret capacitor with a built-in JFET source follower. We describe a design in which the JFET microphone buffer's output current, rather than its output voltage, is transduced via a sense-amplifier topology allowing good in-band power-supply rejection. The design employs a low-frequency feedback loop to subtract the dc bias current of the microphone and prevent it from causing saturation. Wide-band power-supply rejection is achieved by integrating a novel filter on all current-source biasing. Our design exhibits 80 dB of dynamic range with less than 5 /spl mu/V/sub rms/ of input noise while operating from a 2.8 V supply. The power consumption is 96 /spl mu/W which includes 60 /spl mu/W for the microphone built-in buffer. The in-band power-supply rejection ratio varies from 50 to 90 dB while out-of-band supply attenuation is greater than 60 dB until 25 MHz. Fabrication was done in a 1.5-/spl mu/m CMOS process with gain programmability for both microphone and auxiliary channel inputs.

Nonlinear analysis tools for the optimized design of harmonic-injection dividers

New nonlinear analysis tools for harmonic-injection dividers are presented based on bifurcation concepts. The advantage of these tools is their application simplicity and efficiency, which has enabled their use for actual circuit design and optimization. The tools allow control over the divided frequency and output power and predict the variation of the synchronization bands versus the circuit element values, which facilitates design correction. They have been extended to the analysis and optimization of phase-locked harmonic-injection dividers, which contain a low-frequency feedback loop. The use of this loop, together with the accuracy of the analysis, has enabled the implementation of novel frequency-division functions, such as the division of variable order, versus a circuit parameter, or the division by fractional order. The output noise of the frequency dividers is analyzed through the conversion-matrix approach, studying the noise variation along the division bands. The new techniques have been applied to the design of a frequency divider by order 4 and 5, with 18-GHz input frequency, and excellent agreement with experimental results has been obtained.