Low-end Field Programmable Gate Array Research Articles

A Design Method for Low-cost and SOPC-based Flexible Lifting Control System

To efficiently reduce the development and production costs of the intelligent lifting control system, we introduce a design method for the intelligent lifting system with client-server architecture. We replace DSP processor core or DSP (Digital Signal processor) core with Nois II soft-core processor so that the design and production costs can be effectively cut. By replacing DSP processor or DSP processor core with Nois II soft-core processor, the design and production costs can be significantly reduced. In our design, loop vector control units work as a server processor, and a central computing unit with four independent multipliers and two adders is employed, with the implementation method based on a state machine. The experimental results prove effective in reducing resource requirements for FPGA (Field Programmable Gate Array), show that the proposed method can be successfully applied to the implementation of a complete intelligent flexible lifting control system on a low-end Altera Cyclone FPGA, and servo motor control achieves better dynamic performance

Arbitrary Configurable 20-Channel Coincidence Counting Unit for Multi-Qubit Quantum Experiment

This paper presents a 20-channel coincidence counting unit (CCU) using a low-end field-programmable gate array (FPGA). The architecture of the CCU can be configured arbitrarily to measure from twofold to twentyfold coincidence counts thanks to a multifold controllable architecture, which can be easily manipulated by a graphical user interface (GUI) program. In addition, it provides up to 20 of each input signal count simultaneously. The experimental results show twentyfold coincidence counts with the resolution occurring in a less than 0.5 ns coincidence window. This CCU has appropriate characteristics for various quantum optics experiments using multi-photon qubits.

On building a CNN-based multi-view smart camera for real-time object detection

Multi-view image sensing is currently gaining momentum, fostered by new applications such as autonomous vehicles and self-propelled robots. In this paper, we prototype and evaluate a multi-view smart vision system for object recognition. The system exploits an optimized Multi-View Convolutional Neural Network (MVCNN) in which the processing is distributed among several sensors (heads) and a camera body. The main challenge for designing such a system comes from the computationally expensive workload of real-time MVCNNs which is difficult to support with embedded processing and high frame rates. This paper focuses on the decisions to be taken for distributing an MVCNN on the camera heads, each camera head embedding a Field-Programmable Gate Array (FPGA) for processing images on the stream. In particular, we show that the first layer of the AlexNet network can be processed at the nearest of the sensors, by performing a Direct Hardware Mapping (DHM) using a dataflow model of computation. The feature maps produced by the first layers are merged and processed by a camera central processing node that executes the remaining layers. The proposed system exploits state-of-the-art deep learning optimization methods, such as parameter removing and data quantization. We demonstrate that accuracy drops caused by these optimizations can be compensated by the multi-view nature of the captured information. Experimental results conducted with the AlexNet CNN show that the proposed partitioning and resulting optimizations can fit the first layer of the multi-view network in low-end FPGAs. Among all the tested configurations, we propose 2 setups with an equivalent accuracy compared to the original network on the ModelNet40 dataset. The first one is composed of 4 cameras based on a Cyclone III E120 FPGA to embed the least expensive version in terms of logic resources while the second version requires 2 cameras based on a Cyclone 10 GX220 FPGA. This distributed computing with workload reduction is demonstrated to be a practical solution when building a real-time multi-view smart camera processing several frames per second.

A novel hardware-oriented ultra-high-speed object detection algorithm based on convolutional neural network

This paper describes a hardware-oriented two-stage algorithm that can be deployed in a resource-limited field-programmable gate array (FPGA) for fast-object detection and recognition with out external memory. The first stage is the bounding boxes proposal with a conventional object detection method, and the second is convolutional neural network (CNN)-based classification for accuracy improvement. Frequently accessing external memories significantly affects the execution efficiency of object classification. Unfortunately, the existing CNN models with a large number of parameters are difficult to deploy in FPGAs with limited on-chip memory resources. In this study, we designed a compact CNN model and performed the hardware-oriented quantization for parameters and intermediate results. As a result, CNN-based ultra-fast-object classification was realized with all parameters and intermediate results stored on chip. Several evaluations were performed to demonstrate the performance of the proposed algorithm. The object classification module consumes only 163.67 Kbits of on-chip memories for ten regions of interest (ROIs), this is suitable for low-end FPGA devices. In the aspect of accuracy, our method provides a correctness rate of 98.01% in open-source data set MNIST and over 96.5% in other three self-built data sets, which is distinctly better than conventional ultra-high-speed object detection algorithms.

Implementation of a reliable mechanism for protecting IP cores on low-end FPGA devices

Field programmable gate array (FPGA) technology is being adopted in many digital systems, hence the demand for security increases, especially when intrinsic vulnerabilities of programmable devices jeopardise the intellectual properties (IPs). New high and medium-end FPGA devices have built-in mechanisms that, exploiting encryption primitives, are able to avoid IP piracy by preventing cloning and reverse engineering, but low-end FPGA families still lack security solutions. Recently, in the literature, a great researching effort has been done on physically unclonable functions (PUFs), which are eligible to be a fundamental means for authenticating integrated circuits. They can be adopted to guarantee protection against IP violations by implementing locking finite state machines (FSMs) on any device. In this paper, we show two implementations of the Anderson PUF, a good scalable and high reliable PUF architecture, on the Xilinx Spartan-3E family, which can be adopted to introduce the locking mechanism. In the experimental result, we show the quality parameters for signatures generated from proposed Anderson PUFs and the overhead introduced by the locking mechanism through an FSM.

Implementation of a reliable mechanism for protecting IP cores on low-end FPGA devices

Field programmable gate array (FPGA) technology is being adopted in many digital systems, hence the demand for security increases, especially when intrinsic vulnerabilities of programmable devices jeopardise the intellectual properties (IPs). New high and medium-end FPGA devices have built-in mechanisms that, exploiting encryption primitives, are able to avoid IP piracy by preventing cloning and reverse engineering, but low-end FPGA families still lack security solutions. Recently, in the literature, a great researching effort has been done on physically unclonable functions (PUFs), which are eligible to be a fundamental means for authenticating integrated circuits. They can be adopted to guarantee protection against IP violations by implementing locking finite state machines (FSMs) on any device. In this paper, we show two implementations of the Anderson PUF, a good scalable and high reliable PUF architecture, on the Xilinx Spartan-3E family, which can be adopted to introduce the locking mechanism. In the experimental result, we show the quality parameters for signatures generated from proposed Anderson PUFs and the overhead introduced by the locking mechanism through an FSM.

Real-time Speed Limit Traffic Sign Detection System for Robust Automotive Environments

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries’ speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but highperformance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

High-performance reconfigurable coincidence counting unit based on a field programmable gate array.

We present a high-performance reconfigurable coincidence counting unit (CCU) using a low-end field programmable gate array (FPGA) and peripheral circuits. Because of the flexibility guaranteed by the FPGA program, we can easily change system parameters, such as internal input delays, coincidence configurations, and the coincidence time window. In spite of a low-cost implementation, the proposed CCU architecture outperforms previous ones in many aspects: it has 8 logic inputs and 4 coincidence outputs that can measure up to eight-fold coincidences. The minimum coincidence time window and the maximum input frequency are 0.47ns and 163MHz, respectively. The CCU will be useful in various experimental research areas, including the field of quantum optics and quantum information.

Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA

The Direct Digital Frequency Synthesizer (DDFS) is a critical component routinely implemented in communication or signal processing systems.The recent literature proposes various DDFS implementation techniques that, implemented by using state of the art Application Specific Integrated Circuits (ASIC) technologies, provide ever improving performances in terms of speed, power dissipation and silicon area occupation.The performance trend provided by the advanced designs that target ASIC technologies is not guaranteed to remain the same when the target technology is a commercially available Field Programmable Gate Array (FPGA) device.This paper presents the FPGA implementation of the best performing DDFS architectures proposed to date. DDFS performance trends are compared with the ASIC implementations. Further, the state of the art DDFS circuits are modified in order to better suit the FPGA technology and compared against the DDFS implementations obtained using Intellectual Properties (IPs) included in the design suites of the FPGA manufacturers. The comparison is conducted considering as implementation target various (both low end, middle range, and high end) FPGA devices produced by different vendors. Considered performance parameters are the maximum working frequency, the dynamic power dissipation, the logic resource occupation, and the precision of the DDFS measured in terms of Spurious Free Dynamic Range (SFDR).The analysis shows that when dealing with FPGA implementations, it is important that the implemented architectures adapt to the internal logic resources of the FPGA. For low SFDR values the best performing architectures are the straightforward ROM based ones that optimally fit in the very fast Block RAM of the FPGA. When the required SFDR increases more advanced architectures are required. The optimal architectures also depend on the design choice of privileging high working frequency or reduced power dissipation.

Note: A 4 ns hardware photon correlator based on a general-purpose field-programmable gate array development board implemented in a compact setup for fluorescence correlation spectroscopy

We present a fast hardware photon correlator implemented in a field-programmable gate array (FPGA) combined with a compact confocal fluorescence setup. The correlator has two independent units with a time resolution of 4 ns while utilizing less than 15% of a low-end FPGA. The device directly accepts transistor-transistor logic (TTL) signals from two photon counting detectors and calculates two auto- or cross-correlation curves in real time. Test measurements demonstrate that the performance of our correlator is comparable with the current generation of commercial devices. The sensitivity of the optical setup is identical or even superior to current commercial devices. The FPGA design and the optical setup both allow for a straightforward extension to multi-color applications. This inexpensive and compact solution with a very good performance can serve as a versatile platform for uses in education, applied sciences, and basic research.

Mobile Robot Navigation Through a Hardware-Efficient Implementation for Control-Law-Based Construction of Generalized Voronoi Diagram

This paper proposes a navigation control law based on a Lyapunov function for the construction of a generalized Voronoi diagram (GVD), applicable for mobile robots with ultrasonic sensors operating in indoor environments. The proposed control law is a modification of the one in [H. Choset and K. Nagatani, “Topological simultaneous localization and mapping (SLAM): Toward exact localization without explicit localization,” IEEE Trans. Robot. Autom., vol. 17, no. 2, pp. 125-137, Apr. 2001.]. A new definition is proposed for the distance function that renders the proposed modified control law well defined for all points in free space. To follow the trajectory closely, an architecture for the control law based on simultaneous handling of sensors and the motors is proposed. An efficient implementation of the control law using merely a low-end field-programmable gate array and no external memory is presented. Experimental results validate the efficacy of the proposed modified control law. The paper also proves that the proposed modified control law traces the GVD without any approximation. The results are compared with two earlier studies.

Efficient FPGA Realization of CORDIC With Application to Robotic Exploration

We present an area efficient method and field programmable gate array (FPGA) realization for two common operations in robotics, namely, the following: (1) rotating a vector in 2D and (2) aligning a vector in the plane with a specific axis. It is based on a new coordinate rotation digital computer (CORDIC) algorithm that is designed to work with a small set of elementary angles. Unlike conventional CORDIC, the proposed algorithm does not require a ROM and a full-fledged barrel shifter. The proposed CORDIC algorithm is used to design hardware efficient solutions for two mobile robotic tasks in an indoor environment without employing division and floating-point calculations. Experiments with a sole low end FPGA based robot in static as well as dynamic environments validate the power of the approach.

Hardware-Efficient Prediction-Correction-Based Generalized-Voronoi-Diagram Construction and FPGA Implementation

Sensor-based construction of different geometric structures has been an important development in the domain of autonomous robot navigation. This paper presents a hardware-efficient scheme to construct one such geometric structure, namely, the generalized Voronoi diagram (GVD), using a prediction-and- correction strategy. In this paper, an architecture to construct the GVD for an indoor environment with multiple obstacles whose geometry and location are not known beforehand is presented. A feature of the proposed approach is that it does not involve operations that are expensive in hardware. Furthermore, no explicit angle computation circuitry is needed. An efficient architecture based on hardware reuse is presented. The design is shown to be space efficient and fits in a low-end field-programmable gate-array (FPGA) device (with a small number of system gates). Detailed experiments with a mobile robot fabricated locally with a Xilinx XC2S200E FPGA and eight ultrasonic sensors onboard validate the efficacy of the proposed approach for static as well as dynamic environments.