Low-dropout Regulator Research Articles

Stability of On-Chip Power Delivery Systems With Multiple Low-Dropout Regulators

Low-dropout (LDO) voltage regulators have become prominent elements of on-chip power delivery systems due to the increasing importance of separate voltage domains, fast dynamic voltage scaling, and the need for high-quality power. As the number of LDOs sharing a common power network increases, the stability of the power grid can degrade if the resonance frequency due to the off-chip parasitic impedances is not sufficiently separated from the unity gain frequency of the regulator. In this paper, this source of instability in power delivery networks, consisting of multiple LDO regulators with a balanced load, is described. The effect of the number of LDOs on the resonance frequency of the power delivery network is evaluated to determine the stability of the system when the LDOs operate under similar load conditions.

A Digital Low-Dropout Regulator With Autotuned PID Compensator and Dynamic Gain Control for Improved Transient Performance Under Process Variations and Aging

This article demonstrates all-digital tuning and dynamic control of feedback compensator in digital low drop out regulators to enhance the transient performance under process and passive variations, aging, and load changes. The measured results from a 130-nm CMOS test-chip shows 2.1× improvement in transient performance under process variations and 30% improvement for aging-induced degradations. We demonstrate 55-ns setting time for a 5 to 45 mA load step in 100 ps, with 97.8% peak current efficiency.

Dual active capacitive feedbacks for output capacitor-less low-dropout regulator

An output capacitor-less low-dropout (OCL-LDO) voltage regulator with dual active feedback paths is presented in this paper. The dual active feedbacks provide frequency compensation and spike voltage suppression. Two feedback loops are formed by capacitors Cc and Ca, respectively. The capacitor Ca path detects output voltage to suppress undershoot and overshoot during load transient. The frequency compensation is achieved by capacitor Cc, which helps the LDO regulator not only improve stability, but also enhance transient response without large current consumption. The total utilized capacitance values are only 1.5 pF. The proposed OCL-LDO was fabricated in 0.18 μm CMOS technology with supply voltage of 1.8 V. The LDO consumes 21 μA of quiescent current and the chip area is 0.47 mm × 0.49 mm. The measured output voltage difference is 90 mV when the load current is increased from 50 μA to 100 mA with CL= 100 pF and recovery time less than 1 μs. The power supply rejection is − 51.7 dB at 1 kHz.

An efficient energy harvesting circuit for batteryless IoT devices

A new energy harvesting circuit for battery-less IoT beacon tags is developed herein to maximize power conversion efficiency as well as high throughput power with a wide input–output range. This design energy harvest (EH) circuit incorporates a charge pump (CP) with shoot-through current suppression, a body selector circuit, a maximum power point tracking circuit (MPPT), a timing control circuit, a hysteresis control circuit and a low dropout regulator. Also in this MPPT circuit is a gated clock tuned in a self-adaptive fashion to match the input impedance of the EH circuit to the output impedance of the photovoltaic (PV) panel, thus achieving successfully maximum power point. The circuit is implemented in an integrated chip in an area of 1.2 mm2 via the TSMC 0.18 process. Experiments on the chip are conducted and the results show that the input voltage range is allowed from 0.55 to 1.7 V to effectively harvest the solar power from a flexible dye-sensitized solar cell. The achieved peak power conversion efficiency (PCE) is 77% at the input power of 52 μW. For a wide range of lighting luminance (300–1300 lx,) the achieved average PCE is more than 70%. The achieved wide input–output range and the maximum throughput power of 200 μW is much larger than others reported, while the 77% of PCE is close to that best power conversion efficiency reported.

Fast transient low‐dropout regulator with undershoot and settling time reduction technique

This article proposes an external capacitor-less low-dropout (LDO) regulator with undershoot and settling time reduction technique for fast transient response. In the proposed LDO, a feedback capacitor is applied instead of a complicated voltage-spike detection circuit to reduce undershoot voltage and settling time without consuming additional quiescent current. When an undershoot or overshoot voltage occurs in the load transient response, the undershoot voltage and settling time are reduced by increasing the gate discharging current or gate charging current of the pass transistor by the current flowing through the feedback capacitor. An adaptively biased single-stage error amplifier with a cross-coupled pair is used to improve stability without external capacitors at low quiescent current consumption. The proposed LDO regulator is implemented with a 0.18 μm CMOS process and consumes a quiescent current of 3.0 μA at a minimum load current of 0.1 mA. Compared with the conventional LDO regulator, the proposed LDO regulator reduces the undershoot voltage by 53.3% and the settling time by 55.5% without consuming additional quiescent current.

Modeling and Analysis of On-Chip Power Noise Induced by an On-Chip Linear Voltage Regulator Module With a High-Speed Output Buffer

In this paper, analytical models of on-chip power noise induced by an on-chip linear voltage regulator module (VRM) circuit with a high-speed output buffer are proposed. Based on the piecewise linear approximated mosfet I – V curve model, closed-form equations for the on-chip power noise induced by an on-chip low-dropout regulator are derived. The accuracy of the proposed analytical model is validated by SPICE simulation with a 110-nm CMOS technology library. Based on the proposed analytical models, the impacts of VRM design parameters on VRM output noise induced by load current and external noises are analyzed. Because self-impedance at the VRM output and external noise transfer functions share a common resonant frequency, the on-chip power noise is minimized by avoiding the resonant frequency from peak frequencies of noise source spectrums. The larger on-chip decoupling capacitance at load reduces, the overall on-chip VRM output noise. While the larger pass transistor size reduces the on-chip VRM output noise induced by the reference voltage fluctuation, it increases the noise generated by off-chip power fluctuation. The reference voltage node needs to be carefully designed, as opposed to an off-chip power distribution network, due to its dominant impact on the on-chip VRM output noise. The analysis results based on the proposed model provide an in-depth understanding of and useful design guidance for on-chip power noise induced by the on-chip linear VRM with a high-speed output buffer.

Dynamic current-boosting based FVF for output-capacitor-less LDO regulator

A flipped voltage follower structure based on a dynamic current boosting technique is proposed which enables the fast-transient behavior. It is applied to an output capacitor-less low-dropout (LDO) regulator to improve the output transient response and reduce the over/undershoots of the output voltage when the load current or the input voltage is suddenly changed. The proposed low-dropout regulator is simulated in 0.18 μm CMOS technology, which the output voltage is regulated at 1 V with a dropout voltage of about 114 mV. The output voltage over/undershoot amplitudes of the proposed LDO are obtained in 99.52/551.8 mV with the settling time of fewer than 1.3 μs for the load current changes from 0.1 to 100 mA with 200 ns rise/fall times.

Topological Classification-Based Splitting–Combining Methodology for Analysis of Complex Multi-Loop Systems and Its Application in LDOs

Multiple loops have been used extensively to enhance the system performance in various applications. However, the increasing complexity of multi-loop systems also makes them much more difficult to analyze and implement. In this paper, a new methodology to analyze multi-loop system is proposed. In the proposed framework, multi-loop systems are regarded to be built upon of sub-modules of cascade, parallel adding, and feedback units, and then, they are simplified following a certain procedure based on the correlation of the Bode characteristics of the segmented sub-modules. Applying this methodology, the Bode plot and the transfer function of the system can be easily obtained with the system properties of gains, zeros, and poles. Two examples are provided as demonstrators, including a multi-loop low-dropout regulator (LDO) from literature, and a newly designed multi-loop LDO aiming at enhancing the stability over a wide load range, which show that the Bode plot and the transfer function can be obtained more intuitively and rapidly. Excellent agreements among theory, simulations, and measurements are confirmed, which verify the proposed method. It can help designers to gain more intuitions and insights on multi-loop systems from both circuit and device perspectives, which is also an effective tool for both stability analysis and circuit design.

A Fast Transient and Low Power Capacitor-less Low-dropout Regulator using Advanced Dynamic Biasing Method

A Fast Transient and Low Power Capacitor-less Low-dropout Regulator using Advanced Dynamic Biasing Method

A Sub-threshold based 747 nW Resistor-less Low-dropout Regulator for IoT Application

A Sub-threshold based 747 nW Resistor-less Low-dropout Regulator for IoT Application

A Fully Integrated LDO With 50-mV Dropout for Power Efficiency Optimization

This brief presents, a fully integrated low-dropout regulator (LDO) with 50-mV dropout voltage for high power efficiency, with a LDO-self-supplied differential error amplifier (EA) for higher power supply rejection (PSR), and a coupled transient enhancement unit for fast transient response. With 50-mV dropout voltage, the LDO can achieve 94.4% power efficiency in the full load condition. The LDO is fabricated in a standard 28-nm bulk CMOS process with 0.0086-mm2 active area. It features a 288-MHz unity-gain bandwidth (UGB) at 20-mA load current, while consuming a quiescent current of 33 ${\mu }\text{A}$ . With such high bandwidth and the coupled transient enhancement unit, the proposed LDO achieves 270-ps response time for a 0-to-20-mA load transient with 100-ps edge time. The self-supplied EA helps to achieve a PSR of −30 dB even with only 50-mV dropout. The ultra-fast response, small area, and high efficiency features make the proposed LDO very suitable for working as distributed point-of-load regulators in a digital system.

A 50-V Isolation, 100-MHz, 50-mW Single-Chip Junction Isolated DC-DC Converter With Self-Tuned Maximum Power Transfer Frequency

A fully integrated, point-of-load, low-noise, isolated dc–dc converter for supply regulation of high dynamic range analog and mixed-signal isolated sensor signal-chains is presented. The isolated dc–dc converter utilizes an integrated planar air-core micro-transformer as a coupled-resonator and an isolation barrier, and enables direct connection of low-voltage mixed-signal circuits to higher supply rails for current and voltage sensing. The transformer is driven at its resonant frequency of 100 MHz to achieve maximum power transfer. A mixed-signal perturb-and-observe-based frequency search algorithm is developed to improve maximum power transfer efficiency by 60% across the isolation barrier compared to fixed driving frequency method. The switching ripple at output is reduced by 11 dB utilizing spread spectrum clocking in the driver, and 21 dB using a low-dropout regulator. Conducted and radiated EMI distribution on the IC is measured by a set of proposed ring oscillator-based noise sensors with −68-dBm noise sensitivity. The proposed isolated converter achieves the highest level of integration compared to state-of-the-art integrated isolated converters, and provides 50-V on-chip junction isolation using standard CMOS technology.

아날로그 IC에 응용 가능한 높은 PSRR과 높은 구동전류를 갖는 LDO 레귤레이터 설계에 관한 연구

아날로그 IC에 응용 가능한 높은 PSRR과 높은 구동전류를 갖는 LDO 레귤레이터 설계에 관한 연구

A Quiescent 407-nA Output-Capacitorless Low-Dropout Regulator With 0–100-mA Load Current Range

An ultralow quiescent current output-capacitorless low-dropout (LDO) regulator dedicated to Internet-of-Things applications is presented. This is based on an improved adaptive-stage adaptively biased architecture together with the novel frequency compensation to achieve the good stability and fast transient response under ultralow bias current. Validated by the CMOS 0.18- $\mu \text{m}$ technology, the chip area is 0.055 mm2. The proposed LDO regulator consumes only 407-nA quiescent current at no-load current while providing a 1-V output with a maximum load current of 100 mA from a 1.2-V power supply. The adaptive frequency compensation is presented, including a new transistor degeneration frequency compensation (TDFC) to sustain the stability at ultralow quiescent bias. Besides, it also includes Q-reduction and Miller-RC compensation schemes to ensure the stability for full load current range. In addition, a substantial improved transient response is obtained by the proposed distributed overshoot reduction circuit together with the TDFC scheme and the adaptively feed-forward biasing topology. The measured results have shown that the undershoot/overshoot voltage is 117 mV/35.33 mV and the output can settle in $1.56~\mu \text{s}$ with 1% accuracy. Compared to fixed-biased and adaptively biased architectures, it shows the lowest value in figure of merit (FOM) at the quiescent state. Compared to adaptively biased architectures, it shows the improved FOM at the maximum quiescent state.

Flash ADC‐based digital LDO with non‐linear decoder and exponential‐ratio array

This Letter presents a digital low-dropout regulator (LDO) that achieves fast transient response with a flash ADC-based parallel comparison. A non-linear decoder is employed in the flash ADC to further enhance the transient response. In the design of the power switch array, an exponential-ratio array (ERA) is adopted for high load driving capacity. The proposed digital LDO implemented in 65-nm CMOS achieves a load range of 0.04–82.7 mA when the input voltage and the output voltage are 1.0 and 0.9 V, respectively. The digital LDO achieves a settling time of 6 μs with a load step of 48 mA, exhibiting the state-of-the-art normalised settling time for the clock frequency of 1 MHz.

An Advanced Bootstrap Circuit for High Frequency, High Area-Efficiency and Low EMI Buck Converter

An advanced bootstrap control circuit with directly sensing bootstrap voltage (DSBV) for a high frequency, high area-efficiency, and low electromagnetic interference (EMI) buck converter in automotive applications is proposed in this brief. By removing the large off-chip capacitor at the output ${V} _{\text {CC}}$ of low-dropout regulator (LDO), the relevant current loop around ${V} _{\text {CC}}$ to power ground can be eliminated, which is a great contribution for EMI noise mitigation. On the other hand, the fast charging control for bootstrap capacitance has been substituted by a novel bootstrap architecture and is not dependent on the internal capless LDO, which will not degrade high-frequency behavior for the high-side gate driver. This buck converter has been implemented in a 0.35 $ {\mu }\text{m}$ high-voltage BCD process and occupies a chip area of $2 {\times }2.39$ mm2, where the active area of bootstrap circuit is $320 {\times } 194\,\, {\mu }\text{m}^{{2}}$ . Experimental results show that the bootstrap capacitance can be fully charged at MHz switching frequency with a small quiescent current of 43 $ {\mu }\text{A}$ .

Solar Powered Monitoring System Development for Smart Farming and Internet of Thing Applications

This paper is mainly aimed to develop a solar powered hand-held monitoring system for real-time crop-growth multiple environment parameter sensing and ZigBee-based wireless data transmission for Internet of Thing (IoT) applications. Regarding the problems of less man-power and difficult farm management in aging farmer population in many countries, in order to assist famers to monitor the status of plant growth and green-house condition in real time, this research focuses on the use of solar panels (5V/240mA 90mm2) and the buck converter IC to charge 18650 Lithium ion batteries used for hand-held monitoring system. The battery output will be coupled to a Low-Dropout (LDO) regulator, then generate a stable voltage to the CC2530 node. Solar panels will be integrated with the rechargeable batteries to yield more efficient power management. This paper proposes a LDO design for 18650 Lithium ion batteries. It will convert a supply voltage from 3.7V into 3.3V for driving the CC2530 and the sensors. The proposed solar powered system successfully built a Wireless Sensor Network (WSN) for quality agriculture application by using the ZigBee technology standard and TI’s CC2530 chip. Commercially available sensors were utilized specifically for temperature, humidity, soil moisture, light, chlorophyll, and CO2 monitoring. With the consideration and advantages of low power, low cost and multi-node capabilities, we chose ZigBee-based wireless network to transmit data into the cloud system for further data processing and analysis. When the sensors and Zigbee transmission system are set up, the data obtained through the human machine interface on the host will be sent to the cloud database established by MySQL in XAMPP. The management and data storage of the cloud database are both processed under the phpMyAdmin system. In addition, we use another program in XAMPP - Apache HTTP Server to set up the php website. Finally, this database of the sensing information will be used for assessment and evaluation of the environmental condition, data log recording, risk management and decision making. These resources can feed back to farmer’s cell phones through a decision support system. The experimental design and field test were verified in Tai-Yuan Organic farm located in Tao-Yuan County, Taiwan. The system will have a potential to be deployed into an open-field or green-house based farm to improve the optimized crop cultivation and increase the harvest yield. Figure 1

Small-Area Radiofrequency-Energy-Harvesting Integrated Circuits for Powering Wireless Sensor Networks.

This study presents a radiofrequency (RF)-energy-harvesting integrated circuit (IC) for powering wireless sensor networks with a wireless transmitter with an industrial, scientific, and medical (ISM) of 915 MHz. The proposed IC comprises an RF-direct current (DC) rectifier, an over-voltage protection circuit, a low-power low-dropout (LDO) voltage regulator, and a charger control circuit. In the RF-DC rectifier circuit, a six-stage Dickson voltage multiplier circuit is used to improve the received RF signal to a DC voltage by using native MOS with a small threshold voltage. The over-voltage protection circuit is used to prevent a high-voltage breakdown phenomenon from the RF front-end circuit, particularly for near-field communication. A low-power LDO regulator is designed to provide stable voltage by using zero frequency compensation and a voltage-trimming feedback. Charging current is amplified N times by using a current mirror to rapidly and stably charge a battery in the proposed charger control circuit. The obtained results revealed that the maximum power conversion efficiency of the proposed RF-energy-harvesting IC was 40.56% at an input power of −6 dBm, an output voltage of 1.5 V, and a load of 30 kΩ. A chip area of the RF-energy-harvesting IC was 0.58 × 0.49 mm2, including input/output pads, and power consumption was 42 μW.

Smart power management with combined current-feedback low-dropout voltage regulator and switched capacitor DC-DC converter in 180 nm CMOS

Achieving high efficiency over a wide range of input voltages for digital signal processing modules is a key focus in integrated electronic system applications. This paper proposes a current-feedback low-dropout (LDO) voltage regulator functioning in parallel with a step-down switched capacitor DC-DC converter to implement a smart power management in 180 nm CMOS technology. The proposed switched capacitor DC-DC converter is divided into four cell to reduce the output voltage ripple. The smart power management delivers a 0.71 V power supply with an efficiency as high as 69.4% while maintaining tolerable ripple, and operates over a wide input voltage range of 1.1 V–3.0 V while occupying only 1.5 mm2. The highest value of ripple is only 14 mV. Measurement results confirm that the proposed implementation achieves a higher efficiency and wider input voltage range than conventional implementations.

A 99.96% efficiency capacitor-free low-dropout regulator with cross-couple class-AB push–pull input stage for wireless internet of things chip

A high efficiency capacitor-free low-dropout regulator (LDO) with the cross-couple class-AB push–pull input stage is presented for wireless internet of things and wireless senor network chip. Utilizing the proposed input stage, both load/line regulation and power supply rejection ratio (PSRR) are improved. Meanwhile, the transient response including the undershoot voltage, the overshoot voltage and the recovery time is optimized with the sub-threshold slew-rate enhancement circuit and the multiple loop compensation strategy. Simulation results show that the LDO only consumes a quiescent current of 41.8 μA, resulting in the energy efficiency of 99.96% at a 100-mA maximum load current (IL) from 1.2 V supply voltage using 0.18-μm CMOS process. When IL is switching from 0 A to 100 mA in 0.3 μs, the undershoot voltage and the overshoot voltage are about 131.62 mV and 126.31 mV while the corresponding recovery time are 0.77 μs and 0.55 μs with CL = 100 pF, respectively. Furthermore, PSRR at 1-kHz is boosted to − 58.8 dB at full load. Besides, an excellent line and load regulation of 0.24 mV/V and 1.76 μV/mA are obtained, respectively.