Low Dose Rate Testing Research Articles

Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Processes for Mixed-Signal Integrated Circuits

Many bipolar linear integrated circuits have been shown to exhibit enhanced low dose rate sensitivity (ELDRS), where a product may have worse total ionizing dose (TID) performance when exposed to ionizing radiation at a low dose rate (LDR) than when exposed at a high dose rate (HDR). Recent studies on test cells have suggested that submicron CMOS processes may also exhibit ELDRS. Some CMOS products, although not considered to be BiCMOS, do contain active bipolar elements using the parasitic bipolar structures present in all bulk CMOS processes. Three mixed-signal CMOS products, one digital-to-analog converter (DAC) and two analog-to-digital converters (ADC), using different submicron CMOS processes and using active parasitic bipolar structures were put through LDR TID testing to determine if actual products exhibit ELDRS. MIL-STD-883 TM1019 contains a test method to qualify products that fail HDR TID testing for LDR environments by using HDR testing along with a room temperature anneal. This test method was previously demonstrated on supermicron process nodes. It has been suggested that this test method is not valid for submicron processes. The test method was validated on a submicron CMOS product using the LDR test data from one of the products in this study.

Method of simulation of low dose rate for total dose effect in 0.18 μm CMOS technology

Three methods for simulating low dose rate irradiation are presented and experimentally verified by using 0.18 μm CMOS transistors. The results show that it is the best way to use a series of high dose rate irradiations, with 100 °C annealing steps in-between irradiation steps, to simulate a continuous low dose rate irradiation. This approach can reduce the low dose rate testing time by as much as a factor of 45 with respect to the actual 0.5 rad (Si)/s dose rate irradiation. The procedure also provides detailed information on the behavior of the test devices in a low dose rate environment.

Evaluation of proposed hardness assurance method for bipolar linear circuits with enhanced low dose rate sensitivity (ELDRS)

Data are presented on several low dose rate sensitive bipolar linear circuits to evaluate a proposed hardness assurance method. The circuits include primarily operational amplifiers and voltage comparators with a variety of sensitive components and failure modes. The proposed method, presented in 1997, includes an option between a low dose rate test at 10 mrd(Si)/s and room temperature and a 100/spl deg/C elevated temperature irradiation test at a moderate dose rate. The results of this evaluation demonstrate that a 10 mrd(Si)is test is able (in ail but one case) to bound the worst case response within a factor of 2. For the moderate dose rate, 100/spl deg/C test the worst case response is within a factor of 3 for 8 of 11 circuits, and for some circuits overpredicts the low dose rate response. The irradiation bias used for these tests often represents a more degrading bias condition than would be encountered in a typical space system application.

A comparison of methods for simulating low dose-rate gamma ray testing of MOS devices

A radiation testing procedure is presented and experimentally verified in which a series of high-dose-rate irradiations, with 100 degrees C annealing under bias between irradiations, is used to simulate a continuous low-dose-rate irradiation. This approach can reduce low-dose-rate testing time by as much as a factor of 100 with respect to actual low-dose-rate irradiations. The procedure also provides detailed information on the behavior of CMOS parts at low dose-rates which are of interest to many satellite systems. >