Low-density Parity-check Research Articles

Near regular LDPC codes based on combinatorial designs

Some new approaches for constructing near regular binary low-density parity-check (LDPC) codes free of 4-cycles are proposed using dual of certain combinatorial designs which are [Formula: see text]-configurations. The present constructions further broaden the class of code lengths. The present constructions give higher code rates of near regular LDPC codes compared to the earlier codes with respect to same code length.

Layer codes

Quantum computers require memories that are capable of storing quantum information reliably for long periods of time. The surface code is a two-dimensional quantum memory with code parameters that scale optimally with the number of physical qubits, under the constraint of two-dimensional locality. In three spatial dimensions an analogous simple yet optimal code was not previously known. Here we present a family of three dimensional topological codes with optimal scaling code parameters and a polynomial energy barrier. Our codes are based on a construction that takes in a stabilizer code and outputs a three-dimensional topological code with related code parameters. The output codes are topological defect networks formed by layers of surface code joined along one-dimensional junctions, with a maximum stabilizer check weight of six. When the input is a family of good quantum low-density parity-check codes the output codes have optimal scaling. Our results uncover strongly-correlated states of quantum matter that are capable of storing quantum information with the strongest possible protection from errors that is achievable in three dimensions.

A Field-Programmable Gate Array-Based Quasi-Cyclic Low-Density Parity-Check Decoder with High Throughput and Excellent Decoding Performance for 5G New-Radio Standards

This work presents a novel fully parallel decoder architecture designed for high-throughput decoding of Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes within the context of 5G New-Radio (NR) communication. The design uses the layered Min-Sum (MS) algorithm and focuses on increasing throughput to meet the strict needs of enhanced Mobile BroadBand (eMBB) applications. We incorporated a Sub-Optimal Low-Latency (SOLL) technique to enhance the critical check node processing stage inherent to the MS algorithm. This technique efficiently computes the two minimum values, rendering the architecture well-suited for specific Ultra-Reliable Low-Latency Communication (URLLC) scenarios. We design the decoder to be reconfigurable, enabling efficient operation across all expansion factors. We rigorously validate the decoder’s effectiveness through meticulous bit-error-rate (BER) performance evaluations using Hardware Description Language (HDL) co-simulation. This co-simulation utilizes a well-established suite of tools encompassing MATLAB/Simulink for system modeling and Vivado, a prominent FPGA design suite, for hardware representation. With 380,737 Look-Up Tables (LUTs) and 32,898 registers, the decoder’s implementation on a Virtex-7 XC7VX980T FPGA platform by AMD/Xilinx shows good hardware utilization. The architecture attains a robust operating frequency of 304.5 MHz and a normalized throughput of 49.5 Gbps, marking a 36% enhancement compared to the state-of-the-art. This advancement propels decoding capabilities to meet the demands of high-speed data processing.

Two-Phase Globally Coupled Low-Density Parity Check Decoding Aided with Early Termination and Forced Convergence.

To enhance the decoding efficiency of Globally Coupled (GC) LDPC codes, we incorporated Early Termination (ET) and Forced Convergence (FC) into the local/global two-phase decoding algorithm to expedite the decoding process. The two-phase decoding scheme integrates the ET technique to halt unnecessary iterations in the local decoding phase while employing the FC technique to accelerate convergence in the global phase decoding. The application of ET technology in the local decoding of GC-LDPC codes will not cause performance loss as in traditional block codes and will cause considerable complexity gains. For a longer code length and larger convergence differences between nodes' global codes, the FC technique operates more efficiently in global code than local code. Two variants are proposed for the ET scheme in the local decoding, namely ET-1 and ET-2. The initial variant, ET-1, predicts whether local decoding can be successful according to data characteristics and stop the local decoding iteration that is not expected to be successful in time. In the case of ET-2, the saved local iterations are transformed to global decoding equally. The results show that ET-1 saves considerable decoding time complexity and ET-2 improves the performance of the GC-LDPC code with the same decoding time complexity. The combined approach of ET-1 with FC reduces the decoding time complexity up to 42% at a low Signal Noise Rate region while maintaining its performance; ET-2-FC two-phase decoding saves approximately 25% decoding time complexity while improving the BER by about 0.18 dB and FER by about 0.23 dB.

High-throughput software LDPC decoder on GPU

The new or future communication systems require much higher flexibility and scalability to support diverse scenarios. In this paper, a high-throughput low-density parity-check (LDPC) decoder on graphics processing unit is presented to meet the flexible and scalable requirements. A memory-reduced forward/backward approach for the check node update is proposed. Moreover, elaborate on-chip memory allocations are conducted to improve memory bandwidth. The proposed (26112, 8448) 5G LDPC decoder on RTX4090 achieves 27.6 Gbps decoding throughput with five layered iterations, while the latency is less than 1 ms. Compared with related works, the throughput speedups obtained by the presented LDPC decoder are from 1.18×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$1.18\ imes$$\\end{document} to 12.4×\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$12.4\ imes$$\\end{document}.

MIMO Volterra polynomial equalizer for PDM ultrahigh-order QAM signals.

In this work, we proposed and experimentally demonstrated a multiple-input multiple-output (MIMO) Volterra polynomial equalizer (MVPE), in a probabilistic shaping (PS) polarization-division multiplexed (PDM) 4096-quadrature amplitude modulation (QAM) coherent optical transmission system. In comparison with the conventional single-input single-output (SISO) Volterra nonlinear equalizers (VNLEs), the proposed MVPE can equalize the in-phase (I) and quadrature (Q) components in both the X and Y polarizations simultaneously and effectively alleviate nonlinear distortions. In the PS-PDM-4096-QAM experiment, the normalized generalized mutual information (NGMI) reached the threshold of DVB-S2 low-density parity-check (LDPC) codes with a 20% overhead. Compared to the SISO VNLE scheme, the MVPE scheme improves receiver sensitivity by approximately 2.8 dB while maintaining nearly similar computational complexity.

Joint Decoding Technique for Collision Resolution in Non-orthogonal Multiple Access Environment

Multiple access technologies have grown hand in hand from the first generation to the 5th Generation (5G) with both performance and quality improvement. Non-Orthogonal Multiple Access (NOMA) is the recent multiple access technology adopted in the 5G communication technology. Capacity requirements of wireless networks have grown to a large extent with the penetration of ultra-high-definition video transmission, Internet of Things (IoT), and virtual reality applications taking ground in the recent future. This paper develops the Physical Layer Network Coding (PNC) for collision resolution in a NOMA environment with two users. Traditionally NOMA uses Successive Interference Cancellation (SIC) for collision resolution. While additionally a decoding algorithm is added along with SIC to improve the performance of the collision resolution. MATLAB-based simulation is developed on the NOMA environment with two users using Viterbi coding, Low-Density Parity Check (LDPC), and Turbo coding. Performance parameters of Bit Error Rate (BER) and throughput are compared for these three algorithms. It is observed that the Turbo coding performed better among these three algorithms both in the BER and throughput. The BER obtained from the SIC- Turbo is found to be performing well with an increase of about 14% from the ordinary SIC implementation. The performance of the collision resolution has increased by 13% to 14% when joint decoding techniques are used and thus increasing the throughput of the NOMA paradigm.

Improving Threshold for Fault-Tolerant Color-Code Quantum Computing by Flagged Weight Optimization

Color codes are promising quantum error-correction (QEC) codes because they have an advantage over surface codes in that all Clifford gates can be implemented transversally. However, the thresholds of color codes under circuit-level noise are relatively low, mainly because measurements of their high-weight stabilizer generators cause an increase in the circuit depth and, thus, substantial errors are introduced. This makes color codes not the best candidate for fault-tolerant quantum computing. Here, we propose a method to suppress the impact of such errors by optimizing weights of decoders using conditional error probabilities conditioned on the measurement outcomes of flag qubits. In numerical simulations, we improve the threshold of the (4.8.8) color code under circuit-level noise from 0.14% to around 0.27%, which is calculated by using an integer programming decoder. Furthermore, in the (6.6.6) color code, we achieve a circuit-level threshold of around 0.36%, which is almost the same value as the highest value in the previous studies employing the same noise model. In both cases, the effective code distance is also improved compared to a conventional method that uses a single ancilla qubit for each stabilizer measurement. Thereby, the achieved logical error rates at low physical error rates are almost one order of magnitude lower than those of the conventional method with the same code distance. Even when compared to the single-ancilla method with a higher code distance, considering the increased number of qubits used in our method, we achieve lower logical error rates in most cases. This method can also be applied to other weight-based decoders, making the color codes more promising as candidates for the experimental implementation of QEC. Furthermore, one can utilize this approach to improve a threshold of wider classes of QEC codes, such as high-rate quantum low-density parity-check codes. Published by the American Physical Society 2024

Design of Low-Latency Layered Normalized Minimum Sum Low-Density Parity-Check Decoding Based on Entropy Feature for NAND Flash-Memory Channel.

As high-speed big-data communications impose new requirements on storage latency, low-density parity-check (LDPC) codes have become a widely used technology in flash-memory channels. However, the iterative LDPC decoding algorithm faces a high decoding latency problem due to its mechanism based on iterative message transmission. Motivated by the unbalanced bit reliability of codeword, this paper proposes two technologies, i.e., serial entropy feature-based layered normalized min-sum (S-EFB-LNMS) decoding and parallel entropy feature-based layered normalized min-sum (P-EFB-LNMS) decoding. First, we construct an entropy feature vector that reflects the real-time bit reliability of the codeword. Then, the reliability of the output information of the layered processing unit (LPU) is evaluated by analyzing the similarity between the check matrix and the entropy feature vector. Based on this evaluation, we can dynamically allocate and schedule LPUs during the decoding iteration process, thereby optimizing the entire decoding process. Experimental results show that these techniques can significantly reduce decoding latency.

A Low-Complexity Security Scheme for Drone Communication Based on PUF and LDPC

Due to the limited payload and power of drones, the computational overhead, storage overhead and communication overhead that can be used for secure communication are restricted, making it difficult to apply some complex but fairly secure authentication protocols on drones. In this paper, we propose a low-complexity protocol for storing identity information in a resource-unconstrained device that does not require the UAV to store the information, thereby enhancing the UAV’s resistance to capture. The protocol in this paper mainly consists of quasi-cyclic low-density parity-check (QC-LDPC) codes, physical unclonable functions (PUFs) based on random-access memory (RAM), “XOR” operations, and hash computation. The protocol in this paper is an authentication architecture in which the drone is guided by the ground station to read its identity information, and the drone does not store any identity information in advance. The protocol is divided into two phases: 1. fuzzy authentication of fingerprint PUF and 2. uniqueness authentication accomplished while guiding the recovery of identity PUF. Recovering identity PUF in this paper, QC-LDPC is used as the error control module, and the optimization of bit-flip decoding significantly reduces the probability of decoding failure. After the comparative security analysis and comparative overhead analysis of this paper’s protocol, it can be concluded that this paper’s protocol can withstand common attacks (including attacks attempting to pass authentication, attacks attempting to interfere with authentication, and physical capture attacks), and the storage and communication overhead is small in the case of large time overhead.

Enhancing Quantum Key Distribution Protocols for Extended Range and Reduced Error

Abstract this paper proposes an optimized Quantum Key Distribution (QKD) protocol using entanglement swapping techniques to extend transmission range and improve error correction. Additionally, integrates an advanced error correction technique which is Low Density Parity Check (LDPC) and multi-hop quantum repeaters for more enhancement of the protocol performance. Hybrid Quantum Classical Error Correction Methods is applied ensuring compatibility and optimal performance and to manage the increased complexity. Simulations prove that 25% improvement in transmission distance with entanglement swapping. 50% improvement with advanced error correction and a 100% improvement with multi-hop quantum repeaters compared to existing protocols. These discoveries are supported by both theoretical analysis and simulation results, indicating significant decreases in error rates and extensions in maximum transmission distances. Comparative analysis made with existing protocols and that demonstrated the superiority of proposed approach in terms of extended secure communication distance, higher key generation rate and improved resilience to attacks.

On Construction of Low-Density Parity-Check Codes for Ultra-Reliable and Low Latency Communications

On Construction of Low-Density Parity-Check Codes for Ultra-Reliable and Low Latency Communications

Estimation of the Impulse Response of the AWGN Channel with ISI within an Iterative Equalization and Decoding System That Uses LDPC Codes.

In this paper, new schemes have been proposed for the estimation of the additive white Gaussian noise (AWGN) channel with intersymbol interference (ISI) in an iterative equalization and decoding system using low-density parity check (LDPC) codes. This article explores the use of the least squares algorithm in various scenarios. For example, the impulse response of the AWGN channel h was initially estimated using a training sequence. Subsequently, the impulse response was calculated based on the training sequence and then re-estimated once using the sequence estimated from the output of the LDPC decoder. Lastly, the impulse response was calculated based on the training sequence and re-estimated twice using the sequence estimated from the output of the LDPC decoder. Comparisons were made between the performances of the three mentioned situations, with the situation in which a perfect estimate of the impulse response of the channel is assumed. The performance analysis focused on how the bit error rate changes in relation to the signal-to-noise ratio. The BER performance comes close to the scenario of having a perfect estimate of the impulse response when the estimation is performed based on the training sequence and then re-estimated twice from the sequence obtained from the output of the LDPC decoder.

Enhanced Non-Orthogonal Multiple Access Performance Using Channel Coding for High-Altitude Platform System (HAPS)

The high-altitude platform system (HAPS) is a promising technology for providing high-speed data transmission and coverage for remote areas. Still, it suffers from unpredictable channel transmission, especially in the Rician channel. To overcome the issue in transmission, we used one channel coding strategy, namely the quasi-cyclic low-density parity-check (QC-LDPC). This study aims to evaluate the performance of power domain non-orthogonal multiple access (PD-NOMA), which allows multiple users to share the same spectrum in a downlink communication system from HAPS to three ground stations. We simulated the system using MATLAB simulation with different power allocation coefficients for every ground station. The simulation results showed that QC-LDPC codes can significantly lower the signal-to-noise ratio (SNR) required to achieve the same bit error rate (BER) as uncoded NOMA, especially in scenarios with uneven power allocation. The average improvement of QC-LDPC over uncoded NOMA was 8.4% in SNR. However, we also observed that NOMA is prone to domino errors, where decoding errors in one ground station can propagate and degrade the performance of the subsequent ground station. Furthermore, we found that power allocation significantly impacts the system performance, while the location and power allocation of the second ground station have a minor effect. Based on these findings, we conclude that QC-LDPC can enhance system performance in scenarios with low received power and that power allocation is a crucial factor for NOMA systems with multiple ground stations.

Security-based low-density parity check encoder for 5G communication

The fifth generation (5G) of mobile telecommunication standards is intended to offer better performance and efficiency. One of the most significant difficulties in delivering safe data transfer through the transmission channel in the emerging 5G technology is channel-coding security. This research primarily focused on offering information transmission that is secure in the place of novel assaults such as side-channel attacks. In this research, we present a low-density parity check (LDPC) encoder that is constructed using the multiplicative masking method to overcome side-channel attacks, one of the most significant security concerns for the upcoming 5G system. As a result, it offers greater security, reduced complexity, and higher performance. Power, area, and delay can all be calculated using LDPC codes. Comparing multiplicative masking implemented LDPC encoders to ordinary channel coding techniques in terms of security seen that multiplicative masking implemented LDPC encoders offer more security. The program Xilinx ISE 14.7 can synthesize the analysis. The advantage of multiplicative masking is that it offers a promising level of security through the principle of randomization, which is the foundation of the procedure. According to the analysis, the secured transmission of the data by the proposed multiplicative masking implemented LDPC encoder is increased.

Flexible and High-Efficiency LDPC Encoder Architecture for CCSDS Standard

Abstract The Consultative Committee for Space Data Systems (CCSDS) has adopted quasi-cyclic low-density parity-check (QC-LDPC) codes for use in near-Earth (C2) and deep space (AR4JA) communications. Existing encoder architectures for C2 codes, however, fall short in efficiency for high-throughput applications. This paper introduces a comprehensive approach combining algorithmic and architectural optimizations to enhance hardware usage efficiency (HUE) while offering flexibility. We propose an integrated inter-block and intra-block parallel (IIB-IBP) encoding algorithm that leverages the unique matrix structure to significantly enhance performance. Additionally, a matrix-specific command register pretreatment (MSCRP) technique is developed to effectively handle the special dimensions of the generator matrix. Furthermore, we detail an offline design process for the automated generation of the encoder core’s HDL description, facilitating fine-tuning of encoding parallelism, latency, FPGA resource utilization, and overall throughput. Hardware implementation on a Virtex XC5VLX110T FPGA demonstrates that our encoder reaches an impressive throughput of 10.6 Gb/s with only 2531 LUTs and 1040 FFs, achieving a HUE of 2.97 Mbps/logic unit. This performance marks a 70.6% increase in HUE when compared to state-of-the-art designs.

An Optimization Model for Offline Scheduling Policy of Low-Density Parity-Check Codes

An Optimization Model for Offline Scheduling Policy of Low-Density Parity-Check Codes

Robust image tamper detection and recovery with self-embedding watermarking using SPIHT and LDPC

In today’s digital landscape, the pervasive use of digital images across diverse domains has led to growing concerns regarding their authenticity and reliability. The potential for malicious manipulation of these images underscores the critical need to develop robust methods for detecting tampering and ensuring their integrity. Fragile watermarking has been found to have extensive applications for tamper detection and recovery. An image watermarking technique for tamper detection, correction, and recovery is presented in this study. The proposed method employs a self-embedding method to generate the reference watermark from the original image, which has the advantage of superior tamper detection, localization, recovery capabilities, and robustness against attacks. Set Partitioning in the Hierarchical Tree (SPIHT) algorithm is applied to generate a reference watermark of the original image. Low-Density Parity Check (LDPC) is employed for error correction, providing higher-quality reconstruction to recover the original image. Schur decomposition processed the watermarked image blocks to generate authentication bits for each block to enhance tampering detection. The proposed watermarking method was evaluated using PSNR, SSIM, BER, and NC metrics for grayscale and colored images. The technique demonstrated high robustness in tamper detection and recovery against various malicious attacks. Comparative analysis with existing methods shows the efficacy of the proposed method.

Symmetry-Enforced Many-Body Separability Transitions

We study quantum many-body mixed states with a symmetry from the perspective of , i.e., whether a mixed state can be expressed as an ensemble of short-range-entangled symmetric pure states. We provide evidence for “symmetry-enforced separability transitions” in a variety of states, where in one regime the mixed state is expressible as a convex sum of symmetric short-range-entangled pure states, while in the other regime, such a representation is not feasible. We first discuss the Gibbs state of Hamiltonians that exhibit spontaneous breaking of a discrete symmetry, and argue that the associated thermal phase transition can be thought of as a symmetry-enforced separability transition. Next we study cluster states in various dimensions subjected to local decoherence, and identify several distinct mixed-state phases and associated separability phase transitions, which also provides an alternative perspective on recently discussed “average symmetry-protected topological order.” We also study decohered p+ip superconductors, and find that if the decoherence breaks the fermion parity explicitly, then the resulting mixed state can be expressed as a convex sum of nonchiral states, while a fermion parity–preserving decoherence results in a phase transition at a nonzero threshold that corresponds to spontaneous breaking of fermion parity. Finally, we briefly discuss systems that satisfy the no low-energy trivial state property, such as the recently discovered good low-density parity-check codes, and argue that the Gibbs state of such systems exhibits a temperature-tuned separability transition. Published by the American Physical Society 2024

Parallel Implementation of K-Best Quadrature Amplitude Modulation Detection for Massive Multiple Input Multiple Output Systems

Massive MIMO (Multiple Input Multiple Output) systems impose significant processing burdens along with strict latency requirements. The combination of large-scale antenna arrays and wide bandwidth requirements for next-generation wireless systems creates an exponential increase in frontend to backend data. Balancing the processing latency and reliability is critical for baseband processing tasks such as QAM detection. While linear detection algorithms have low computational complexity, their use in Massive MIMO scenario has heavy degradation in error performance. Nonlinear detection methods such as Maximum Likelihood and Sphere Decoding have good error performance, but they suffer from high, variable, and uncontrollable computational complexity. For such cases, the K-best QAM detection algorithm can provide required control over the system performance while maintaining near-ML error performance. In this paper, hard-output, as well as soft-output K-best QAM detection, is implemented in a CPU by utilizing the multiple cores combined with vector processing. Similarly, hard-output detection in a GPU is implemented by leveraging the SIMD (Single Instruction, Multiple Data) architecture and Warp-based execution model. The processing time per bit and the energy consumption per bit are compared for CPU and GPU implementations for QAM constellation density and MIMO array size. The GPU implementation shows up to 5× processing latency per bit improvement and up to 120× energy consumption per bit improvement over the CPU implementation for typical QAM constellations such as 4, 16, and 64 QAM. GPU implementation also shows up to 125× improvement over CPU implementation in energy consumption per bit for larger MIMO configurations such as 24 × 24 and 32 × 32. Finally, the soft-output detector is combined with a LDPC (Low-Density Parity Check) decoder to obtain the FER (Frame Error Rate) performance for CPU implementation. The FER is then combined with frame processing latency to form a Goodput metric to demonstrate the latency and reliability tradeoff.