Low-density Parity-check Encoder Research Articles

Security-based low-density parity check encoder for 5G communication

The fifth generation (5G) of mobile telecommunication standards is intended to offer better performance and efficiency. One of the most significant difficulties in delivering safe data transfer through the transmission channel in the emerging 5G technology is channel-coding security. This research primarily focused on offering information transmission that is secure in the place of novel assaults such as side-channel attacks. In this research, we present a low-density parity check (LDPC) encoder that is constructed using the multiplicative masking method to overcome side-channel attacks, one of the most significant security concerns for the upcoming 5G system. As a result, it offers greater security, reduced complexity, and higher performance. Power, area, and delay can all be calculated using LDPC codes. Comparing multiplicative masking implemented LDPC encoders to ordinary channel coding techniques in terms of security seen that multiplicative masking implemented LDPC encoders offer more security. The program Xilinx ISE 14.7 can synthesize the analysis. The advantage of multiplicative masking is that it offers a promising level of security through the principle of randomization, which is the foundation of the procedure. According to the analysis, the secured transmission of the data by the proposed multiplicative masking implemented LDPC encoder is increased.

A Quasi-Cyclic LDPC Based Low Complexity and Area-Efficient Communication System for IEEE 802.11n

Low-density parity-check (LDPC) code, which has an excellent error-correcting performance that is close to the Shannon limit, is the most often used error correction code (ECC) for reliable and effective communication. Despite higher performance and lower decoding complexity, the main disadvantage of LDPC codes is their high encoding complexity. A significant problem is the VLSI implementation of the LDPC encoder and decoder. In this paper, structured LDPC codes—also known as quasi-cyclic low-density parity check codes—have been used since it is good bit error ratio (BER) performance and adaptable hardware execution characteristics. The Complete (Encoder-Channel-Decoder) communication system with a 1/2 code rate, 648 bits codeward length, and sub-block size of z = 27 has been constructed for the IEEE 802.11n wireless standard.

Novel intelligent blind information reconciliation for LDPC codes in quantum key distribution systems

Information reconciliation is an important step in quantum key distribution (QKD). As a good channel coding technology, LDPC (low-density parity-check) code perform well in information reconciliation. In this paper, we investigate a new approach, namely blind information reconciliation. In our approach, after the state distribution is carried out by Alice and the measurements are taken by Bob, Alice can select an appropriate LDPC encoder (parity-check matrix) from the predefined candidate pool according to the estimated QBER (quantum bit-error-rate). Bob can use the expectation–maximization (EM) estimator and the maximum average log-likelihood ratio (LLR) detector to blindly identify parity-check matrices associated with not only different code-rates but also different codeword-lengths Alice employed. Moreover, puncturing and shortening can also be invoked to adjust the code-rate slightly to improve the error-correction performance. Monte Carlo simulations have demonstrated that our proposed new blind information-reconciliation scheme can successfully identify the parity-check matrix even under high QBER conditions, reduce the interactive communication-rounds, and improve the reconciliation efficiency in comparison with the conventional rate-adaptive LDPC coding scheme without QBER estimation.

Area‐ and energy‐efficient high‐throughput QC‐LDPC encoder for space applications

AbstractAn area‐ and energy‐efficient encoding method and encoder architecture are proposed for the quasi‐cyclic low‐density parity check (LDPC) in near‐earth applications recommended by the Consultant Committee for Space Data Systems. The proposed encoding method reduces the computational complexity using a switch network before bit XOR operations in vector–matrix multiplication. A fully parallel LDPC encoder is implemented on the Taiwan Semiconductor Manufacturing Company 90 nm complementary metal oxide semiconductor (CMOS) technology, achieving a throughput of 10.06 Tbps with the lower area and energy utilization.

Performance Evaluation of Single-Carrier and Orthogonal Frequency Divison Multiplexing-Based Autoencoders in Comparison with Low-Density Parity-Check Encoder

Recently, the growing demands for ultra-high speed applications require more advanced and optimal data transmission techniques. Wireless autoencoders have gained significant attention since they provide global optimization of the transceiver structure. This article explores the application of autoencoders to enhance the performance of wireless communication systems. It provides the performance evaluation of the systems using single-carrier and OFDM-based autoencoders under the conditions of AWGN and fading channels. Then, in terms of the BLER metric, the wireless systems with autoencoders are compared with conventional systems using LDPC coding and quadrature amplitude modulation for various configurations. Simulation results indicate that for high-modulation orders (QAM-64 or QAM-256), communication systems employing autoencoders provide superior performance compared to systems using LDPC channel encoding in regions with a low signal-to-noise (SNR) ratio. Specifically, a gain of 1–2 dB in signal power is obtained for single-carrier autoencoders and 0.3–2 dB is obtained for OFDM-based autoencoders. Therefore, wireless communication systems utilizing autoencoders can be considered as a promising candidate for future wireless communication systems.

A Review of Modern and Recent Studies on the Low-Density Parity-Check Technology Approach

Data theory coding is an excellent and well-known branch of study that has produced various crucial solutions to the insoluble challenges of safe data transfers. Last improvements in detecting error techniques have resulted in a significant increase in the use of low-density parity-check (LDPC) code to address critical concerns connected to secure data transfer. Until now, decent efforts have been performed on LDPC codes that target low complexity, high performance, and low bit error rate goals. The final aim of this review is to provide a recent literature understanding of modern improvements previously mentioned and in LDPC encoding and decoding (applicative and theoretical) techniques. A comparative scan of many remarkable LDPC decoding algorithms, 5G standard requirements, popular power management methods, and low-energy LDPC design studies is also shown. Lastly, conclusions are presented by outlining key study results, current concerns, and general thoughts on new research directions possibilities. Index Terms— low-density parity-check encoder/decoder (LDPC), error correction codes (ECC), forward error correction codes (FEC), parity check matrix(PCM).

GF(q) LDPC encoder and decoder FPGA implementation using group shuffled belief propagation algorithm

This paper presents field programmable gate array (FPGA) exercises of the GF(q) low-density parity-check (LDPC) encoder and interpreter utilizing the group shuffled belief propagation (GSBP) algorithm are presented in this study. For small blocks, non-dual LDPC codes have been shown to have a greater error correction rate than dual codes. The reduction behavior of non-binary LDPC codes over GF (16) (also known as GF(q)-LDPC codes) over the additive white Gaussian noise (AWGN) channel has been demonstrated to be close to the Shannon limit and employs a short block length (N=600 bits). At the same time, it also provides a non-binary LDPC (NB-LDPC) code set program. Furthermore, the simplified bubble check treasure event count is implemented through the use of first in first out (FIFO), which is based on an elegant design. The structure of the interpreter and the creation of the residential area he built were planned in very high speed integrated circuit (VHSIC) hardware description language (VHDL) and simulated in MODELSIM 6.5. The combined output of the Cyclone II FPGA is combined with the simulation output.

Implementation of real-time high-speed ultrasound communications through tissue

In this work, we propose a novel implementation of both a transmitter and receiver with field programmable gate arrays (FPGAs) to achieve real-time continuous high-definition (HD) video transmission through tissue, which can enable HD and higher frame rate wireless capsule endoscopy. We used a Texas Instruments AFE58JD48EVM 16 channel analog front end (AFE) evaluation board as the receiver connected to a Xilinx ZCU106 Zynq Ultrascale MPSoC development board in which we implemented a digital down converter (DDC), OFDM demodulator, maximum ratio combiner and low-density parity-check (LDPC) decoder. For the transmitter, we used an Analog Devices EVAL-AD9166 vector signal generator evaluation board, which has a built-in 4.3 dBm output power amplifier as a transmitter connected to another ZCU106 development board in which we implemented a LDPC encoder, OFDM modulator and digital up converter (DUC). The modulated signal was transmitted through a tissue-mimicking abdominal phantom using a 2-mm microcrystal transducer and received with a Sonic Concepts IP103 64 channel phased array at a center frequency of 3.2 MHz. We achieved the continuous transmission of up to over[OML1] 6 Mbps error free payload data rate after LDPC decoder which is used to carry HD video streams through ultrasound.

A Comprehensive Review of Low Density Parity Check Encoder Techniques

This paper presents a survey on various technologies of low density parity check encoder. LDPC codes are capable to handle high speed communication channel, by reducing attenuation, hazards and efficiently rectifying the linear error correction. Various coding technologies used in new generation communication system, such as turbo code, hamming code, low-density parity check (LDPC) code and Bose–Chaudhuri–Hocquenghem (BHC) code, are widely used in recent communication system. The LDPC has technical remarkable advantages and better performance in high speed communication process compared to turbo code. This paper deals with study of LDPC encoding techniques with various methods of detecting error and its correction. Here classification and performance analysis of LDPC encoding techniques on the basis of resources utilization, systematic, non-systematic approaches and consumer data right etc. have been analyzed in this paper. Apart from above mentioned criteria, this study deals with hardware and software architecture of LDPC encoder in rectification of forward error correction, parallel execution of instruction set. This study and analysis could offer scalability, the future scope of improving the performance of LDPC encoder in all aspects of the next generation communication process. This paper gives overview of various LDPC encoder applications, drawbacks and solution to overcome it.

A capacity-approaching coding scheme for M-PAM VLC systems with dimming control

A visible light communication (VLC) system with intensity modulation and direct detection is considered. A channel coding scheme based on a binary low-density parity-check (LDPC) code and M-ary pulse amplitude modulation (PAM) is designed. The LDPC encoder is followed by a many-to-one mapper. This mapper induces the input distribution for the non-equally spaced M-PAM alphabet under a desired dimming target. No auxiliary coding technique for DC-balance is needed. The coded scheme using non-equally probable M-PAM levels outperforms the use of equally probable levels showing capacity-approaching performance. Moreover, the scheme is flicker-free for typical information rates of a VLC system. The main advantage of the proposed scheme is that it does not incur any coding rate loss compared to other similar schemes in the literature.

An LDPC Encoder Architecture With Up to 47.5 Gbps Throughput for DVB-S2/S2X Standards

Low-Density Parity-Check (LDPC) code is a type of forward error-correction code with excellent performance, and has been widely used in many modern communication standards. The second-generation satellite broadcasting standard (DVB-S2) and its extension (DVB-S2X) adopt a special Irregular Repeated Accumulate (IRA) LDPC code as inner coding scheme. However, due to the large block size, most of the architectures proposed so far use Random Access Memory (RAM) to store and update the encoding results, and the delay caused by address-controlled read and write operations and barrel shift during computation inevitably limits the upper bound of encoder throughput. In this paper, by extracting the periodicity of the parity-check matrix, we introduce a fast encoding algorithm that can efficiently process the multiplication of the information sequence and a large-dimensional sparse matrix, and propose an encoder architecture with low encoding delay and high throughput. The proposed architecture has been implemented and tested on a Xilinx Kintex-7 FPGA, and the result show that the encoder architecture can achieve the highest throughput of 47.5 Gbps at a clock frequency of 280 MHz.

Ternary LDPC Error Correction for Arrhythmia Classification in Wireless Wearable Electrocardiogram Sensors

This paper presents a ternary low-density parity-check (LDPC) error correction system for wireless electrocardiogram sensors to improve the accuracy of arrhythmia classification. The classification system is based on ternary Delta-modulated bitstreams and rotation linear kernel support vector machines, which identifies the supraventricular ectopic beat (SVEB) and the ventricular ectopic beat (VEB) over the normal heartbeats. We model errors using a ternary symmetric channel with probability parameter <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$p$ </tex-math></inline-formula> and construct a variety of ternary LDPC codes with different coding rates by concatenating two-component sub-matrices to form a parity-check matrix with a quasi-cyclic structure that facilitates the hardware design. In particular, a hardware-friendly LDPC encoder circuit is proposed that leverages the highly structured parity-check matrix to perform serial generation of the parity symbols using an accumulator and a look-up table. The encoder circuits are implemented on FPGA and synthesized on ASIC using a 32 nm CMOS process. Simulation results show that the ternary LDPC codes can significantly improve classification accuracy in the presence of errors. For example, with an error probability of up to 21% in the sensor output bitstreams, the classification accuracy remains above 99% with the proposed error correction system.

Next generation earth-to-space telecommand coding and synchronization: ground system design, optimization and software implementation

The Consultative Committee for Space Data Systems, followed by all national and international space agencies, has updated the Telecommand Coding and Synchronization sublayer to introduce new powerful low-density parity-check (LDPC) codes. Their large coding gains significantly improve the system performance and allow new Telecommand services and profiles with higher bit rates and volumes. In this paper, we focus on the Telecommand transmitter implementation in the Ground Station baseband segment. First, we discuss the most important blocks and we focus on the most critical one, i.e., the LDPC encoder. We present and analyze two techniques, one based on a Shift Register Adder Accumulator and the other on Winograd convolution both exploiting the block circulant nature of the LDPC matrix. We show that these techniques provide a significant complexity reduction with respect to the usual encoder mapping, thus allowing to obtain high uplink bit rates. We then discuss the choice of a proper hardware or software platform, and we show that a Central Processing Unit-based software solution is able to achieve the high bit rates requested by the new Telecommand applications. Finally, we present the results of a set of tests on the real-time software implementation of the new system, comparing the performance achievable with the different encoding options.

Design and Analysis of (5, 10) Regular LDPC Encoder Using MRP Technique

An efficient compact encoding process with the pipelining design of Low Density Parity Check (LDPC) Encoder with a two stage, three stage and Maximal Rate Pipelining (MRP) structures are proposed in this work. Comparatively, LDPC encoding is more complex than decoding. The complexity mainly referred to the mathematical computation involved in the design of LDPC encoder. There are several methods used to design reduced parity check matrix, one of the methods involved is the Gauss Elimination method. Conventional and wave pipelining techniques are implemented to overcome the disadvantages of the area, latency, etc., The designed architectures are synthesized in SYNOPSYS tool and implemented in the XC3S-250E FPGA device. The overheads like power and area are efficiently reduced by wave pipelining and their efficiency can be proved by synthesis report. This showcases that the LDPC Encoders require less memory by using MRP structure.

LDPC Hardware Acceleration in 5G Open Radio Access Network Platforms

The Open Radio Access Network (RAN) concept has been gaining wide acceptance in recent network architectures, including 5G New Radio (NR) network deployments. Current Open RAN radio implementation efforts, aim at integrating several white-box hardware elements and executing digital processing on open-source software. When building such a software-based, 5G Open RAN platform, challenges include achieving real-time execution times for demanding computational blocks of the 5G NR physical layer processing, such as Low Density Parity Check (LDPC) decoding. In this context, having already identified both the capabilities as well as the challenges that Field-programmable Gate Arrays (FPGAs) offer for accelerating LDPC, we present our novel LDPC FPGA accelerator system. In this paper, we contribute the implementation details of our FPGA accelerator design as well as the process of integrating the accelerator with OpenAirInterface (OAI), the basis for our 5G NR platform. For the first time in the literature, we show an FPGA-based LDPC accelerator fully integrated with a complete software platform, that is able to achieve more than $1.6Gbps$ decoding throughput and up to 13 times faster execution times compared to single core software implementations. Finally, in our results, we show that LDPC encoding is more challenging to accelerate due to lower computational complexity.

An Improved Method for Identification of LDPC Codes Within a Candidate Set

The identification of low-density parity-check (LDPC) codes with higher rate over a candidate set is more difficult than that of LDPC encoders with lower rate. For the given soft information on a received sequence, we present a method to compute the average Taylor polynomial of the syndrome posterior probability according to the parity-checks of the candidates. Simulation results show that the proposed method performs as well as the existing works when dealing with lower rate encoders. Meanwhile, our method outperforms the existing works in higher rate encoders identification, with the gain being about 0.5 dB.

Error Correction LDPC Encoder with Bit-Flipping Decoder

The communication method conveys information from the transmitter to the receiver over an intermediate medium. The competence of received information is determined by medium and clatter. There is a great need for robust error correction techniques with ever accumulative usage of wireless expedients such as portable electronic items and broadband modems. Wireless communication schemes depend on advanced error rectification techniques for their suitable functioning. Hence transferring and getting information with less or without error, while utilizing the accessible bandwidth is a foremost proposal, project necessities for present digital wireless communication systems comprising of high throughput, low power consumption, and less area. In this article, the functional analysis is performed for error control coding technique i.e., Low-Density-Parity-Check (LDPC) coding in terms of device utilization and power. The functional verification and the simulation are performed using Verilog HDL. Error correction techniques such as Linear block codes, RS codes, Convolutional codes are employed to implement forward error correction but as the constraint length increases the design of decoders becomes more complex. LDPC is a type of block code that is capable of correcting random errors. They are popular because of their eminent detection and correction capabilities. LDPC encoding technique provides high throughput and aims to improve BER when compared to conventional techniques. The decoding of LDPC codeword employs the Message Passing Algorithm, where each bit in a codeword is allocated to special nodes. The performance of these codes is hence better and easily attains Shannon’s limit than the previously used codes. Synthesis for the technique is performed and utilization reports are derived from the synthesis in Vivado.

Reliability Analysis of the Sum-Product Decoding Algorithm for the PSK Modulation Scheme

Iteratively decoding and reconstruction of encoded data has been considered in recent decades. Most of these iterative schemes are based on graphical codes. Messages are passed through space graphs to reach a reliable belief of the original data. This paper presents a performance analysis of the Low-Density Parity-Check (LDPC) code design method which approach the capacity of the Additive White Gaussian Noise (AWGN) model for communication channels. We investigate the reliability of the system under Phase Shift Keying (PSK) modulation. We study the effects and advantages of variation in the codeword length, the rate of parity-check matrix of the LDPC codes, and the number of iterations in the Sum-Product Algorithm (SPA). By employing an LDPC encoder prior to the PSK modulation block and the SPA in the decoding part, the Bit Error Rate (BER) performance of the PSK modulation system can improve significantly. The BER performance improvement of a point-to-point communication system is measured in different cases. Our analysis is capable for applying any other iterative message-passing algorithm. The code design process of the communication systems and parameter selection of the encoding and decoding algorithms are accomplished by considering hardware limitations in a communication system. Our results help to design and select paramours efficiently.

A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees

This article proposes an encoding method based on a two-step encoding algorithm for the 12 quasi-cyclic (QC)-low-density parity-check (LDPC) (QC-LDPC) codes specified in the IEEE 802.11n/ac/ax standards. The proposed approach jointly considers all codes of the particular set, instead of targeting each code separately. The proposed algorithm performs multiplication by inverse matrices. The complexity of the multiplications is significantly reduced by the introduced encoding method. It allows the implementation of full-parallel architectures that execute the encoding process within a single clock cycle, or more for pipelined implementations, for any of the supported codes. A corresponding VLSI encoding architecture based on XOR-gate trees is also proposed. The proposed solution exploits the structure and features of the involved matrices to extract common subexpressions (CSs) using common sub-expression sharing techniques (CSST). Such expressions result due to common features of the original matrices and the corresponding inverses, identified in this article. Innovative subexpression extraction procedures that target the specific codes as a set are introduced here. Furthermore, illustrative single-clock hardware encoders derived by the proposed technique are integrated into 90- and 45-nm technologies at 1 GHz occupying 125 and 107 KGates, respectively, achieving throughput rates up to 1.62 Tbps.

Bandwidth efficient frame structures for flip OFDM with phase conjugated sub carriers and LDPC encoding

The paper presents two modified frame structures for flipped OFDM over optical fiber. Conventional flipped OFDM carries two different frames back to back with positive samples and negative samples with flipped polarity. Almost half of the subcarriers in each frame are loaded with zeros. Conventional flipping enhances the spectral efficiency compared to asymmetrically clipped optical OFDM (ACO-OFDM) but also increases the noise variance at receiver. Proposed flipped OFDM structures are time compressed versions of conventional flipped OFDM. This results in the final flipped OFDM with frame duration which is only half as compared to that in conventional OFDM. Simulation results show that time compression increases the bandwidth efficiency (bits/s Hz−1) along with DC electrical power. Proposed flipped OFDM frames show significant improvement in error performance over single mode fiber of 50 km length at 10 Gbps data rate and low density parity check (LDPC) codes. For nonlinearity and dispersion compensation, phase conjugated subcarrier coding (PCSC) is performed before the inverse fast Fourier transform (IFFT) calculation in OFDM generation, which further improves the fiber length reach capacity by almost 11 km and 2 km respectively in both the proposed flipped OFDM frame structures when compared to conventional flipped OFDM frame structure.