Low-density Parity-check Decoder Research Articles

Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories

With the development of NAND flash memories’ bit density and stacking technologies, while storage capacity keeps increasing, the issue of reliability becomes increasingly prominent. Low-density parity check (LDPC) code, as a robust error-correcting code, is extensively employed in flash memory. However, when the RBER is prohibitively high, LDPC decoding would introduce long latency. To study how LDPC performs on the latest 3D NAND flash memory, we conduct a comprehensive analysis of LDPC decoding performance using both the theoretically derived threshold voltage distribution model obtained through modeling (Modeling-based method) and the actual voltage distribution collected from on-chip data through testing (Ideal case). Based on LDPC decoding results under various interference conditions, we summarize four findings that can help us gain a better understanding of the characteristics of LDPC decoding in 3D NAND flash memory. Following our characterization, we identify the differences in LDPC decoding performance between the Modeling-based method and the Ideal case. Due to the accuracy of initial probability information, the threshold voltage distribution derived through modeling deviates by certain degrees from the actual threshold voltage distribution. This leads to a performance gap between using the threshold voltage distribution derived from the Modeling-based method and the actual distribution. By observing the abnormal behaviors in the decoding with the Modeling-based method, we introduce an Offsetted Read Voltage ( Δ RV) method, for optimizing LDPC decoding performance by offsetting the reading voltage in each layer of a flash block. The evaluation results show that our Δ RV method enhances the decoding performance of LDPC on the Modeling-based method by reducing the total number of sensing levels needed for LDPC decoding by 0.67% to 18.92% for different interference conditions on average, under the P/E cycles from 3000 to 7000.

Energy-Efficient Partial LDPC Decoding for NAND Flash-Based Storage Systems

A new decoding method for low-density parity-check (LDPC) codes is presented to lower the energy consumption of LDPC decoders for NAND flash-based storage systems. Since the channel condition of NAND flash memory is reliable for most of its lifetime, it is inefficient to apply the maximum-effort decoding with the full parity-check matrix (H-matrix) from the beginning of the lifespan. As the energy consumption and the decoding latency are proportional to the size of the H-matrix used in decoding, the proposed algorithm starts the decoding with a partial H-matrix selected by considering the channel condition. In addition, the proposed partial decoding provides various error-correcting capabilities by adjusting the partial H-matrix. Based on the proposed partial decoding algorithm, a prototype decoder is implemented in a 65 nm CMOS process to decode a 4 KB LDPC code. The proposed decoder reduces energy consumption by 93% compared to the conventional LDPC decoding architecture at maximum.

A Quasi-Cyclic LDPC Based Low Complexity and Area-Efficient Communication System for IEEE 802.11n

Low-density parity-check (LDPC) code, which has an excellent error-correcting performance that is close to the Shannon limit, is the most often used error correction code (ECC) for reliable and effective communication. Despite higher performance and lower decoding complexity, the main disadvantage of LDPC codes is their high encoding complexity. A significant problem is the VLSI implementation of the LDPC encoder and decoder. In this paper, structured LDPC codes—also known as quasi-cyclic low-density parity check codes—have been used since it is good bit error ratio (BER) performance and adaptable hardware execution characteristics. The Complete (Encoder-Channel-Decoder) communication system with a 1/2 code rate, 648 bits codeward length, and sub-block size of z = 27 has been constructed for the IEEE 802.11n wireless standard.

Iterative Equalization and Decoding over an Additive White Gaussian Noise Channel with ISI Using Low-Density Parity-Check Codes

In this article we present an iterative system of equalization and decoding to manage the intersymbol interference over an additive white Gaussian noise (AWGN) channel. Following the classic turbo equalization scheme, the proposed system consists of low-density parity-check (LDPC) coding at the transmitter side; we applied a Log maximum a posteriori probability (Log-MAP) equalizer and min-sum LDPC decoding at the receiver side. The equalizer and decoder, linked through interleaving and deinterleaving, iteratively update each other’s information. We performed the performance analysis of the proposed system, bit error rate (BER) vs. signal-to-noise ratio (SNR), considering three different impulse responses of the channel (h). Our experimental results indicated that increasing the number of iterations performed by the LDPC decoder from 10 to 20 during the iterative process of equalization and decoding leads to better outcomes. The proposed system was compared with turbo equalization and separate equalization, performed before the decoding process with minimum mean-square error (MMSE) and LDPC decoding, in terms of BER vs. SNR, considering the three different h. Based on the analyzed results, it can be concluded that the equalization performance depends on both the impulse responses of the channel and the chosen decoding and equalization method; therefore, the equalization method does not always offer good results for any h.

High-speed information reconciliation with syndrome-based early termination for continuous-variable quantum key distribution.

Information reconciliation (IR) is an indispensable component in the post-processing stage of continuous-variable quantum key distribution (CV-QKD), which adopts error-correcting codes to address the asymmetry of secret keys. Currently, low-density parity-check (LDPC) decoding in IR is a post-processing bottleneck in high-speed CV-QKD systems since the upper bound on secret key rate is higher than the information throughput delivered by decoder. In this paper, we study the relationship between the syndrome variation pattern (SVP) in iterative decoding and reconciliation frame error rate. An early termination scheme based on SVP is proposed and applied to multidimensional reconciliation, which can increase information throughput by adaptively adjusting the iteration number of iterative decoding to real-time decoding status. Furthermore, we show that only the resulting syndrome of the highest-rate code part in Raptor-like LDPC codes needs to be calculated to verify whether the reconciliation is successful by studying the convergency of resulting syndrome, which can save a large fraction of computational resources for syndrome calculation. Simulation results show that information throughput of the proposed scheme can be improved by 617.1% compared to the existing scheme when the IR efficiency reaches 97.09%. The proposed scheme points out a new direction for breaking the post-processing bottleneck in high-speed CV-QKD systems.

Efficient Layered Parallel Architecture and Application for Large Matrix LDPC Decoder

For a 50G passive optical network (PON) low-density parity-check (LDPC) decoder, decoding performance and area efficiency must be balanced. This paper adopts a layered decoder method to improve the area efficiency of the decoder. By parallel processing of three submatrices and storage reuse of node information, optimizing the matrix partitioning and processing order of the 50G-PON standard, the throughput of 1235 bps was reached under 100 MHz circuit frequency in field-programmable gate array (FPGA) implementation, and 9.864 Gbps was achieved based on Taiwan semiconductor manufacturing company (TSMC) 65 nm synthesis with 800 MHz circuit frequency in an area of 2.61 mm2 by proposing a mechanism of spare decision storage to avoid errors caused by quantization overflow of the decoder and using full verification to terminate decoding in advance to improve performance. Finally, at an input bit error rate (BER) of 2.3×10−2 (signal-to-noise ratio (SNR) of about 3.72 dB), the output BER was lower than 10−12, and the throughput area rate (TAR) also increased by 2 to 4 times compared with other papers. In conclusion, an area-efficient LDPC decoder without sacrificing decoding performance is made.

Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories

Low Density Parity Check (LDPC) codes are used in 5G systems for traffic channels due to their excellent error correction capability for long sequences, and the Min-Sum algorithm is widely applied in practical implementations of LDPC decoders due to its low complexity. If the decoder is implemented on a SRAM-based field-programmable gate array (SRAM-FPGA), the radiation-induced single-event upsets (SEUs) can affect the operation of the LDPC decoder by corrupting the configuration memory, which can change the circuit functionality and will not be corrected unless the FPGA is reconfigured. Therefore, protection of LDPC decoders with low overhead is an important problem, especially for resource-limited on-board space systems. In this paper, an efficient Duplicate With Comparison (DWC) protection scheme is proposed based on the different distribution of the parity check sum of the LDPC decoder in the error-free case and the faulty case. In particular, the check sum accumulation number and threshold are optimized to achieve high detection probability with short delay. FPGA based implementation and hardware fault injection experiments are conducted to evaluate the performance of the proposed schemes. Experimental results show that, the effect of SEUs on the LDPC decoder can be completely eliminated by the proposed scheme with 2 times computational overhead and 1.69 times power consumption overhead compared to the unprotected decoder.

High Throughput and Hardware Efficient Hybrid LDPC Decoder Using Bit-Serial Stochastic Updating

Hybrid low-density parity-check (LDPC) decoding combines conventional Belief-Propagation (BP) algorithm with stochastic decoding to achieve high performance and low complexity simultaneously. However, lossy and inefficient stochastic-to-binary (S2B) conversion brings extra performance degradation and decoding latency. In this paper, a bit-serial stochastic updating based hybrid decoding (BSSU-HD) is proposed, which employs fully correlated stochastic (FCS) check nodes (CNs) and probability tracers assisted variable nodes (VNs) to accomplish accurate and efficient S2B conversion. Two strategies, including random source selection and tracing speed switching, are proposed to further improve performance and convergence. A BSSU LDPC decoder for IEEE 802.3an is designed in a 65-nm CMOS process, which occupies 4.6 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> silicon area and achieves a throughput of 200.8 Gb/s at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E_b/N_0 = 4.4$</tex-math> </inline-formula> dB with 500 MHz clock frequency from a 1.2 V supply voltage. The power and energy efficiency are 2.933 W and 14.61 pJ/bit, respectively. To the best of our known, it achieves the best decoding performance, the highest throughput and hardware efficiency among state-of-the-art IEEE 802.3an LDPC decoders. We also verify that the BSSU-HD can achieve better performance for multi-rate 5th generation (5G) New Ratio (NR) LDPC codes than conventional algorithm, which greatly extends the application of the stochastic decoding.

An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder

A hardware-efficient implementation of a Low-Density Parity-Check (LDPC) decoder is presented in this paper. The proposed decoder design is based on the Hybrid Offset Min-Sum (HOMS) algorithm. In the check node processing of this decoder, only the first minimum is computed instead of the first two minimum values among all the variable-to-check message inputs as in the conventional approach. Additionally, taking advantage of the unique structure of 5G LDPC codes, layered scheduling and partially parallel structures are employed to minimize hardware costs. Implementation results on the Xilinx Kintex UltraScale+ FPGA platform show that the proposed decoder can achieve a throughput of 2.82 Gbps for 10 decoding iterations with a 5G LDPC codelength of 8832 bits and a code rate of 1/2. Moreover, it yields a check node memory reduction of 10% with respect to the baseline and provides a hardware usage efficiency of 4.96 hardware resources/layer/Mbps, while providing a decoding performance of 0.15 dB better than some of the existing decoders.

Bootstrapped low complex iterative LDPC decoding algorithms for free-space optical communication links

In recent years, much research has been devoted to free-space optical communication (FSO). The unregulated spectrum, low implementation costs, and robust security of FSO systems all are of great importance which lead to a wide range of applications for FSO links, from terrestrial communications to satellite communications. However, the fundamental limitation with FSO links is atmospheric turbulence (AT) caused by fading, significantly reducing link performance. Random phenomena are the best characteristic of atmospheric turbulence caused by changes in the air’s refractive index over time. Numerous probability density functions of the AT models were presented to model the randomness in AT channels. The Log-Normal (LN) channel model is for weak atmospheric turbulence, while the Gamma–Gamma (G–G) channel is selected for moderate and strong atmospheric turbulence. The impacts of geometric losses, attenuation due to weather, and errors due to misalignment are addressed using LN and G–G channels. Channel coding is one of the possible solutions for mitigating such FSO channel impairments as the low-density parity check (LDPC) codes. In this article, the Weighted Bit Flipping (Algorithm (1)), Implementation Efficient Reliability Ratio Weighted Bit Flipping (Algorithm (2)), and Min-Sum (Algorithm (3)) algorithms are compared and evaluated against FSO atmospheric turbulence channels. In addition, two novel algorithms are proposed to enhance the complexity or Bit Error Rate performance of LDPC decoding over FSO channels. The results showed an impressive improvement of the coded FSO system by employing the proposed algorithms compared to the existing LDPC decoders for FSO communications from the point of all comparison parameters.

A Hybrid Scheme Combining Duplications and LDPC Decoding to Reduce NAND Flash

Abstract With the development of NAND flash, the storage density has become larger and larger, but the reliability has become lower and lower. To address this problem, stronger error correction codes, low-density parity-check (LDPC) codes, are widely used in flash memory. However, the direct use of LDPC codes for error correction has a great impact on the read and write performance of SSDs. Given this, this paper proposes a new mentality that combines replica and LDPC decoding methods to improve the read performance of solid state drives (SSDs). Considering the characteristics of the quantization level of LDPC soft-decision decoding, this paper proposes the IDSD (LDPC soft-decision decoding and duplication method) and IDHSD (a method combining duplication and LDPC hybrid decoding)schemes. These schemes are mainly for hot data. When reading the data, the IDSD scheme needs to first judge whether it is soft-decision decoding. Then, according to the number of quantization levels recorded, it needs to select whether to use duplication or soft-decision decoding to correct the error data. The IDHSD scheme does not need to judge the soft-decision decoding but directly uses the duplication after the hard-decision decoding fails. Both schemes reduce the average response time to a certain extent and optimize the read performance of the SSD. The experimental results show that compared with the Native Scheme, the average response delay time of the IDSD scheme decreases by 5–30% and the IDHSD scheme slashes by 5–38%. Compared with the Traditional Refresh Scheme, the average response delay time of the IDSD scheme cuts down by 1–30% and the IDHSD scheme lowers by 1–29%.

Fast phase error correction with reference beam-assisted LDPC coding for collinear holographic data storage.

Low-density parity-check (LDPC) coding is a significant technique for ensuring data reliability in phase-modulated holographic data storage. To accelerate LDPC decoding, we design reference beam-assisted LDPC coding for 4-level phase-modulated holography. The reliability of a reference bit is higher than that of an information bit during decoding because reference data are known during recording and reading processes. By considering the reference data as prior information, the weight of the initial decoding information (i.e., log-likelihood ratio (LLR) information) of the reference bit is increased during LDPC decoding. The performance of the proposed method is evaluated through simulations and experiments. In the simulation, compared with the conventional LDPC code with a phase error rate (PER) of 0.019, the proposed method can reduce bit error rate (BER) by 38.8%, uncorrectable bit error rate (UBER) by 24.9%, decoding iteration time by 29.9%, the number of decoding iterations by 14.8%, and improve decoding success probability by 38.4% approximately. Experimental results demonstrate the superiority of the proposed reference beam-assisted LDPC coding. The developed method can significantly decrease the PER, BER, the number of decoding iterations, and decoding time by using the real captured images.

Parity-Check Matrix Partitioning for Efficient Layered Decoding of QC-LDPC Codes

In this paper, we consider how to partition the parity-check matrices (PCMs) to reduce the hardware complexity and increase decoding throughput for the row layered decoding of quasi-cyclic low-density parity-check (QC-LDPC) codes. First, we formulate the PCM partitioning as an optimization problem, which targets to minimize the maximum column weight of each layer while maintaining a block cyclic shift property among different layers. As a result, we derive all the feasible solutions for the problem and propose a tight lower bound ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>LB</i></sub> on the minimum possible maximum column weight to evaluate a solution. Second, we define a metric called layer distance to measure the data dependency between consecutive layers and further illustrate how to identify the solutions with desired layer distance from those achieving the minimum value of ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>LB</i></sub> = 1, which is preferred to reduce computation delay. Next, we demonstrate that up-to-now, finding an optimal solution for the optimization problem with polynomial time complexity is unachievable. Therefore, both enumerative and greedy partition algorithms are proposed instead. After that, we modify the quasi-cyclic progressive edge-growth (QC-PEG) algorithm to directly construct PCMs that have a straightforward partition scheme to achieve ω <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>LB</i></sub> or the desired layer distance. Simulation results showed that the constructed codes have better error correction performance and achieve less average number of iterations than the underlying 5G LDPC codes.

Improving FEC layer frame for DVB-S2 link system based on 5G NR polar coding

Within the scope of this investigation, the MATLAB simulation code for digital video broadcasting–for satellite–second generation (DVB-S2) has been constructed. Forward error correction (FEC) rates as 3/5, 2/3, and 3/4 across additive white Gaussian noise (AWGN) and Rayleigh fading channels are used to evaluate the system's performance, mainly while working on quadrature phase-shift keying (QPSK), 8-ary phase-shift keying (8PSK), 16-ary amplitude phase-shift keying (16APSK), and 32-ary amplitude phase-shift keying (32APSK) official modulation types. The system's redesign has been achieved to investigate high performance and reliability based on a cascade of new radio (NR) fifth generation (5G) Polar coding with low-density parity-check (LDPC). Some signal-to-noise ratio (SNR) levels were changed when evaluated in contrast to the conventional model. It has been determined that five iterations of the LDPC decoder were performed. In comparison to the traditional model. The proposed design's performance accomplished the highest possible value for reducing the bit error rate (BER) value and investigated better-transmitted power gain for most testing cases.

A Review of Modern and Recent Studies on the Low-Density Parity-Check Technology Approach

Data theory coding is an excellent and well-known branch of study that has produced various crucial solutions to the insoluble challenges of safe data transfers. Last improvements in detecting error techniques have resulted in a significant increase in the use of low-density parity-check (LDPC) code to address critical concerns connected to secure data transfer. Until now, decent efforts have been performed on LDPC codes that target low complexity, high performance, and low bit error rate goals. The final aim of this review is to provide a recent literature understanding of modern improvements previously mentioned and in LDPC encoding and decoding (applicative and theoretical) techniques. A comparative scan of many remarkable LDPC decoding algorithms, 5G standard requirements, popular power management methods, and low-energy LDPC design studies is also shown. Lastly, conclusions are presented by outlining key study results, current concerns, and general thoughts on new research directions possibilities. Index Terms— low-density parity-check encoder/decoder (LDPC), error correction codes (ECC), forward error correction codes (FEC), parity check matrix(PCM).

Convolutional Neural Network-Based Media Noise Prediction and Equalization for TDMR Turbo-Detection With Write/Read TMR

This article considers a turbo-detection system that includes a convolutional neural network (CNN)-based equalizer, a Bahl-Cocke-Jelinek-Raviv (BCJR) trellis detector, a CNN-based media noise predictor (MNP), and a low-density parity-check (LDPC) channel decoder for two-dimensional magnetic recording (TDMR) in the presence of track misregistration (TMR). The input readings are passed to a 2-D partial response (PR) equalizer, which is either linear or CNN-based. The equalized waveforms are inputs to a 2-D BCJR detector, which generates log-likelihood-ratio (LLR) outputs. The CNN MNP is provided with BCJR LLRs to estimate signal-dependent media noise samples and feed them back to the BCJR. A second pass through the BCJR produces LLRs, which are decoded by an LDPC decoder; achieved areal density (AD) is computed from the LDPC code rate. Spatially varying read- and write-TMR models are developed. We investigate the performance of the proposed system on simulated TDMR readback waveforms generated by grain-switching probabilistic (GSP) simulations. We have two types of GSP datasets. Dataset #1 includes two 10 nm bit length (BL) datasets with 18 and 24 nm track pitch (TP). Dataset #2 has 11 nm BL and 15 nm TP. The comparison baseline is a 1-D BCJR detector with pattern-dependent noise prediction (PDNP) and soft intertrack interference (ITI) subtraction, referred to as 1-D PDNP with LLR exchange. The write-TMR and read-TMR are modeled as cross-track-independent downtrack-correlated random processes. In the presence of joint write- and read-TMR, the proposed turbo-detection system achieves 8.34% and 0.70% AD gain over 1-D PDNP with LLR exchange for TP 18 and 24 nm dataset #1, respectively, and is more robust to TMR compared to the baseline.

Simplified LDPC-assisted CNC algorithm for entropy-loaded discrete multi-tone in a 100G flexible-rate PON.

Passive optical networks (PONs) have been widely used in optical access networks to meet the requirement of the rapidly growing data traffic. However, the optical power budget of the worst optical network unit certainly limits the maximum capacity of PON. In this paper, we demonstrate a flexible-rate PON based on entropy-loaded clipping discrete multi-tone (DMT) for increasing the capacity. Meanwhile, clipping operation and simplified low-density parity-check (LDPC) assisted clipping-noise-cancellation (CNC) algorithm are proposed to improve the performance of DMT in peak-power constrained PON. In the simplified LDPC-assisted CNC algorithm, the iteration number of the sum-product algorithm in the LDPC decoding can be reduced to decrease the computational complexity almost without performance loss. The experimental results show that the simplified CNC algorithm can achieve approximately 1.8dB improvement of the optical receiver sensitivity at the 20% soft-decision forward-error-correction limit. The proposed flexible-rate PON has a wide-range data-rate adjustment from 12.5Gb/s to 100Gb/s under the optical power budget from 40dB to 26dB.

Normalized Min-Sum Neural Network for LDPC Decoding

The success of deep learning has encouraged its applications in decoding error-correcting codes, e.g., LDPC decoding. In this paper, we propose a model-driven deep learning method for normalized min-sum (NMS) low-density parity-check (LDPC) decoding, namely neural NMS (NNMS) LDPC decoding network. By unfolding the iterative decoding progress between checking nodes (CNs) and variable nodes (VNs) into a feed-forward propagation network, we can harvest the benefits of both the model-driven deep learning and the conventional normalized min-sum (NMS) LDPC decoding method. In addition, we proposed a shared parameters NNMS with the LeakyReLU and a 12-bit quantizer (SNNMS-LR-Q) which reduces the number of required multipliers and correction factors by sharing parameters, increasing the nonlinear fitting ability by adding LeakyReLU. By utilizing the 12-bit quantizer, we can improve the confrontation ability. Thorough experiments with different code lengths, code rates, channel conditions, and check matrices are implemented to demonstrate the advantages and robustness of our proposed networks. The BER performance of the proposed NNMS is 1.5 dB better than the NMS, using fewer iterations. Meanwhile, The SNNMS-LR-Q outperforms the NNMS regarding the BER performance and efficiency.

Algorithmic Obfuscation for LDPC Decoders

In order to protect intellectual property against untrusted foundry, many logic-locking schemes have been developed. The main idea of logic locking is to insert a key-controlled block into a circuit to make the circuit function incorrectly without right keys. However, in the case that the algorithm implemented by the circuit is naturally fault-tolerant or self-correcting, existing logic-locking schemes do not affect the system performance much even if wrong keys are used. One example is low-density parity-check (LDPC) error-correcting decoder, which has broad applications in digital communications and storage. This paper proposes two algorithmic-level obfuscation methods for LDPC decoders. By modifying the decoding process and locking the stopping criterion, our new designs substantially degrade the decoder throughput and/or error-correcting performance when the wrong key is used. Besides, our designs are also resistant to the SAT, AppSAT and removal attacks. For an example LDPC decoder, our proposed methods reduce the throughput to less than 1/3 and/or increase the decoder error rate by at least two orders of magnitude with only 0.33% area overhead.

A Low-Complexity RS-SPC Product Coding Scheme for Optical Systems

This paper presents a product coding scheme based on binary images of Reed-Solomon (RS) codes and single-parity-check (SPC) codes for high-speed communications. Utilizing the special selection of components, we propose hybrid soft- and hard-decision iterative decoding (ID) algorithms for these codes, during which many RS component decoders can be early terminated. The proposed hybrid ID only exchanges ternary messages between component decoders and early stops the RS component decoders satisfying a proposed stopping criterion, thus low hardware and computational complexities are guaranteed. The hybrid ID of RS-SPC product codes not only performs comparable to the soft-decision decoding of low-density parity-check (LDPC) codes and block turbo codes (BTCs), but also takes much lower computational complexity and smaller decoder data flow. We also propose semi-analytical methods to estimate the waterfall and error-floor performances of the proposed scheme, which yield relatively accurate estimated results. The simulation results and error-floor estimations indicate that some good RS-SPC product codes have very low error floors that satisfy the requirements of optical systems.