Low-cost CMOS Technology Research Articles

Robustly Operating: Passive Near-Field Communication Systems in Metal Environments

The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Internet of Things</i> ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IoT</i> ) refers to a structure that links everyday objects and the Internet. To enable the IoT, a massive deployment of wireless IoT nodes is required; predictions indicate that trillions of these nodes will be needed. This trend raises sustainability issues on environmental, economic, and societal levels. Concerning environmental and economic problems, a significant design challenge is to create wireless IoT nodes that operate at ultralow power to avoid the ecotoxicity of batteries and the prohibitive maintenance costs of battery replacement <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> . Another design challenge is to reach high levels of integration based on low-cost CMOS technologies <xref ref-type="bibr" rid="ref2" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[2]</xref> to limit the carbon footprint and costs associated with the nodes’ production and end of life. Concerning societal issues, a significant design challenge is to guarantee the security and privacy of data in IoT nodes.

Analysis and Design of a Non-Magnetic Bulk CMOS Passive Circulator Using 25% Duty-Cycle Clock.

A circulator, which is a non-reciprocal device, is widely used in full-duplex systems, future communication and sensing networks, and quantum computing, and it is difficult to implement a passive topology on a chip. Based on switch-based spatio-temporal conductivity modulation, in this study, we design and implement a non-magnetic on-chip passive circulator operating at the Ku band in a 90-nm bulk CMOS technology using a 25% duty-cycle I/Q clock signal. With the virtue of the four-phase non-overlapping clock signal, the proposed circulator achieves a 3.9 dB transmitter (TX)-to-antenna (ANT) and a 4.0 dB ANT-to-receiver (RX) insertion loss with a 1-dB bandwidth of 2.7 GHz (21.4%). The TX-to-RX isolation is better than 17.2 dB, and the TX-to-ANT IIP3 and ANT-to-RX IIP3 are 19.7 dBm and 20.0 dBm, respectively, while occupying a die area of 1.55 mm × 1.15 mm. Although low-cost bulk CMOS technology is used, competitive isolation, linearity performance, and isolation bandwidth are achieved in the proposed design.

A 0.31-THz Orbital-Angular-Momentum (OAM) Wave Transceiver in CMOS With Bits-to-OAM Mode Mapping

This article reports the first chip-based demonstration (at any frequency) of a transceiver front end that transmits and receives electromagnetic waves with a helical distribution of wavefront phase [namely, orbital angular momentum (OAM)]. The CMOS chip consists of eight 0.31-THz modulator/detector units, with an integrated patch antenna, which are placed in a uniform circular pattern with a diameter of one free-space wavelength. The chip transmits OAM modes that are digitally switched among the <inline-formula> <tex-math notation="LaTeX">$m\,\,=0$ </tex-math></inline-formula> (plane wave), &#x002B;1 (left-handed), &#x2212;1 (right-handed), and <inline-formula> <tex-math notation="LaTeX">$(+1)+(-1)$ </tex-math></inline-formula> (superposition) states. The chip is also reconfigurable into a receiver mode that identifies different OAM modes with &#x003E;10-dB rejection of mismatched modes. The array, driven by only one 310-GHz signal generation path, has a measured EIRP of &#x2212;4.8 dBm and consumes 154 mW of dc power in the OAM source mode. In the receiver mode, it has a measured conversion loss of <inline-formula> <tex-math notation="LaTeX">$\sim 30$ </tex-math></inline-formula> dB and consumes 166 mW of dc power. Using a low-cost 65-nm bulk CMOS technology, the terahertz (THz)-OAM chip has an area of only 2.1 <inline-formula> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 2.6 mm², which is the smallest among all prior OAM prototypes. The output OAM beam profiles and modes&#x2019; orthogonality are experimentally verified. The dynamic mode switching capability of the chip is also verified in the time domain across 1-m distance, and a full-silicon OAM link is demonstrated.

A 193-nW Wake-Up Receiver Achieving −84.5-dBm Sensitivity for Green Wireless Communications

This paper presents a cost-effective, ultra-low-power and highly sensitive wake-up receiver (WuRX) to reduce overall power consumption of Wireless Sensor Networks (WSN). The proposed tuned radio frequency (TRF) receiver (RX) analogue front-end (AFE) incorporates a 400-MHz, low-power, low-noise amplifier (LNA) with a high voltage gain of 50 dB as well as a Gilbert Cell based envelop detector achieving a conversion gain of 224V^&#x2212;1 to enhance the overall sensitivity of the WuRX. Meanwhile, a duty-cycling technique is used to reduce the power consumption of the WuRX AFE. In addition, a 31-bit correlator is implemented in the WuRX digital back-end (DBE) to further improve the sensitivity of the WuRX by 4 dB. A proof-of-concept WuRX circuit prototype has been fabricated in a low-cost 180-nm CMOS technology. Measurement results show the complete WuRX attains a sensitivity of &#x2212;84.5 dBm at a wake-up error rate (<i>WER</i>) of 10^&#x2212;3 whilst only consuming 193nW at the minimum data rate of 64 bps with a carrier frequency of 402 MHz. With the sensitivity unchanged, the data rate of the WuRX can be scaled up from 64 bps to 8.2 kbps. The used 4-time oversampling technique makes the WuRX robust against asynchronization and clock deviation between the TX and RX. The proposed WuRX is a promising solution for energy-efficient rendezvous between wireless sensor nodes, particularly in application scenarios where both low power consumption and high sensitivity are indispensable.

Integrated Stacked Parallel Plate Shunt Capacitor for Millimeter-Wave Systems in Low-Cost Highly Integrated CMOS Technologies

This letter presents a stacked parallel plate (SPP) shunt capacitor (SC) that benefits from metal stack increment with process nodes advancement. It demonstrated high quality (Q) factor and high self-resonance frequency (SRF), promoting the design of analog integrated circuits (IC) in low-cost highly-integrated CMOS technologies at millimeter-wave (mm-wave) frequency range. As a proof-of-concept, an analytical-equation based design method is also proposed and three ac-grounded capacitors: 300-fF, 600-fF and 900-fF, are implemented in STMicroelectronics (STM) 55-nm process. Characterization is performed up to 100 GHz. An effective capacitance density of 0.8 fF/μm2 is obtained. Measurements show Q-values reaching up to 14.7 at 100 GHz and equivalent input series resistances with flat wide band behavior reaching at most an average of 0.55 Ω. SRFs of 140 GHz for the 900-fF SPP-SC up to 368 GHz for the 300-fF SPP-SC are also determined from measurements: the highest SRFs for such large capacitances to the authors’ knowledge.

28–38-GHz 6-bit Compact Passive Phase Shifter in 130-nm CMOS

In this letter, a highly compact, bidirectional, wideband 6-bit resolution passive phase shifter (PS) is presented in low-cost 130-nm CMOS technology. A compact Lange differential hybrid is designed in this letter to provide quadrature signals from the input. The compact Lange hybrid is followed by a switching matrix that generates weighted sums of the quadrature signals to cover 360° and additional controlled loss using single pole single throw (SPST) switches. The matrix consists of 12 transistors, each of which is controlled by a three-level gate voltage (0, 0.6, and 1.2 V) providing higher resolution in phase shifts. The chip achieves the state-of-the-art performance with 10-dB insertion loss across 28–38 GHz. The chip also achieves an rms gain error of 0.6 dB and an rms phase error of 3° in the bandwidth, consuming no dc power and only 0.15 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including baluns.

Exploiting Parasitic Capacitances in 3-D Inductors to Design RF CMOS Quasi-Elliptic-Type Broad-Band Bandpass Filters

A class of RF broad-band bandpass filter (BPF) with quasi-elliptic-type response in low-cost bulk CMOS technology is reported. It is based on the in-series cascade connection of lowpass and highpass filtering stages with 3-D inductors, whose parasitic capacitances are properly exploited. Specifically, they are used to transform the basic inductor into an LC tank, thus allowing to generate an upper transmission zero (TZ) that increases filtering selectivity and out-of-band power-rejection levels in a spurious-free/extended upper stopband. The layout of a basic third-order BPF cell shaped by four 3-D inductors and its lossless equivalent lumped-element circuit are detailed. By means of this lossless equivalent lumped-element model, its scalability to higher-order BPF designs by in-series cascading various BPF-cell replicas is also demonstrated. For experimental-validation purposes, an on-chip RF CMOS BPF prototype with 11-GHz center frequency and 68.5% 3-dB fractional bandwidth is developed using a 0.13- μm bulk CMOS technology. According to the measured results, it shows an upper stopband with minimum attenuation of 31.7 dB from 22.5 GHz to 67 GHz, alongside with TZs at 3.5 GHz and 22.5 GHz to produce sharp-rejection filtering.

Processing Electrocardiographic Signals Using a Custom Designed Sigma-Delta Modulator

This paper introduces the experimental results obtained after processing an electrocardiographic signal by a full-custom, low-complexity, Sigma-Delta Modulator integrated circuit, designed and fabricated using the C5N CMOS technology available through MOSIS. By exploiting a large oversampling ratio, it was possible to obtain an effective number of bits equal to 11 at the proposed single-bit modulator’s output. The resulting bitstream was captured with a logic-state analyzer and processed offline. After decimation and digital filtering, the electrocardiographic signal was reconstructed and plotted in the time domain. Commonly referred quality metrics over the retrieved signal were calculated. A total signal-to-noise and distortion ratio, superior to 66[Formula: see text]dB, was achieved by analyzing the entire system. The proposed approach shows the feasibility of processing electrocardiographic signals using low-cost and straightforward CMOS technology circuits. Since the proposed converter uses a single voltage supply of 1.5[Formula: see text]V, exhibits a power consumption of 38[Formula: see text][Formula: see text]W, and uses a silicon area of 0.052[Formula: see text]mm2, it is suitable for single battery-operated systems on a chip.

CMOS THz-ID: A 1.6-mm² Package-Less Identification Tag Using Asymmetric Cryptography and 260-GHz Far-Field Backscatter Communication

This article presents an ultra-small, high-security identification tag that is entirely built in a CMOS chip without external components. The usage of backscatter communications at 260 GHz enables full integration of a 2 × 2 patch antenna array. For chip compactness and minimum interference caused by direct wave reflection, the backscatter signal is frequency-shifted by 2 MHz and radiated with cross polarization from the same antenna array. Such a configuration also, for the first time for RF tags, enables beamsteering for enhanced link budget. For authentication and secure wireless data transmission, the tag also integrates a compact elliptic-curve-cryptography (ECC) dedicated processor, which is based on a narrow-strong private identification protocol. The presented tag has a peak power consumption of 21 μW and can be powered by a chip-wide array of photodiodes and a DC-DC converter. Using a low-cost 65-nm bulk CMOS technology, the terahertz (THz) ID chip has an area of only 1.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and demonstrates the measured downlink speed of 100 kb/s and the upload speed of 2 kb/s across 5-cm distance from the reader. The tag-reader authentication/communication protocol is fully demonstrated using external tag power and partially demonstrated using the tag-integrated photo-voltaic powering. The tag size is the smallest among all prior radio-frequency identifications (RFIDs) using far-field communications.

Channel-bonding CMOS transceiver for 100 Gbps wireless point-to-point links

5G systems and networks are expected to provide unprecedented data-rate to final users and services, in combination with increased coverage and density. The traffic generated at the edges of the network should be hauled through high capacity data-conveyors. Extremely high data-rate links able to provide optical-fiber like performance in the order of 100 Gbps are required to reduce the cost and increase the flexibility of the network infrastructure deployment. This paper presents a full transceiver architecture based on a channel-bonding radio-frequency front-end operating at millimeter-wave frequencies and digital baseband processing units able to provide such data-rates with a feasible implementation in low-cost CMOS technologies. The baseband section of the receiver includes digital compensation algorithms that allow to cope with some of the radio front-end impairments. The main functionalities of the proposed transceiver architecture are validated in hardware.

A Compact Calibration Model for Linearizing CMOS Sample-and-Hold Circuits

Intermediate-Frequency (IF) sampling demands stringent tracking bandwidth and linearity performance of analog-to-digital converters (ADCs), dictating high supply voltages and bipolar devices to implement the front-end buffer/sampler. As quantizers are nowadays almost exclusively realized in scaled CMOS technology, the integration of the high-voltage bipolar front-end and the low-voltage CMOS quantizer becomes a challenging task as cost, complexity, and power consumption are important competitive metrics for vendors. In this brief, we present a compact calibration model to linearize the sample-and-hold (S/H) circuits realized in low-cost CMOS technology for IF-sampling applications. Simulation and experimental results show that a spurious-free dynamic range (SFDR) close to 100 dB can be achieved using the proposed technique.

A 30-GHz Digital Sub-Sampling Fractional-$N$ PLL With −238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS

This article describes the implementation of a 30-GHz frequency synthesizer. The target is to reduce the gap in terms of jitter-power product that exists between millimeter-wave and RF synthesizers, using a low-cost 65-nm LP CMOS technology. The circuit is a digitally intensive fractional- ${N}$ phase-locked loop, which combines a sub-sampling bang-bang phase detector, a low-power divider-by-six prescaler with a novel injection scheme, and a digital technique reducing the output range of the digital-to-time-converter. The synthesizer can operate between 30.4 and 34.2 GHz with a frequency resolution of 191 Hz and with an integrated rms jitter below 180 and 197.6 fs for the integer- ${N}$ and fractional- ${N}$ channels, respectively. The sub-sampling loop can synthesize fast sawtooth chirps around 33.4 GHz with peak-to-peak amplitudes up to 1.14 GHz. The fractional spurs, measured at the 5-GHz prescaler output, are below −54 dBc, even considering near-integer channels. The power dissipation of 35 mW from the 1.2-V supply leads to a −238.6 dB of jitter-power figure of merit for fractional- ${N}$ channels.

Bayesian estimation of physical and geometrical parameters for nanocapacitor array biosensors

Massively parallel nanosensor arrays fabricated with low-cost CMOS technology represent powerful platforms for biosensing in the Internet-of-Things (IoT) and Internet-of-Health (IoH) era. They can efficiently acquire “big data” sets of dependable calibrated measurements, representing a solid basis for statistical analysis and parameter estimation.In this paper we propose Bayesian estimation methods to extract physical parameters and interpret the statistical variability in the measured outputs of a dense nanocapacitor array biosensor. Firstly, the physical and mathematical models are presented. Then, a simple 1D-symmetry structure is used as a validation test case where the estimated parameters are also known a-priori. Finally, we apply the methodology to the simultaneous extraction of multiple physical and geometrical parameters from measurements on a CMOS pixelated nanocapacitor biosensor platform.

A Standard-Cell-Based All-Digital PWM Modulator With High Resolution and Spread- Spectrum Capability

The use of digital pulse-width modulators (DPWMs) as controllers for dc–dc converters is becoming more and more popular, due to the lower sensitivity to process variations, programmability, and easiness to translate complex control algorithm in digital architecture. DPWMs require high resolution to avoid limit cycling. Moreover, especially in high-frequency switching power converters, the reduction of the electromagnetic interference (EMI) is of primary importance. A novel DPWM circuit is proposed in this paper. The circuit uses only standard cells, easing portability to new technological nodes. The DPWM includes a coarse delay stage, based on an enhanced counter-based architecture, which is able to modulate both the frequency and duty cycle. As a result, the proposed DPWM supports spread-spectrum modulation, with arbitrary modulation law, to reduce the EMI. The DPWM also includes a fine delay stage that employs digitally controlled NAND-based delay lines with excellent linearity and resolution. A measurement unit is used to compensate at run time, the process, voltage, and temperature variations. The circuit has been fabricated in low-cost UMC 130-nm CMOS technology and is fit in a 44-pin package. The chip can generate spread-spectrum pulse-width waveforms up to 10 MHz. Measurement of the conducted EMI in buck dc–dc converter is reported in this paper.

Study of capacitance nonlinearity in nano-scale multi-stage MOSFET-only sigma-delta modulators

Digital integrated circuits (ICs) can be integrated in low-cost digital CMOS technologies with less number of masks than a mixed-signal CMOS technology. This property, however, limits the access to reliable analog components such as linear capacitors and linear inductors. Regardless of the CMOS process, sigma-delta (ΣΔ) modulation of analog signals can be fulfilled by using ordinary MOS devices as capacitors. Called as MOS capacitors (MOSCAPs), these elements illustrate nonlinear C-V characteristic, although the thin gate oxide layer results a high capacitance per unit area. In this article, we investigate the effect of MOS capacitance nonlinearity on the overall performance of discrete-time sigma-delta modulators. To this end, a behavioral-level model of a MOSFET-only switched-capacitor (SC) integrator is proposed, and enables characterizing the transfer behavior of MOSFET-only modulators. The proposed model is used to analyze the linearity and to select a suitable architecture for the modulator. It helps to decide proper structure of each MOSCAP depending on its significance on the output linearity. In virtue of the new model, behavioral-level simulation of a 1-V 12-bit 20MS/s MOSFET-only 2 + 2 sturdy MASH (SMASH) modulator matches well to circuit-level simulations in 90-nm digital CMOS technology. For a −1.4 dB, 19.7 kHz input and an oversampling ratio of 16, the modulator achieves over 72 dB signal-to-noise plus distortion ratio (SNDR), only 3 dB lower than a conventional design based on linear metal-insulator-metal (MIM) capacitors.

IC Design and Measurement of an Inductorless 48 V DC/DC Converter in Low-Cost CMOS Technology Facing Harsh Environments

With reference to 48-V systems, used in electric and hybrid vehicles and for telecom and networking power supply, this paper presents the circuit/transistor-level design, implementation, and test of an inductorless dc/dc converter. Its architecture is a cascade of three switched-capacitor converters with step-up/down capabilities plus linear converters, working in parallel at the end of the cascade. It provides multiple regulated voltages, which are isolated from input failures. The design also includes on-chip control unit and a serial interface toward an external host. Experimental tests carried out on the chip, fabricated in 0.35- $\mu \text{m}$ CMOS technology, proves that the design is suitable to face harsh operating environments, including the 48-V automotive one. Compared with the state-of-art, the proposed design stands for its wide input voltage regulation range, load/line regulation, power supply rejection ratio, and low electromagnetic interference emissions.

Linearized differential current sensor in low-voltage CMOS

PurposeThis work aims to improve upon the linearity of integrated CMOS current sensors used in switch mode power supply topologies, using a low-cost and low-voltage (less than 1.2 V) CMOS technology node. Improved sensor accuracy contributes to efficiency in switched supplies by reducing measurement errors when it is integrated with closed-loop control.Design/methodology/approachIntegrated current-sensing methods were investigated and CMOS solutions were prioritized. These solutions were implemented and characterized in the desired process and shortcomings were identified. A theoretical analysis accompanied by simulated tests was used to refine improvements which were prototyped. The current sensor prototypes were fabricated and tested.FindingsMeasured and simulated results are presented which show improved linearity in current sensor outputs. Techniques borrowed from analog amplifier design can be used to improve the dynamic range and linearity of current-steered CMOS pairs for measuring current. A current sensor with a gain of 5 V/A operating in a 10 MHz switch mode supply environment is demonstrated.Originality/valueThis paper proposes an alternative approach to creating suitable bias conditions for linearity in a SenseFET topology. The proposed method is compact and architecturally simple in comparison to other techniques.

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

Endpoint devices for Internet-of-Things not only need to work under extremely tight power envelope of a few milliwatts, but also need to be flexible in their computing capabilities, from a few kOPS to GOPS. Near-threshold (NT) operation can achieve higher energy efficiency, and the performance scalability can be gained through parallelism. In this paper, we describe the design of an open-source RISC-V processor core specifically designed for NT operation in tightly coupled multicore clusters. We introduce instruction extensions and microarchitectural optimizations to increase the computational density and to minimize the pressure toward the shared-memory hierarchy. For typical data-intensive sensor processing workloads, the proposed core is, on average, $3.5\times $ faster and $3.2\times $ more energy efficient, thanks to a smart L0 buffer to reduce cache access contentions and support for compressed instructions. Single Instruction Multiple Data extensions, such as dot products, and a built-in L0 storage further reduce the shared-memory accesses by $8\times $ reducing contentions by $3.2\times $ . With four NT-optimized cores, the cluster is operational from 0.6 to 1.2 V, achieving a peak efficiency of 67 MOPS/mW in a low-cost 65-nm bulk CMOS technology. In a low-power 28-nm FD-SOI process, a peak efficiency of 193 MOPS/mW (40 MHz and 1 mW) can be achieved.

A compact low-noise broadband digital picoammeter architecture

Abstract A low-noise (⩽4 fA/√Hz), broadband (⩾100 kHz) compact architecture and related operation solutions are proposed for portable and low-cost time-domain acquisition of currents with effective resolution in the order of 1 pA and below. The front-end architecture is based on an integrating-differentiating scheme to achieve the optimal performance in terms of input-referred equivalent noise, but it overcomes the typical noise/bandwidth trade-off by making the sampling frequency of the A/D conversion independent from the rate at which the analog front-end is reset. In order to strongly mitigate the main drawback, i.e., the introduction in the system of an inherent time-variance, a Track-and-Hold circuit synchronized with the reset is exploited. For validation purposes, a dual-channel prototype was implemented in a low-cost CMOS technology. The prototype is characterized by standard figures of merit and is experimentally validated by two simple case studies, which are typical of practical applications.

Integrated CMOS Optical Sensor for Light Spectral Analysis

In this paper, a fully integrated photo sensor in standard CMOS technology is reported, which enables light spectral analysis in the visible light range without additional optical components like color filters or gratings. The proposed sensor structure provides a continuously tunable spectral responsivity based on lateral carrier diffusion effects in combination with tunable field electrodes for defined carrier redirection. The tunable responsivity characteristics in combination with digital signal processing can be deployed for light spectral analysis like color measurements or full light spectral reconstruction. The realization of an accurate photometric color measurement based on the CIE X, Y, Z or R, G, B standard will be presented as an example for a basic light spectral analysis. Furthermore, the sensor application in a basic spectrophotometer is presented, providing a unique opportunity to realize a highly integrated low-cost spectrophotometer for basic spectral light measurements using a low-cost standard CMOS technology without process modification.