Low-complexity Chase Decoding Research Articles

Low-Complexity Chase Decoding of Reed-Solomon Codes Using Channel Evaluation.

A novel time-varying channel adaptive low-complexity chase (LCC) algorithm with low redundancy is proposed, where only the necessary number of test vectors (TVs) are generated and key equations are calculated according to the channel evaluation to reduce the decoding complexity. The algorithm evaluates the error symbol numbers by counting the number of unreliable bits of the received code sequence and dynamically adjusts the decoding parameters, which can reduce a large number of redundant calculations in the decoding process. We provide a simplified multiplicity assignment (MA) scheme and its architecture. Moreover, a multi-functional block that can implement polynomial selection, Chien search and the Forney algorithm (PCF) is provided. On this basis, a high-efficiency LCC decoder with adaptive error-correcting capability is proposed. Compared with the state-of-the-art LCC (TV = 16) decoding, the number of TVs of our decoder was reduced by 50.4% without loss of the frame error rate (FER) performance. The hardware implementation results show that the proposed decoder achieved 81.6% reduced average latency and 150% increased throughput compared to the state-of-the-art LCC decoder.

An Even/Odd Error Detection Based Low-Complexity Chase Decoding for Low-Latency RS Decoder Design

This letter presents a modified low-complexity chase (LCC) algorithm, where a fewer number of vectors can be tested with minor error correction performance degradation. The proposed LCC decoding pre-determines whether the number of errors in the received codeword is even or odd, and it processes only necessary test vectors. As a result, the number of test vectors can be reduced by half compared to the conventional LCC decoding. The Reed-Solomon (255,239) decoder with the proposed LCC algorithm has been implemented using 65nm CMOS process. The hardware implementation results show that the proposed decoder shows 48.5% reduced latency with 0.06 dB of coding gain decrease at $\mathbf {10^{-6}}$ codeword error rate compared to the state-of-the-art LCC decoder.

Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code

In this work, we present a new architecture for soft-decision Reed–Solomon (RS) Low-Complexity Chase (LCC) decoding. The proposed architecture is scalable and can be used for a high number of test vectors. We propose a novel Multiplicity Assignment stage that sorts and stores only the location of the errors inside the symbols and the powers of α that identify the positions of the symbols in the frame. Novel schematics for the Syndrome Update and Symbol Modification blocks that are adapted to the proposed sorting stage are also presented. We also propose novel solutions for the problems that arise when a high number of test vectors is processed. We implemented three decoders: a η = 4 LCC decoder and two decoders that only decode 31 and 60 test vectors of true η = 5 and η = 6 LCC decoders, respectively. For example, our η = 4 decoder requires 29% less look-up tables in Virtex-V Field Programmable Gate Array (FPGA) devices than the best soft-decision RS decoder published to date, while has a 0.07 dB coding gain over that decoder.

An Algorithm for Improving the Throughput of Serial Low-Complexity Chase Soft-Decision Reed–Solomon Decoder

A novel early termination algorithm (ETA) is proposed for the serial low-complexity chase (LCC) Reed–Solomon (RS) decoder. It can terminate the decoding procedure after the reencoding step conditionally, which results in the improvement of the serial LCC decoders’ speed. The ETA will not degrade the decoding performance of RS codes; on the contrary, it can even improve that of short RS codes remarkably. The simulations of the ETA for (3125) and (255,239) RS codes over the additive white Gaussian noise (AWGN) channel and a (458,410) RS code over the EPR4 channel with 100% AWGN show that it is effective. Moreover, the hardware implementation of the early terminated LCC decoder for (458,410) and (255,239) RS codes is provided. The analysis shows that it can work faster than the previous serial LCC decoder with only a few extra hardware costs. It also shows great advantages in average throughput performance than the common pipelined LCC decoders, especially for relatively high Eb/N0 values, by an overall consideration of the area, speed, and decoding performance.

Reduced-Complexity Multiplicity Assignment Algorithm and Architecture for Low-Complexity Chase Decoder of Reed-Solomon Codes

A reduced-complexity multiplicity assignment (RCMA) algorithm for low-complexity chase (LCC) is proposed for decoding Reed-Solomon (RS) codes. The properties of bit-level received voltages over an additive white Gaussian noise (AWGN) channel with binary modulation are explored. By using the properties, the hard-decision, secondary hard-decision, and unreliable positions can be easily determined, and hence, significantly reduce the computational complexity. Compared with the original multiplicity assignment (MA) algorithm, the RCMA eliminates $n^{2}\log_{2}n$ multiplication operations and reduces the number of comparison operations from $2n^{2}$ to $n\log_{2}n$ , where $n$ is the code length of an RS code. Moreover, a hardware design for RCMA is proposed and applied in the unified syndrome computation (USC) based LCC decoder. Implementation results show the throughput of the proposed decoder can reach a Gbps order, which meets the requirements of high-speed communications.

Efficient architecture for algebraic soft‐decision decoding of Reed–Solomon codes

Reed–Solomon (RS) codes possess excellent error correction capability. Algebraic soft-decision decoding (ASD) of RS codes can provide better correction performance than the hard-decision decoding (HDD). The low-complexity Chase (LCC) decoding has the lowest complexity cost and similar or even higher coding gain among all of the available ASD algorithms. Instead of employing complicated interpolation technique, the LCC decoding can be implemented based on the HDD. This study proposes a modified serial LCC decoder, which employs a novel syndrome calculation, polynomial selection, Chien search and Forney algorithm block. In addition, an improved two-dimensional optimisation is provided to reduce the hardware complexity of the proposed decoder. Compared with the previous design, the proposed decoder can improve about 1.27 times speed and obtain 1.29 times higher efficiency in terms of throughput-over-slice ratio.

Reduced-Complexity LCC Reed–Solomon Decoder Based on Unified Syndrome Computation

Reed-Solomon (RS) codes are widely used in digital communication and storage systems. Algebraic soft-decision decoding (ASD) of RS codes can obtain significant coding gain over the hard-decision decoding (HDD). Compared with other ASD algorithms, the low-complexity Chase (LCC) decoding algorithm needs less computation complexity with similar or higher coding gain. Besides employing complicated interpolation algorithm, the LCC decoding can also be implemented based on the HDD. However, the previous syndrome computation for 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">η</sup> test vectors and the key equation solver (KES) in the HDD requires long latency and remarkable hardware. In this brief, a unified syndrome computation algorithm and the corresponding architecture are proposed. Cooperating with the KES in the reduced inversion-free Berlekamp-Messy algorithm, the reduced-complexity LCC RS decoder can speed up by 57% and the area will be reduced to 62% compared with the original design for η = 3.

Low-power high-efficiency architecture for low-complexity chase soft-decision Reed–Solomon decoding

Algebraic soft-decision decoding (ASD) of Reed–Solomon (RS) codes can obtain significant coding gain over the hard-decision decoding with polynomial complexity. Compared with other ASD algorithms, the low-complexity chase (LCC) decoding testing 2η test vectors has less computation complexity with similar or better coding gain. To reduce the latency of the interpolation, one major step of the LCC decoding, multiple interpolators can be applied and the pipelined architecture is usually adopted to make the throughput of the decoder higher. However, for application specific integrated circuit (ASIC) implementation and practical applications, the area and power consumption of the pipelined decoder are not preferable. This study proposes a modified serial LCC decoder architecture which reduces the power consumption and hardware requirement while keeping the shortest critical path as one adder, one multiplexer and one multiplier. As major contributions of this study, a novel re-encoder and erasure decoder block and an improved way to compute syndromes are proposed to reduce the whole latency of the decoder. For a (458, 410) RS code over Galois Field (GF)(210) with η=8, the hardware requirement and power consumption of the proposed LCC decoder are reduced by 23 and 25% than those of the common pipelined counterparts, respectively.

Novel Interpolation and Polynomial Selection for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding

Algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes can achieve substantial coding gain with polynomial complexity. Particularly, the low-complexity Chase (LCC) ASD decoding has better performance-complexity tradeoff. In the LCC decoding, 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">η</sup> test vectors need to be interpolated over, and a polynomial selection scheme needs to be employed to select one interpolation output to send to the rest decoding steps. The interpolation and polynomial selection can account for a significant part of the LCC decoder area, especially in the case of long RS codes and large η . In this paper, simplifications are first proposed for a low-complexity polynomial selection scheme. Then a novel interpolation scheme is developed by making use of the simplified polynomial selection. Instead of interpolating over each vector, our scheme first generates information necessary for the polynomial selection. Then only the selected vectors are interpolated over. The proposed interpolation and polynomial selection schemes can lead to 162% higher efficiency in terms of throughput-over-area ratio for an example LCC decoder with η = 8 for a (458, 410) RS code over <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GF</i> (2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> ).

Systematically Re-encoded Algebraic Soft-Decision Reed–Solomon Decoder

To reduce the complexity of algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes, re-encoding and coordinate transformation can be applied. For an (n, k) code, the re-encoding was implemented as applying erasure decoding to the k most reliable code positions previously. Such re-encoding can occupy a significant part of the overall decoder area. In this brief, we propose to choose the first k positions and implement the re-encoding in the low-complexity Chase (LCC) ASD algorithm by systematic encoding, which can be done by simple constant multipliers. Moreover, novel schemes are developed to modify the following interpolation and codeword recovery steps in the case that systematic symbols need to be flipped to form the test vectors in the LCC decoding. Without any performance loss, the proposed schemes can lead to 15.5% higher efficiency in terms of throughput-over-area ratio in the LCC decoder with eight test vectors for a (255, 239) RS code over GF(28).

High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes

In this paper, a high-throughput interpolator architecture for soft-decision decoding of Reed-Solomon (RS) codes based on low-complexity chase (LCC) decoding is presented. We have formulated a modified form of the Nielson's interpolation algorithm, using some typical features of LCC decoding. The proposed algorithm works with a different scheduling, takes care of the limited growth of the polynomials, and shares the common interpolation points, for reducing the latency of interpolation. Based on the proposed modified Nielson's algorithm we have derived a low-latency architecture to reduce the overall latency of the whole LCC decoder. An efficiency of at least 39%, in terms of area-delay product, has been achieved by an LCC decoder, by using the proposed interpolator architecture, over the best of the previously reported architectures for an RS(255,239) code with eight test vectors. We have implemented the proposed interpolator in a Virtex-II FPGA device, which provides 914 Mb/s of throughput using 806 slices.

High-Speed RS(255, 239) Decoder Based on LCC Decoding

Algebraic Soft-Decision Decoding (ASD) of Reed–Solomon (RS) codes provides higher coding gain over the conventional hard-decision decoding (HDD), but involves high computational complexity. Among the existing ASD methods, the Low Complexity Chase (LCC) decoding is the one with the lowest implementation cost. LCC decoding is based on generating 2 η test vectors, where η symbols are selected as the least reliable symbols for which hard-decision or the second more reliable decision are employed. Previous decoding algorithms for LCC decoders are based on interpolation and re-encoding techniques. On the other hand, HDD algorithms such as the Berlekamp–Massey (BM) algorithm or the Euclidean algorithm, despite of their low computational complexity, are not considered suitable for LCC decoding. In this paper, we present a new approach to LCC decoding based on one of these HDD algorithms, the inversion-less Berlekamp–Massey (iBM) algorithm, where the test vectors are selected for correction during decoding on occurrence of hard-decision decoding failure. The proposed architecture when applied to a RS(255, 239) code with η=3, saves a 20.5% and 2% of area compared to the LCC with factorization and a factorization-free decoder, respectively. In both cases, the latency is reduced by 34.5%, which is an increase of throughput rate in the same percentage since the critical path is the same in all the competing architectures. So an efficiency of at least 56% in terms of area-delay product can be obtained, compared with previous works. A complete RS(255, 239) LCC decoder with η=3 has been coded in VHDL and synthesized for implementation in Vitex-5 FPGA device, and by using SAED 90 nm standard cell library as well, and find a decoding rate of 710 Mbps and 4.2 Gbps and area of 2527 slices and 0.36 mm2, respectively.

Algebraic Soft-Decision Decoder Architectures for Long Reed–Solomon Codes

Algebraic soft-decision (ASD) decoders of Reed-Solomon (RS) codes can achieve significant coding gain with polynomial complexity. Most prior work on ASD decoder architecture design is for relatively short RS codes. However, one major application of RS codes, magnetic recording, usually requires a code length of 4Kbits or longer. For long RS codes, the low-complexity Chase (LCC) ASD decoding needs to interpolate over a large number of test vectors, which leads to long latency. This brief proposes a unified backward-forward interpolation scheme and a corresponding architecture for the LCC decoding. The proposed architecture can achieve almost twice the speed with only 40% area overhead. Another contribution of this brief is that the hardware complexity analysis for different ASD decoders is provided for the first time. For a (458, 410) RS code over GF(210), the proposed LCC decoder can achieve much higher efficiency in terms of speed-over-area ratio than other ASD decoders with similar error-correcting performance.

Modified Low-Complexity Chase Soft-Decision Decoder of Reed–Solomon Codes

Reed---Solomon (RS) codes are widely used as error-correcting codes in digital communication and storage systems. Algebraic soft-decision decoding (ASD) of RS codes can achieve substantial coding gain with polynomial complexity. Among practical ASD algorithms, the low-complexity chase (LCC) algorithm that tests 2 ? vectors can achieve similar or higher coding gain with lower complexity. For applications such as magnetic recording, the performance of the LCC decoding is degraded by the inter-symbol interference from the channel. Improving the performance of the LCC decoding requires larger ?, which leads to higher complexity. In this paper, a modified LCC (MLCC) decoding is proposed by adding erasures to the test vectors. With the same ?, the proposed algorithm can achieve much better performance than the original LCC decoding. One major step of the LCC and MLCC decoding is the interpolation. To reduce the complexity of the interpolation, this paper also proposed a prioritized interpolation scheme to test a small proportion of the vectors at a time, starting with the ones with higher reliabilities. For a (458, 410) RS code, by testing 1/8 of the vectors at a time, the area requirement of the MLCC decoder with ??=?8 can be reduced to 57%, and the average decoding latency is reduced to 73%.

Backward Interpolation Architecture for Algebraic Soft-Decision Reed–Solomon Decoding

Recently developed algebraic soft-decision (ASD) decoding of Reed-Solomon (RS) codes have attracted much interest due to the fact that they can achieve significant coding gain with polynomial complexity. One major step of ASD decoding is the interpolation. Available interpolation algorithms can only add interpolation points or increase interpolation multiplicities. However, backward interpolation, which eliminates interpolation points or reduces interpolation multiplicities, is indispensable to enable the reusing of interpolation results in the following two scenarios: 1) interpolation needs to be carried out on multiple test vectors, which share common entries and 2) iterative ASD decoding where interpolation points have decreasing multiplicities. Examples for these cases are the low-complexity chase (LCC) decoding and bit-level generalized minimum distance (BGMD) decoding. With lower complexity, these algorithms can achieve similar or higher coding gain than other practical ASD algorithms. In this paper, we propose novel backward interpolation schemes and corresponding efficient implementation architectures for LCC and BGMD decoding through constructing equivalent GrOumlbner bases. The proposed architectures share computational units with forward interpolation architectures. Hence, the area overhead for incorporating the backward interpolation is very small. Substantial area saving or speedup can be achieved by using the backward interpolation. When the proposed architecture is applied to the LCC decoding of a (255, 239) RS code with eta = 3, the area is reduced to 39% of those required by prior architectures. In terms of speed/area ratio, the proposed architecture is 48% more efficient than the best available architecture. For the BGMD decoding of the same code, the proposed architecture can achieve around 20% higher efficiency.