Low Basal Plane Dislocation Research Articles

Electrical Characterization of High Voltage 4H-SiC pin Diodes Fabricated Using a Low Basal-Plane Dislocations Process

Forward current-voltage (I-V) characteristics and non-equilibrium carrier lifetime, τ were measured in 4H-SiC pin diodes (10-kV rated, 100 μm base width). The τ value was found to be 3.7 μs at room temperature by measurements of open circuit voltage decay. To the best of the authors' knowledge, the above lifetime value is the highest reported for 4H-SiC. The forward voltage drops were measured to be 3.44 V at current density of 100 A/cm2 and 5.45 V at 1000 A/cm2 showing a very deep modulation of the blocking base by injected carriers. Diodes operated well at elevated temperatures up to 400oC. No essential forward degradation was detected after 300- A×min current stress at 400oC.

Low Trap Concentration and Low Basal-Plane Dislocation Density in 4H-SiC Epilayers Grown at High Growth Rate

Fast homoepitaxial growth of 4H-SiC has been carried out on off-axis (0001) substrates by horizontal hot-wall CVD at 1600οC. High growth rate up to 24 μm/h has been achieved with mirror-like surface in the C/Si ratio range of 1.0-2.0. The Z1/2 and EH6/7 concentrations can be kept as low as 7 × 1011 cm-3 and 3 × 1011 cm-3, although an unknown trap (UT1) is observed with the concentration in the 1011 cm-3 range. The photoluminescence spectra are dominated by strong free exciton peaks, and the L1 peak is not observed. The basal-plane dislocation (BPD) density has decreased with increase in growth rate, and it can be reduced to 22 cm-2 when epilayers are grown on Chemical Mechanically Polished (CMP) substrates at a growth rate of 24 μm/h.

Fast homoepitaxial growth of 4H-SiC with low basal-plane dislocation density and low trap concentration by hot-wall chemical vapor deposition

Fast homoepitaxial growth of 4H-SiC has been carried out on 8° off-axis (0 0 0 1) Si substrates by horizontal hot-wall chemical vapor deposition (CVD) at 1650 °C. Growth at low pressure, by which gas-phase Si condensation can be minimized, has made it possible to obtain mirror-like surface at high growth rate up to 50 μm/h. Epilayers grown on chemical mechanically polished (CMP) substrates show much better surface morphology than those on as-received substrates. The basal-plane dislocation (BPD) density can be decreased by fast epitaxy on CMP substrates, and the minimum BPD density obtained in this study is 22 cm −2. The concentration of Z 1/2 and EH 6/7 centers is in the low 10 12 cm −3 range even at high growth rate of 50 μm/h. In photoluminescence (PL), free exciton peaks are remarkably dominant, and impurity-related peaks and L 1 peak are hardly observed.

Growth of Low Basal Plane Dislocation Density SiC Epitaxial Layers

A method was developed in our laboratory to grow low basal plane dislocation (BPD) density and BPD-free SiC epilayers. The key approach is to subject the SiC substrates to defect preferential etching, followed by conventional epitaxial growth. It was found that the creation of BPD etch pits on the substrates can greatly enhance the conversion of BPDs to threading edge dislocations (TEDs) during epitaxy, and thus low BPD density and BPD-free SiC epilayers are obtained. The reason why BPD etch pits can promote the above conversion is discussed. The SiC epilayer growth by this method is very promising in overcoming forward voltage drop degradation of SiC PiN diodes.

Techniques for Minimizing the Basal Plane Dislocation Density in SiC Epilayers to Reduce V<sub>f</sub> Drift in SiC Bipolar Power Devices

Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to <10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The first low BPD technique employs a selective etch of the substrate prior to epilayer growth to create a near on-axis surface where BPDs intersect the substrate surface. The second low BPD technique employs lithographic and dry etch patterning of the substrate prior to epilayer growth. Both processes impede the propagation of BPDs into epilayers by preferentially converting BPDs into threading edge dislocations (TEDs) during the initial stages of epilayer growth. With these techniques, we routinely achieve Vf stability yields of up to 90% in devices with active areas from 0.006 to 1 cm2, implying that the utility of the processes is not limited by device size.

Do You Really Expect To Grow Epilayers On That? A Rationale For Growing Epilayers On Roughened Surfaces

AbstractWe describe surface preparation and epilayer growth techniques that readily reduce the density of Vf drift inducing basal plane dislocations in epilayers to less than 10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The optimal process route requires etching the substrate surface prior to epilayer growth to enhance the natural conversion of basal plane dislocations into threading edge dislocations during epilayer growth. The surface of this relatively rough “conversion” epilayer is subsequently repolished prior to growing the device structure. We provide details on processing parameters and potential problems as well as describe devices produced using this low basal plane dislocation growth processes.

Degradation of hexagonal silicon-carbide-based bipolar devices

Only a few years ago, an account of degradation of silicon carbide high-voltage p-i-n diodes was presented at the European Conference on Silicon Carbide and Related Compounds (Kloster Banz, Germany, 2000). This report was followed by the intense effort of multiple groups utilizing varied approaches and subsequent progress in both fundamental understanding of this phenomenon and its elimination. The degradation of SiC p-i-n junctions is now well documented to be due to the expansion of Shockley-type stacking faults in the part of the devices reached by the electron-hole plasma. The faults can gradually cover most of the junction area, impeding current flow and, as a result, increasing the on-state resistance. While in most semiconductors stacking faults are electrically inactive, in hexagonal silicon carbide polytypes (4H- and 6H-SiC) they form quantum-well-like electron states observed in luminescence and confirmed by first-principles calculations. The stacking-fault expansion occurs via motion of 30° silicon-core partial dislocations. The Si–Si bond along the dislocation line induces a deep level in the SiC band gap. This state serves as both a radiative and a nonradiative recombination center and converts the electron-hole recombination energy into activation energy for the dislocation motion. Dislocation motion is typically caused by shear stress, but in the case of SiC diodes, the driving force appears to be intrinsic to the material or to the fault itself, i.e., the fault expansion appears to lower the energy of the system. Stable devices can be fabricated by eliminating stacking-fault nucleation sites. The dominant type of such preexisting defects is the segment of basal plane dislocations dissociated into partials. The density of such defects can be reduced to below 1cm−2 by conversion of all basal plane dislocations propagating from the substrate into threading ones in the epitaxial layer. Remarkable progress in fabrication of low basal plane dislocation density material offers hope of bipolar SiC devices being available commercially in the near future.

Basal plane dislocation-free epitaxy of silicon carbide

Molten KOH etching was implemented on SiC substrates before growing epilayers on them. It was found that the creation of basal plane dislocation (BPD) etch pits on the substrates can greatly enhance the conversion of BPDs to threading edge dislocations during epitaxy, and thus low BPD density and BPD-free SiC epilayers are obtained by this method. The reason why BPD etch pits can promote the earlier conversion is discussed. The SiC epilayer growth by this method is very promising in overcoming forward voltage drop degradation of SiC PiN diodes.