Lossy Matching Networks Research Articles

A Novel Over-Push Gain-Boosting Technique for Embedded Amplifier at Near-f max Frequencies

In this letter, a novel over-push method is proposed to improve the power gain of amplifiers with an embedding network and a lossy matching network (MN) at near- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm {max}}$ </tex-math></inline-formula> frequency. The gain-plane approach has been employed to study the change of the maximum available gain when adding the lossy MN to the embedded core. The proposed over-push method can effectively improve the power gain by compensating the effect of the lossy MN to the maximum available gain of an embedded core. To verify the proposed method, a three-stage amplifier has been implemented in a 65-nm CMOS process with a measured power gain of 17.1 dB at 134 GHz.

Highly Integrated PA-PIFA With a Wide Frequency Tuning Range

This letter presents a highly integrated power amplifier (PA) antenna with the capability of frequency tuning. A planar inverted-F antenna (PIFA) is used to directly match the PA transistor. This mitigates the lossy output matching network in the PA-integrated antenna (PAIA). In order to achieve a wide frequency tuning range, a combination of capacitors is loaded at the PIFA to control the antenna input impedances so that matching can be maintained with frequency tuning. The antenna analysis and design procedure of the tunable PAIA are detailed. For verification, a prototype is designed, fabricated, and measured. The experimental results show that the frequency tuning range of the proposed PAIA covers from 2 to 4 GHz. Over this frequency tuning range, the effective isotropic radiation power and power-added efficiency are higher than 40.5 dBm and 60% at the input power of 26.5 dBm, respectively.

Co-Design and Validation Approach for Beam-Steerable Phased Arrays of Active Antenna Elements With Integrated Power Amplifiers

An approach for designing a beam-steering active phased array of antenna elements with integrated power amplifiers (PAs) is presented. It is based on an amplifying active integrated unit cell (AiUC) concept, where the AiUC comprises a radiating slot element, a GaN high-electron-mobility transistor (HEMT), its input matching, and dc biasing/feeding circuitry. The HEMT is embedded in the antenna element, being directly impedance-matched to HEMT’s drain output, i.e., without using any intermediate and potentially lossy impedance matching network. The proposed co-design approach involves a full-wave analysis of the AiUC passive part (naturally including elements mutual coupling effects) along with the subsequent full-system harmonic balance simulations. Furthermore, we extend the standard definition of the scan element pattern (SEP) to the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">active</i> SEP (ASEP) that accounts for nonlinear effects of PAs on the AiUC performance. We show that the ASEP is, in general, power-dependent and has a different shape compared with the SEP. The proposed approach has been demonstrated for a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band AiUC design example. It was verified through an active waveguide simulator, which is equivalent to the 23.7° H-plane beam-steering case. Measurements are in good agreement with simulations, revealing AiUC 47% peak drain efficiency and 33 dBm maximum radiated power. The predicted scan range is ±60° and ±37° in the E- and H-planes, respectively.

Optimize the Efficiency of Lossy Matching Network: A Top-Down Splitting Algorithm Based on Generalized Quality-Based Equation

For the lossy matching network, the efficiency of transferring the power is one of the most important factors. In this brief, a novel generalized quality-based equation has been derived which can accurately calculate the efficiency. This generalized equation covers all the situations that the source and load impedance are both complex and consider both the loss of inductor and capacitor. Meanwhile, the SPICE simulations have been carried out to validate the accuracy of the proposed equation. Based on this generalized equation, a top-down splitting algorithm is proposed to further optimize the efficiency of multi-stage matching network. The proposed method shows better improvement of efficiency than prior works.

Novel Battery-Less Sustainable Energy Harvester Scheme for On-board Electronic Units

With the rapid development in smart vehicles, the on-board unit is established for communication between the vehicle and toll collection booth for toll collection. However, providing a continuous power supply to such units has been a challenge. While features like compactness, low cost and simplicity are to be maintained, the accuracy and performance of the device are to be maintained intact. This paper proposes a battery-less energy harvester scheme as a solution to this power issue. Maximum energy transmission Several researches are conducted on obtaining maximum energy transmission through performance optimization in this domain. This paper provides maximum performance while minimizing the energy harvester transponder dimensions. The energy transmitted to the transponder is maximized considering the optimal source impedance. This provides power to the battery-less structure. The radio frequency to DC rectifier is provided with an optimal source impedance with the help of a small patch antenna. Utilization of a lossy matching network can be avoided through this technique. Inter-stage matching network is used for comparison of the function. The energy efficiency using the proposed scheme is increased by a factor of 10% when compared to the existing schemes.

Design of a Compact and Highly Efficient Energy Harvester System Suitable for Battery-Less Low Cost On-Board Unit Applications

This study addresses the general problem regarding the power supply in specific on-board unit (OBUs) solutions. In detail, this paper refers to a subset of the so-called electronic toll collection (ETC) applications such as assets control and vehicle identification, where simplicity, low costs, and maximum compactness represent the most important features. In this context, the next generation of OBUs, developed specifically with reference to such applications, will involve energy harvester-based battery-less techniques. Previous studies have mainly concentrated on performance optimization by achieving maximum energy transmission to the OBUs. This study discusses a technique suitable for both maximizing performance and minimizing the dimensions of transponder energy harvesters suitable for assets control and vehicle identification operating at 5.8 GHz. The technique assumes that an optimal source impedance exists that maximizes the energy transfer to the transponder, thus enabling its power supply in a battery-less configuration. We discuss a solution based on a compact patch antenna designed to exhibit this optimal source impedance to the RF-to-DC rectifier. This approach avoids the use of a lossy matching network. For the sake of comparison, the same function is compared with an equivalent development, which includes the interstage matching network between the antenna and the RF-to-DC rectifier. We introduce experimental results demonstrating that the ultracompact energy harvester optimized at −5 dBm of impinging power is capable of increasing both the charge current and energy efficiency from 340 to 450 μA and from 37% to 47%, respectively.

Systematic Co-Design of Matching Networks and Rectifiers for CMOS Radio Frequency Energy Harvesters

This paper presents a systematic methodology for the co-design of matching network and rectifier of radio frequency (RF) harvesters that results in maximum power conversion efficiency (PCE) for a given available power. This method is based on our newly developed rectifier model capable of calculating the CMOS Dickson’s rectifier’s input/output voltages at a given input power developed for low/high input power regimes. The proposed model allows for the co-design of the matching network and the rectifier in a fraction of time that takes for the design of the RF energy harvester using previously developed models relying on the knowledge of rectifier’s input voltage levels where a computationally extensive iterative design procedure must be performed because of the interdependence of the rectifier’s input voltage, the input power, and the matching network’s and rectifier’s parameters. The proposed methodology is capable of accurately predicting matching network components’ sizes for both the lossless and lossy matching networks for a maximum power transfer. Utilizing the proposed methodology, the designers can produce efficiency contour plots for a given input power for finding the optimum matching network and rectifier’s parameters for maximum PCE. The model, simulation, and measurement results for different parameters and input power levels in a 130-nm process are in good agreement.

Unimodal criteria of tunable matching network

A set of unimodal criteria for a tunable matching network is presented to make the objective function of the matching network to be unimodal, which leads to the finding of the global optimum point. Furthermore, the proposed unimodal criteria are extended to the lossy matching network.

On the Minimum Number of States for Switchable Matching Networks

The impedance of an antenna changes heavily with changing EM environments, while RF power amplifiers (PAs) are optimized for driving a well-defined load impedance. As a solution, switchable matching networks are used in automatic antenna tuners to match the antenna impedance to (about) the desired PA load impedance. This paper presents a theoretical treaty of the minimum number of required states for switchable matching networks to achieve sufficient matching from a certain load VSWR to a sufficiently low input VSWR. First for an arbitrary passive lossless switchable matching network, the mathematical minimum required number of states as a function of the required input VSWR and of the required load VSWR is derived. Several variants are analyzed and benchmarked: single-stage one-ring configuration, single-stage two-ring configuration, two-stage one-ring configuration and three-stage one-ring configuration showing that single-ring configurations are optimum. An extension towards the required number of states for lossy matching networks is also provided.

Design of a 0.7~2.6GHz Wideband Power Amplifier in 0.18-μm CMOS Process

A power amplifier (PA) for multi-mode multi-standard transceiver which is implemented in a TSMC 0.18μm process is presented. The proposed PA uses matching compensation, lossy matching network and negative feedback technique to improve bandwidth. To achieve the linearity performance, the two-stage PA operates in Class-A regime. Simulation results show that the power amplifier achieves maximum output power of more than 24dBm in 0.7~2.6GHz. The output P1dB of the PA is larger than 22dBm. The simulated power gain is more than 27dB. The S11 is less than-10dB and the S22 is under-5dB.

Design of a 0.7~3.8GHz Wideband Power Amplifier in 0.18-μm CMOS Process

The design of a 0.7~3.8GHz CMOS power amplifier (PA) for multi-band applications in TSMC 0.18-μm CMOS technology is presented. The PA proposed in this paper uses lossy matching network and low Q multistage impedance matching network to improve wideband. To achieve maximum linearity, this PA operates in the Class-A regime. The post-layout simulation results show that the power amplifier achieves 21.9dB of power gain, 22.3dBm of 1dB compression power output at 2GHz. The power adder efficiency (PAE) at gain compression point is 17.8% at 2GHz.

A unique MMIC broadband power amplifier approach

A broadband monolithic microwave integrated circuit (MMIC) power amplifier design approach is described using lossy matching networks in the form of a bridged-T all-pass network. This approach offers the advantage of exceptional gain flatness, good input VSWR, high efficiency, and small size. A two-stage amplifier is described that delivers power greater than 1 W across the 2 to 6-GHz range with a linear gain of 20 dB, an input VSWR better than 1.7:1, and a power-added efficiency of 30% to 37% with a chip area less than 4.4 mm/sup 2/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Lumped lossy circuit synthesis and its application in broad-band FET amplifier design in MMICs

A lumped lossy circuit is synthesized by means of the transformation introduced by L. Zhu et al. (ibid., vol.36, no.12, p.1614-20, Dec. 1988). The circuit contains two different kinds of lossy branches that include arbitrary nonuniform reactive resistors as well as lossy inductors and capacitors. This approach can be used to synthesize a lumped lossy matching network more flexibly than previous techniques. An example is presented to show the application of the synthesis of the lumped lossy matching networks for compensating the device gain roll-off with frequency in the design of a broadband monolithic microwave integrated FET amplifier. The advantages of the technique are seen by comparison with the amplifier designed by Zhu et al. >

Real frequency technique applied to the synthesis of lumped broad-band matching networks with arbitrary nonuniform losses for MMICs

A computer-aided synthesis technique for lumped matching networks with arbitrary nonuniform losses is presented. It is especially applicable to the design of broadband amplifiers in MMIC form. A useful theorem and two corollaries for the transformation between lossy and lossless networks are developed, so that the design of the lossy matching networks is considerably simplified and can yield complex models of the lumped elements with arbitrary nonuniform losses. An example showing the application of the method to monolithic broadband amplifier design is given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Computer-aided design of microwave amplifiers by the random addition of new components

A new technique for the optimisation of microwave transistor amplifiers has been developed, whereby the computer program removes components or adds new components and nodes to the circuit, in a systematic but apparently random manner, in order to approach specified performance targets. Although the assessment of a large number of possible alternative circuits consumes a large amount of computer time, two examples show that acceptable circuits are produced with very little operator interaction. The program optimises for gain, noise figure, input and output VSWR and stability. It is suitable for integrated circuit design. Examples are given of a single-stage amplifier with feedback and a two-stage amplifier with lossy matching networks but without feedback operating over the frequency band 8–12 GHz.

Tapered-magnitude lossy bandpass networks†

Bandpass lossy matching networks (both lumped and distributed) having sloped gain versus frequency characteristics are presented. These networks have approximately 6dB/octave slope in gain against ...

Computer-Aided Synthesis of Lumped Lossy Matching Networks for Monolithic Microwave Integrated Circuits ( MMIC's)

A systematic computer-aided synthesis (CAS) technique of lumped Iossy matching networks is presented in this paper. This exact synthesis procedure can take arbitrary finite quality factor Q for each lumped element in the matching network and therefore facilitate the circuit design for monolithic microwave integrated circuits (MMIC's) where the loss of the passive elements is too large to be neglected. The gain-band-width limitations of some useful lumped Iossy matching networks are discussed in detail and are summarized in a set of gain-bandwidth constraint plots. An interactive computer program LUMSYN is developed to solve this lumped Iossy synthesis problem. LUMSYN is a general-purpose CAS program which can be used by microwave circuit designers with limited background in network synthesis to carry out Iow-noise and power amplifier designs in MMIC's. Finally, a design example of broad-band monolithic microwave low-noise amplifier using a state-of-the-art low-noise submicron gate-length GaAs MESFET is presented to illustrate the computer-aided synthesis of MMIC amplifiers.