Semiconductor Losses Research Articles

A Single Stage Doubly Grounded Transformerless Inverter Topology With Buck-Boost Voltage Capability for Grid Connected PV Systems

A novel single-stage doubly grounded transformerless inverter configuration which can buck-boost the output voltage is proposed in this paper. In this transformerless inverter configuration grid neutral is directly connected to PV panel negative rail which suppresses/eliminates the PV leakage currents. In addition, the tracking of maximum power point is possible for wide variation of weather conditions due to buck-boost voltage capability of inverter. Moreover, the proposed inverter topology has symmetrical operation in both half cycles hence injects negligible DC offset current in to the grid. Here the symmetrical operation of inverter is achieved due to one inductor is used for both half cycles of the grid. The proposed topology is realized using five switches, two of which work at 50 Hz and remaining three switches at high frequency which reduces overall semiconductor losses. Further, the proposed inverter topology is controlled through a newly developed modulation technique and possible working modes are analyzed and described thoroughly. For performance validation, the experimental analysis of grid connected proposed inverter is performed on a 1 kVA system and results show that proposed inverter feeds power in to the grid with lesser THD while achieving greater efficiency.

An Active-Neutral-Point-Clamped Switched-Capacitor Multilevel Inverter With Quasi-Resonant Capacitor Charging

Switched-capacitor (SC) multilevel inverters (MLIs) offer various advantages over conventional series MLIs owing to the operation from a single dc source, self-balanced capacitor voltages, and inherent voltage gain. However, these advantages come at the cost of high current stress on the capacitors, associated semiconductors, and the dc source. This inrush current has limited the practical application of SC-MLIs to a fractional kilowatt rating. This article proposes a practical solution by introducing a unity gain nine-level active-neutral-point-clamped SC-MLI with an alleviated capacitor charging current. Switching loss in the SC circuit semiconductors is reduced by using a modified switching sequence that allows the charging current to flow with a minimum interruption till it is turned off at zero-current crossing. The structure also integrates protection against the detrimental effects of voltage transients across the charging inductor. The inverter exhibits a maximum efficiency of 98.03% at 583.91 W output power. Compared with similar SC-MLIs with hard-charging, the proposed inverter significantly reduces the losses and improves efficiency. Experimental results from a 2 kVA laboratory prototype validate the theoretical analysis and show the capacitor voltages stable under varying load impedance and modulation index.

Sliding-Mode Control for Interleaved Operation of Parallel-Connected Three-Phase Active Front-Ends

A converter system is considered that consists of parallel-connected two-level voltage source converters that share the same ac and dc terminals. A controller design is proposed that, in a first stage, controls the grid currents using hysteresis controllers. To this end, augmented grid currents are introduced, which feature decoupling between the phases. As a consequence, a switching action in one phase does not affect the derivatives of these currents in the other phases. In a second stage, the converter currents are controlled using hysteresis controllers such that a desired current distribution among the parallel converters may be ensured. This implicitly sets the circulating currents. The proposed approach is verified by measurements on an industrial megawatt-scale testbench with ten parallel converters. The results are compared with a benchmark approach, with the proposed approach showing lower semiconductor losses and grid current harmonic distortion.

Analytical Estimation of Power Losses in a Dual Active Bridge Converter Controlled with a Single-Phase Shift Switching Scheme

Micro-grid solutions around the world rely on the operation of DC/DC power conversion systems. The most commonly used solution for these topologies is the use of a dual active bridge (DAB) converter. Increasing the efficiency and reliability of this system contributes to the improvement in the stability of the entire microgrid. This paper discussed an analytical method of energy efficiency and power loss estimation in a single phase dual active bridge (DAB) converter controlled with a single-phase shift (SPS) modulation scheme for microgrid system stability. The presented approach uses conduction and commutation losses of semiconductors and high frequency transformer. All parameters required for the calculation may be obtained from the manufacturers’ datasheets or can be based on a simple measurement. The approach was validated by the comparison of the estimated energy efficiency characteristics with the measured ones for a prototype of a 5 kW single phase DAB converter equipped with silicon carbide metal-oxide semiconductor field-effect transistors (SiC MOSFET).

Semiconductor Losses Calculation of a Quasi-Z-Source Inverter with Dead-Time

A quasi-Z-source inverter (qZSI) belongs to the group of single-stage boost inverters. The input dc voltage is boosted by utilizing an impedance network and so called shoot-through (ST) states. In pulse-width modulations utilized for the qZSI, the dead-time is commonly omitted. However, unintended ST states inevitably occur as a result of this action, due to the non-ideality of the switching devices, causing the unintended voltage boost of the inverter and an increase in the switching losses. Hence, the implementation of the dead-time is desirable with regard to both the controllability and efficiency of the qZSI. This paper deals with the calculation of semiconductor losses of the three- phase qZSI with implemented dead time. An algorithm available in the literature was utilized for that purpose. The algorithm in question was originally proposed and applied for the qZSI with omitted dead-time, where the occurrence of unintended, undetected ST states combined with the errors in the switching energy characteristics of the insulated gate bipolar transistor (IGBT) provided by a manufacturer led to errors in the obtained results. However, these errors were unjustifiably ascribed solely to the errors in the switching energy characteristics of the IGBT. In this paper, a new, corrected multiplication factor is experimentally determined and applied to the manufacturer-provided IGBT switching energies. The newly-determined multiplication factor is expectedly lower than the one obtained in the case of omitted dead time. The loss- calculation algorithm with the new multiplication factor was experimentally evaluated for different values of the qZSI input voltage, the duty cycle, and the switching frequency.

Half-Controlled Converters Connecting Open-End Doubly Fed Induction Generator to a DC-Microgrid

This article presents a novel system to connect a three-phase doubly fed induction generator (DFIG) to a dc-microgrid. The proposed topology is based on two three-phase half-controlled converters connected in series with the generator stator windings, in an open-end winding configuration. The converters operating principles, pulsewidth modulation, power and air-gap flux controls, and zero-sequence current minimization strategies are discussed. The proposed system is compared with conventional systems in terms of current harmonic distortions, torque ripple, and semiconductor losses. Simulations and experiments were also performed, showing steady-state and transient results for the DFIG generating 500 W. Finally, it was verified that the proposed system can operate with lower power losses and maintain low-distorted voltages and currents over the DFIG stator windings.

Multilevel inverter with active clamping diodes for energy efficiency improvement

Multilevel inverters can replace commonly used two-level inverters for three-phase electrical drives. In this lowvoltage range new wide-bandgap power switches (SiC MOSFET, GaN FET) are available. In the four-, five- and sevenlevel inverters, the majority of the power losses are caused by the threshold voltage of the clamping diodes. The new idea is the replacement of the clamping diodes by active switches, since they only have low on-resistance in the forward direction. In this case freewheeling paths of the clamping diodes would have to be actively switched. However, the control signals for the clamping switches can be generated by logic operations from the control signals for the main switches. The use of active clamping switches has significant potential to reduce semiconductor losses, but requires the development of wide-bandgap power semiconductors with reverse blocking capability. At nominal motor operation point of the 5.5 kW induction motor a loss reduction of 56 % between active clamping switches and clamping diodes is possible. With a higher number of inverter levels, the size of the motor filter can be reduced by about 70 % and also the losses can be reduced by 73 %.

A Generalized Interleaved Approach Feasible to Static Synchronous Compensator Applications

This work investigates a generalized cascaded full-bridge (GCF) concept, which uses a full-bridge converter as a basic submodule, combined with the interleaving and cascading techniques. When compared with the traditional cascaded full-bridge (CFB) converter, the GCF topologies present the advantages of reduced current and voltage stresses on the semiconductors, and flexible design. Thereby, the resulting structures become an alternative solution for high-power applications involving high current and high voltage levels. The generalized analysis involving design guidelines for the synthesis of each topology, the system model, and possible modulation strategies are described in detail. A comparative study with the CFB-based topologies shows that the introduced structures are capable of achieving improved performance in terms of reduced losses in the power semiconductors and lower device count. A small-scale laboratory prototype of a static synchronous compensator rated at 2.2 kVA/311 V is implemented to validate the design assumptions considering the steady-state and transient performances.

Integrated Inductor Design for a Highly Compact Embedded Battery Charger

An integrated inductor for a highly compact embedded battery charger is designed in this article. A zero-voltage switching (ZVS) buck converter is the selected topology to achieve high power density. ZVS is achieved by sizing the inductor based on energy balance and introducing the <inline-formula><tex-math notation="LaTeX">$k$</tex-math></inline-formula> factor. A novel four-leg magnetic core structure is proposed as the integrated inductor. By introducing a modified parameter <inline-formula><tex-math notation="LaTeX">$\alpha _{\mathrm{eff}}$</tex-math></inline-formula> to the improved generalized Steinmetz equation method, the optimal switching frequency for core losses can be found. From the constructed inductor model and semiconductor loss calculation, the design tradeoff and optimization is analyzed. The optimal <inline-formula><tex-math notation="LaTeX">$f_{\mathrm{sw}}$</tex-math></inline-formula> is found to be around 2 MHz, which is when the performance factor for the core material peaks. As a proof of concept, a highly compact prototype, featuring stacked printed circuit board solution, with 16.2 &#x00D7; 19.2 &#x00D7; 6 mm<inline-formula><tex-math notation="LaTeX">$^{3}$</tex-math></inline-formula> dimension is built. The input voltage ranges from 6 to 12 V, and the converter is capable of delivering up to 10 A at the 4-Voutput. Converter peak efficiency of 96&#x0025; is achieved, and the inductor design has a power density of 113.6 W/cm<inline-formula><tex-math notation="LaTeX">$^{3}$</tex-math></inline-formula>. This shows improvement over several state-of-the-art designs. This article is accompanied by a video demonstrating the flux distribution in the magnetic core over the switching period.

Design of Cascaded H-Bridge Multilevel Inverter Topology for Integrated Portable Power Pack Application

This paper presents the necessity of portable power supplies that can be carried and cater to all the users' demands. Since the energy storage of the portable power pack are coming from DC supply, it needs an inverter to convert the DC voltage into AC voltage. Most of the low-priced inverters in the market have a simple build and are inefficient, resulting in high THD that can cause the electrical appliance not to work properly. This project was focused on the most suitable inverter type where the cascaded H-bridge multilevel inverter with PWM switching technique was proposed. This type of inverter will produce a better THD and a higher output voltage level when the inverter level is increased. This theory was proved where 3-level, 5-level and 7-level of Cascaded H-Bridge Multilevel Inverter has a 52.05 %, 29.98 % and 21.94 % of voltage THD. These results prove that by increasing the output voltage level can reduce the voltage THD. For the hardware implementation, a 5-Level Cascaded H-Bridge Multilevel Inverter with PWM switching technique is chosen because it has a lower voltage THD compared to 3-Level Cascaded H-Bridge Multilevel Inverter and at the same time use less of semiconductor devices compared to 7-Level Cascaded H-Bridge Multilevel Inverter and has fewer semiconductor losses compared to the inverter with SPWM switching technique. The voltage THD of circuit models hardware when reaches 24 V_pk is 28.3 % which is slightly better to simulation result, 29.98 %. This inverter was then connected with a step-up transformer with a ratio of 1:10 to reach standard electrical voltage supply in Malaysia of 230 V_rms with a voltage THD of 28.4 % without load and 30 % with load. This proves that the circuit model can work properly as the 5-Level Cascaded H-Bridge Inverter simulation and hardware results show a good agreement.

Study of a novel soft‐switched Vienna rectifier using simple active technique

SummaryIn recent years, efficient power transfer is getting increasing attention in high‐power conversion systems such as fast battery charger systems primarily necessitate an energy efficient, compact, and reliable power electronic converter scheme. This has stirred vigorous research in high‐power converter‐based power electronic systems which are feasible in actual practice and perform efficiently. In view of this fact, a novel soft‐switched T‐type boost rectifier Vienna topology is proposed, which can be considered as a potential candidate in high‐power conversion systems. The proposed converter scheme operates at high‐switching frequency with soft‐switching conditions by employing a simple active snubber circuit, which results in high‐efficiency and high‐power density with low cost. The low components count, simple power and control circuitry, comparable stresses, and performance are the distinctive features of the proposed converter scheme. Furthermore, the proposed topology achieves high‐switching operation while reducing reverse recovery rectifier diode losses and semiconductor losses. The proposed converter scheme's construction, operating principle, and practical implementation are carried out using a low‐scale laboratory prototype. In order to evaluate, a comparison with existing soft‐switched rectifier topologies is performed in terms of components count. In addition, a MATLAB/Simulink designed subsystem is used to assess the semiconductor devices switching power losses in comparison to its hard‐switched counterpart.

A Critical Review of Modular Multilevel Converter Configurations and Submodule Topologies from DC Fault Blocking and Ride-Through Capabilities Viewpoints for HVDC Applications

Modular multilevel converters (MMCs) based on half-bridge submodules (HBSMs) are unable to prevent the AC side contribution to DC side fault currents, thus necessitating circuit breakers (CBs) for protection. A solution to this problem is using submodules (SMs) that are capable of blocking the flow of current from the AC grid to feed the DC side fault. The full-bridge submodule (FBSM) is one type of fault blocking SM where the presence of two extra switches ensures that in the event of a DC fault, the reverse voltage from the FBSM capacitor is placed in the path of the AC side current feeding the DC side fault through the antiparallel diodes. However, the additional semiconductor switches in the FBSMs increase the converter cost, complexity, and losses. Several SM configurations have been proposed in recent years that provide DC fault blocking capability with lower losses and device counts than those of FBSMs. Besides, many of the proposed hybrid converter configurations that combine different topologies to optimize converter performance are also capable of providing DC fault blocking. Furthermore, certain SM topologies are capable of riding through DC faults by remaining deblocked and operating in static synchronous compensator (STATCOM) mode to provide reactive power support to the AC grid. In this paper, noteworthy SM and MMC configurations capable of DC fault blocking and ride-through are reviewed and compared in terms of component requirements, semiconductor losses, and DC fault handing capability. The review also includes a discussion on control strategies for MMC arm/leg energy balancing during STATCOM operation.

Simulation model of unity power factor uninterruptible power supply topology using single-phase matrix converter

This paper presents a computer simulation model of the unity power factor uninterruptible power supply (UPS) topology using single-phase matrix converter (SPMC) that focuses on the switching integration for both rectifier and inverter operations. The proposed integrated switches capable of controlling the SPMC to operate as a rectifier operation to charge the DC battery during the normal operation and to switch the SPMC to operate as an inverter during power outage conditions continuously and instantaneously using a single power converter circuit. The use of a single power converter circuit can solve the typical UPS system that requires at least two separate power converter circuits, thus contributing to the higher power semiconductor losses and complicated control circuits. With the proposed circuit topology, it can improve the power density of the power electronics converter system resulting in low power losses. The active power filter (APF) function has been used to improve the supply current waveform to follow the shape of the sinusoidal reference current to be in phase with the supply voltage waveform, thus reduce the total harmonic distortion (THD) level and improve the power factor. To verify the proposed operation, the selected simulation results are presented, and the proposed work has been done through the MATLAB/Simulink.

Single-Phase Transformerless Five-Leg AC–DC–AC Multilevel Converter for Voltage Step-Up Applications

This article proposes a single-phase transformerless ac&#x2013;dc&#x2013;ac multilevel converter composed of a three-leg module series-connected to an H-bridge at the load side to achieve a higher and multilevel voltage at this side. The proposed structure is appropriated for applications with the same input and output frequencies, such as uninterrupted power supply and unified power quality conditioner, and for electric power conversion systems in which the output voltage required is higher than the input voltage (voltage step-up applications). System model, converter power analysis, dc-link voltage specifications, and a space vector PWM strategy are developed. The proposed system control ensures fixed load voltage with constant amplitude and frequency, maximizes the grid power factor, and regulates the dc-link voltages. Compared with conventional solutions, the proposed configuration has presented lower dc-link voltage ratings and lower mean switching frequency on the semiconductor devices, lower harmonic contents, and lower switching losses. The comparative analysis shows that the mean weighted total harmonic distortion (WTHD) of the generated voltages of the proposed topology are reduced about 27&#x0025; and 16&#x0025;, respectively, compared to the topologies 4L and 3L, and 4L-LLC; and the total semiconductor losses are reduced about 26&#x0025;, 10&#x0025;, and 49&#x0025;, respectively, compared to 4L, 3L, and 4L-LLC, when all topologies operate with the same mean WTHD. Operating with the same switching frequency, the proposed converter presented total semiconductor losses similar to conventional 3L, and about 17&#x0025; and 45&#x0025; lower than 4L and 4L-LLC. Experimental results demonstrate the operation of the proposed converter under load transients and grid voltage variations.

Single-Phase to Single-Phase Three-Wire Power Converters Based on Two-Level and Three-Level Legs

This article presents two single-phase to single-phase three-wire converters based on two-level and three-level neutral-point-clamped legs. The converters present a shared-leg between the grid and load. A space-vector pulsewidth modulation technique considering the harmonic distortion and the semiconductor losses is presented, besides the dc-link voltage-balance technique to balance the neutral-point voltage. The converters can supply the loads with constant amplitude and frequency under grid voltage disturbances. These characteristics make the proposed converters suitable for applications as uninterrupted power supply. The proposed converters are compared to a conventional two-level converter from simulated results for evaluating the semiconductor losses and harmonic distortion. The experimental results are provided to illustrate and validate the operation of the proposed systems.

A design for switched capacitor and single‐switch DC–DC boost converter by a small signal‐based PI controller

AbstractIn this study, a switched capacitor (SC)‐based single‐switch DC–DC boost converter structure operating under the high voltage gain and the low duty ratio is proposed using the PI control technique. High current and voltage stresses across the power switches and power diodes can be reduced by using the projected SC block. In addition, the proposed converter can achieve high voltage gain through shorter duty cycles, which directly reduces the voltage stress and dynamic losses in the power semiconductors. On the other hand, because the proposed converter includes a single power switch under different output powers and different loads, the control process is simpler than multiswitch structures. With the proposed converter, an output voltage of 10 times greater rather than the input voltage is obtained at 0.57 of the duty cycle. In this study, the fundamental functions of the proposed converter and the controller design steps are analyzed mathematically and tested in MATLAB/SIMULINK environment. As a result of the analysis, it was determined that the proposed topology works with a high performance at high frequency and variable load ranges. To validate the proposed converter and theoretical calculations, a 200‐W prototype was established under a continuous conduction mode (CCM) working state, with 48‐VDC input voltage and 400‐VDC output voltage. Finally, the simulation results were tested and verified through the experimental results.

Comparative Assessment of Multi-Port MMCs for High-Power Applications

Multi-port converters can interconnect different dc and ac systems while reducing semiconductor requirements and losses by eliminating redundant power conversion stages. Modular multilevel converter (MMC)-based multiport systems are well suited for application in mixed ac-dc grids containing high-voltage dc (HVDC) and medium-voltage dc (MVDC) systems. This paper conducts a detailed comparative assessment of multi-port dc-dc-ac MMCs for high power applications. Four representative topologies are chosen for study due to their contrasting internal power processing characteristics. Three different network scenarios are investigated that include HVDC and MVDC applications, covering several different power flow cases. The multi-port MMCs are compared in terms of losses, semiconductor effort, internal energy storage and magnetics requirements. The results are extensively discussed and general conclusions are summarized.

Spectral Steady-State Analysis of Inverters With Temperature-Dependent Losses Using Harmonic Balance

Accurate calculation of semiconductor losses and temperature is the foundation of any design methodology for a power electronic converter. Computation accuracy and speed play a vital role if a large set of parameters needs to be considered. Averaged loss models often neglect the temperature dependence of transistors, leading to fast, but inaccurate results. In contrast, iterative methods and simulation tools, which can include temperature dependence, take significantly longer to compute, but yield more precise results. This paper presents a best of both worlds approach, by using the harmonic balance method to obtain the steady-state solution for any inverter topology including temperature dependent conduction and switching losses. The proposed method solves for the discrete Fourier series of the device temperature, by expressing the temperature dependence and operating parameters in the frequency domain. The set of equations for each coefficient is solved by a single matrix inversion, resulting in very fast computation for steady-state temperature cycles. The steady-state operation of over one thousand possible inverter designs is calculated within less than one minute, matching iterative simulation in device temperature, conduction and switching losses, at a fraction of the computation time. In addition, the method shows good agreement with temperature measurements of a three-phase silicon-carbide inverter.

New FOM-Based Performance Evaluation of 600/650 V SiC and GaN Semiconductors for Next-Generation EV Drives

The drive inverter represents a central component of an electric vehicle (EV) drive train, being responsible for the DC/AC power conversion between the battery and the electrical machine. In this context, novel converter topologies adopting modern 600/650V wide bandgap (WBG) semiconductor devices will play a crucial role in improving the performance of next-generation drive inverters. In fact, WBG devices theoretically allow to achieve both higher inverter power density and higher conversion efficiency with respect to conventional silicon (Si) IGBT based solutions. Even though silicon carbide (SiC) devices are already well established in the automotive industry, high-voltage gallium nitride (GaN) devices are rapidly entering the market, promising higher theoretical performance but featuring a lower degree of maturity. As a consequence, it is currently not clear which semiconductor technology is most suited for future EV drive inverters. Therefore, this paper aims to address this gap providing a comparative performance evaluation of state-of-the-art SiC and GaN 600/650V active switches. In particular, a novel figure-of-merit (FOM) representing the minimum theoretical semiconductor losses under hard-switching operation is introduced. Remarkably, this FOM enables a fair and accurate performance comparison among semiconductor devices, allowing to clearly determine the best performing technology for a given set of application-specific conditions. The results of the comparative assessment show that currently available SiC and GaN active switch technologies can outperform each other depending on the semiconductor operating temperature and the converter switching frequency.

A Novel Fundamental Frequency Switching Operation for Conventional VSI to Enable Single-Stage High-Gain Boost Inversion with ANN Tuned QWS Controller

Single-stage high-gain inverters have recently gained much research focus as interfaces for inherent low voltage DC sources such as fuel cells, storage batteries, and solar panels. Many impedance-assisted inverters with different input stage configurations have been presented. To decrease passive component sizes, these inverters operate at high-frequency switching. The high-frequency switching optimizes the passive component sizes but introduces many challenges in the form of high-frequency inductor design, control complexity, high-frequency gate driver requirements, high semiconductor losses, and electromagnetic interferences. This article proposes a novel fundamental frequency switching operation for the conventional voltage source inverters (VSI) to operate as a single-stage high-gain inverter. As the novel operational strategy changes the behavior of conventional VSI from buck inverter to a boost inverter, it is hereafter termed as a novel inverter. By virtue of the operation strategy, switches withstand peak inverse voltage (PIV) equal to DC link voltage, unlike other impedance assisted boost inverters where PIV across switches is the amplified DC voltage. The proposed inverter can invert low-level DC voltage to high voltage AC with low total harmonic distortion (THD) in a single stage without the help of any external filter. A novel quarter-wave symmetric phase-shift controller is proposed for variable voltage and frequency control of proposed inverters tuned by a back-propagation thin-plate-spline neural network (BPTPSNN). Mathematical analysis with experimental validation is presented. Experimentation is carried out on a prototype of 2 kW for single-phase resistive load, induction motor, and non-linear loads.