Loosely-coupled Parallel Processor Research Articles

Modeling and simulation of mixed-signal electronic designs - Enabling analog and discrete subsystems to be represented uniformly within a single framework

This article has presented for the first time a scientific and mathematically sound principle that enables both analog and discrete subsystems to be represented uniformly within a single framework, thereby facilitating their simultaneous and uniform simulation within the same simulator. While the combination of the laboratory prototype analog subsystem simulator, DiamSim, and available discrete-event simulators such as VHDL constitute necessary and sufficient proof of the principle, the article outlines how a unified language and execution environment, nVHDL, may be realized for the future. In the coming age of networked computational systems (NCS), future complex systems will include analog hardware, synchronous and asynchronous discrete hardware, software, and inherently asynchronous networks that will interconnect both stationary and mobile entities, all governed by asynchronous control and coordination algorithms (Ghosh,2006). Paul (2006) believes that the current object-oriented programming is being quickly obsoleted by the increasing demands of net-centric warfare and that a dynamic, service-oriented architecture is critically needed to address key future needs of the US DoD. Logic dictates that nVHDL will likely play a key role in the development of a whole new approach, networked computational systems design language and execution environment (NCSDL). that will consist of a language in which complex systems may be described accurately and an execution environment that will permit the realistic execution of the executable description on a testbed to assess the system correctness, reliability, safety, security, and other performance parameters. Furthermore, to obtain results quickly for large systems and use them in iterating system designs, the testbed must consist of a network of workstations configured as a loosely-coupled parallel processor

A modeling and simulation methodology for analyzing ATM network vulnerabilities

The design of complex asynchronous distributed systems including ATM networks is in itself quite challenging and designers rarely expend either the time or energy to consider how unexpected changes in the operating environment may affect the reliability of the system, let alone take into consideration imaginative ways in which a clever perpetrator may maliciously cause the system to fail, often catastrophically. While the occurrence and impact of attacks launched against telephone networks, store-and-forward networks such as the Internet, and the power grid, are widely reported in the news media, a systematic analysis of these attacks in the scientific literature is lacking. This paper is the first to propose the use of modeling and asynchronous distributed simulation as a systematic methodology to uncover vulnerabilities in complex ATM networks. The approach is demonstrated in two steps. In step 1, a few complex attacks are identified, which while based on the principles of ATM networking, are representative of those that would be construed by intelligent enemy agents. An attack is viewed as a perturbation of an operationally correct ATM network and may be classified under two broad categories. The first attack type focuses on failing specific, standard functions in ATM networks while the second category of attacks refers to the prescription of a malicious intent or objective. Under step 2, the attacks are modeled utilizing a representative ATM network and analyzed through a simulation utilizing an asynchronous, distributed, and accurate ATM simulator, that executes on a network of Pentium workstations under Linux, configured as a loosely-coupled parallel processor. Thus, the environment underlying the evaluation of the vulnerabilities reflect reality, implying, in turn, realistic results. In addition to revealing the weaknesses, the findings of this methodology may serve as a guide to either redesigning the ATM network and eliminating the vulnerabilities or synthesizing a sentinel that conceptually surrounds and protects from network from attacks. While the methodology is generalizable to ATM-like MPLS network and future network designs, it is beyond the scope of this paper.

A Novel, User-Level, Security-On-Demand Paradigm for ATM Networks: Modeling, Simulation, and Performance Analysis

With networks increasingly moving into virtually every aspect of our daily life, security is gaining importance, not only from the traditional perspective of communication but the network's growing role in modern automation and control. The traditional, certification based approach attempts to guarantee the security of a network through certification. Certified networks are generally confined to a limited domain and, as a result, they are isolated, costly, and under-utilized. In contrast, this paper presents a new principle – user-level, security-on-demand system, wherein the network allocates, where possible, the security resources commensurate with the user's request for transporting message(s) through the network securely. This principle is successfully demonstrated for the current Asynchronous Transfer Mode (ATM) networks, and is the result of an integration of the fundamental framework for network security, recently proposed by the authors in the literature, with the unique characteristics of ATM networks. The framework encapsulates the fundamental knowledge and set of relationships in network security and permits scientific and systematic reasoning about network security. It also enables all user groups – military, government, industry, and academia, to define their security requirements in a uniform manner. The security-on-demand approach promises the development of a "mixed use" class of networks in the future that may be simultaneously shared by different groups of users, with the system sustaining the diverse security requirements of each user. A unique characteristic in ATM network design is the dynamic call setup process. Under it, a network first establishes a virtual path or route for a user's call, guided by the user's requirements, and then transports the messages when a route has been successfully determined. This unique ATM characteristic is integrated with the framework to yield a successful demonstration of the proposed, user-level, security-on-demand approach. Utilizing the security framework as the foundation, every element of the network – node and link, is characterized by a security matrix that reflects its security resources. Every user is permitted to specify the security requirement for the call through a matrix, which expresses the limits of the security resources that the traffic cells must encounter during their transport through the network. Thus, during the dynamic establishment of the virtual path, every node and link is examined to ensure that the user-specified security is met, in addition to bandwidth and other Quality of Service (QoS) requirements. Traffic is launched when the call setup succeeds, otherwise, the call fails. Like all networks, the ATM network inherently consists of geographically dispersed entities and, as a result, the resource allocation strategy is necessarily distributed. Furthermore, as the network operation progresses, the resource availability scene changes dynamically. This paper proposes a unique function that reduces the key network resource parameters at a node to a single value, termed Node Status Indicator (NSI). The NSI value is computed dynamically at every node and disseminated across the network to be utilized by a node to refine its determination of a virtual path for a user call. The aim of the NSI is to improve the resource utilization in the network. The proposed approach is modeled for a large-scale, representative, 40-node ATM network. Utilizing stochastic input traffic that is synthesized to reflect realistic operating conditions, the model is simulated extensively on a testbed of 35+ Pentium workstations, under Linux, configured as a loosely-coupled parallel processor, utilizing an accurate, asynchronous, distributed simulator. The simulator implements the key characteristics of the ATM Forum proposed P-NNI 1.0 and UNI 3.0 standards. While the simulation results reflect a successful realization of the proposed approach, analysis reveals minimal impact of incorporating security on ATM network performance, as measured through call success rates and call setup times. In contrast, the tradition has been to incorporate security into large-scale systems and networks as an afterthought, i.e. adding hardware and software devices after the design has been completed, resulting in performance degradation. Also, while the use of NSI is observed to yield slightly lower average call setup rates and slightly higher average call setup times, a careful analysis of the trace of the calls as they progress through the system, reveals that, in general, calls are dispersed throughout the network, seeking to utilize all available resources of the network more evenly.

A comparative analysis of virtual versus physical process-migration strategies for distributed modeling and simulation of mobile computing networks

Improvements in processor power and diminishing processor costs coupled with the potential of asynchronous, distributed algorithms promise to expand the frontier of mobile computing networks. In general, a mobile computing network consists of semi-autonomous or autonomous stationary and mobile agents that perform local computations, cooperate, and communicate among themselves to achieve a desired objective. While the stationary entities are connected through a static interconnection network and interact with each other, the mobile units interact dynamically with the stationary entities. Examples of newly emerging mobile computing networks include route guidance in the U.S. Department of Transportation's Intelligent Vehicle Highway Systems, distributed scheduling in railway networks, semi-autonomous decision making in the battlefield environment, and the community health care network wherein mobile physicians may interact with remote patient medical records. This paper focuses on the high level principles that underlie the distributed modeling and accurate simulation of mobile computing networks on a parallel processing testbed. The testbed consists of a network of workstations configured as a loosely-coupled parallel processor and it closely resembles reality. A key issue is the representation of the stationary and mobile entities of the mobile computing network through concurrent and interacting processes in the testbed. The nature of the representation will influence the accuracy and performance of the simulation. This paper first reviews a process representation technique that has been proposed in the literature for modeling railway networks and then analyzes its limitations. This strategy is referred to as Virtual Process Migration (VPM). The paper then proposes a new strategy, termed Physical Process Migration (PPM), that aims to address the limitations of VPM. It details the software techniques underlying both approaches, describes their implementations on a realistic testbed, and then contrasts their performance under different representative scenarios. While VPM is capable of modeling modest to large-scale mobile computing networks on a testbed consisting of a few processors, the number of processors of the testbed in PPM must correspond to the number of stationary and mobile entities of the mobile computing network size that is being modeled. Analysis of the simulation results reveals that both VPM and PPM are highly effective and very useful strategies under different circumstances. For a given number of mobile and stationary entities, simulation under PPM is fast when every mobile entity requires significant computation. On the other hand, VPM exhibits superior performance relative to PPM when the number of data elements exchanged by each mobile entity at each hop is significantly high.

A Fundamental Framework for Network Security Towards Enabling Security on Demand in an ATM Network

The traditional, certification based approach attempts to guarantee the security of a network through risk analysis that involves the static analysis of the risks, threats, resource availability, cost, and other parameters. Certified networks are generally confined to a limited domain and, as a result, they are isolated, costly, and under-utilized. This paper integrates the recently introduced fundamental framework for network security with the fundamental and unique characteristics of ATM networks towards a new paradigm-user level security on demand. The framework approach has been adopted by the US National Security Agency as the basis for its Network Rating Model. The framework consists of eight perspectives and nine attributes. The perspectives, termed pillars in this paper, individually provide orthogonal views of network security and collectively constitute a comprehensive stable structure that supports the total network security. The attributes refer to the inherent characteristics of a secure network. The framework provides a basis to address, fundamentally, every weakness in a given network. It also enables the understanding of the security posture of an individual network, in a comprehensive manner, the comparative evaluation of the security of two or more networks, and the determination of the resulting security of a composite network that is formed from connecting two or more networks with known security. In the proposed security on demand approach, the security posture of every node and link is computed, utilizing the framework. Under call setup, the ATM network allows the system to configure, i.e. first project and then verify through propagating a setup message containing a DTL (designated transit list), a route from the source to the destination, including every intermediate ATM node and link, that meets the requirements of every user. Every user specifies the appropriate elements of a security matrix that represents the desired security requirements, in addition to the usual bandwidth and other quality of service (QoS) requirements. Traffic is launched when the call setup succeeds, otherwise, the call fails. Thus, the approach is consistent with the basic characteristics of, is fundamentally the most logical approach to security in, and offers comprehensive security in ATM networks. It also views security as a distributed network resource and allocates it to each user efficiently, based on demand and dictated by the need. The approach has been integrated into the call admission control (CAC) algorithm of the ATM Forum proposed Private Network-Network Interface (PNNI), modeled for a representative, 50-node ATM network, and an asynchronous distributed simulation is executed on a testbed of 25+ Pentium workstations under Linux, configured as a loosely-coupled parallel processor. While the success of the implementation validates the approach, the asynchronous distributed simulation closely resembles an operational ATM network. Performance results, obtained utilizing stochastic and representative input traffic, reveal that the overhead of integrating security into CAC is negligible.

Modelling and performance assessment of large ATM switching networks on loosely-coupled parallel processors

A parallel simulation tool has been developed with the aim of evaluating the performance of a class of ATM switching systems. In this paper, the class of ATM switching networks of interest and the corresponding modelling are addressed. An appropriate decomposition scheme is revealed with respect to the model being built. The performance of the parallel tool is examined, based on a scalable ATM switching network, by means of a loosely-coupled parallel computer system. A combination of general purpose and problem specific algorithms results in a high computational efficiency, portability and scalability.

A distributed algorithm for fault simulation of combinatorial and asynchronous sequential digital designs, utilizing circuit partitioning, on loosely-coupled parallel processors

Fault simulation constitutes an indispensable tool in ensuring the correctness and quality of manufactured digital designs. Traditional uniprocessor based algorithms for fault simulation have been observed to be agonizingly slow for today's large and complex digital designs. More recently, a few researchers introduce an approach, as evident in the literature, wherein the fault set is partitioned and the digital design fault simulated for each of the fault subset on separate processors of a parallel processor system. The approach is limited in that it continues to utilize the traditional uniprocessor-based algorithm and the performance results are not encouraging. This paper introduces, perhaps for the first time, a distributed algorithm that is capable of fault simulating both combinational and asynchronous sequential digital designs on parallel processors. An underlying assumption of the algorithm is that the digital design, under fault simulation, is partitioned by the user. In this approach, referred to as NODIFS in this paper, every component in the circuit is modeled as an asynchronous, concurrent, entity that is fault simulated as soon as appropriate signal transitions and fault lists are asserted at its input ports. The circuit partitioning is such that components of every partition are allocated to a unique processor of the parallel processor system. Consequently, a number of components may be concurrently fault simulated on multiple processors in NODIFS implying significant increase in throughput. This approach promises (i) very high throughput because of its ability, in principle, to utilize the maximal inherent parallelism, and (ii) scalability. The algorithm is novel in that the overall task of decision-making i.e., fault simulation of the circuit, is distributed into a number of natural, independent, and concurrent entities that execute asynchronously to utilize maximal parallelism. NODIFS's success is the result of the asynchronous distributed discrete-event simulation algorithm, YADDES, and a new approach to fault simulation. The notion of scalability implies that where the problem size increases, the algorithm continues to apply and, by increasing the number of computational engines proportionately, the performance of the algorithm will continue to increase. Furthermore, NODIFS is a natural choice for fault simulation of digital designs at the behavior-level — an eventual reality, wherein the ratio of the computational to communication load for the behavior models may approach a significantly large value. This paper also reports on an implementation of NODIFS on both the ARMSTRONG parallel processor system at Brown University and the performance results indicate significant increase in the speedup for a few representative example digital designs. It is stressed that the representative digital designs serve to support the mathematical validity of the algorithm along with the proof of correctness and not to demonstrate a high-performance, commercial, industrial-quality fault simulator.

An asynchronous distributed approach for the simulation of behavior-level models on parallel processors

Traditional approaches to the distributed simulation of digital designs are limited in that they are inefficient and prone to deadlock for systems with feedback loops. This paper proposes an asynchronous distributed algorithm to the simulation and verification of behavior-level models and describes its implementation on an actual loosely-coupled parallel processor. The approach is relatively efficient for realistic digital designs and mathematically shown to be deadlock free. Additionally, it includes a new technique for modeling the timing of digital systems that guarantees the accuracy of the simulation results. In the discipline of computer-aided design of digital systems, a behavior model refers to a compact and executable representation of the activities of a complex digital component or an entire digital system such as the Motorola 68000, expressed through a high-level hardware description language such as ADLIB or VHDL. Behavior models are popular because of their flexibility; however, they execute excruciatingly slow on uniprocessor computers. The approach presented in this paper has the potential to significantly reduce the execution time through concurrent execution on multiple processors. >

A Distributed Approach to Real-Time Payments-Processing in a Partially-Connected Network of Banks: Modeling and Simulation

The payment-processing system in the banking industry consists of deposits, withdrawals, and transfers of monies through the use of cash, checks, magnetic tapes, and electronic transactions. Of these, nearly all of the check processing through the United States Federal Reserve System, most of the check processing in the private networks, and a part of the electronic transactions are realized through the utilization of the principles of batch- mode processing. Batch-mode processing suffers from many limitations, the principal ones being that (i) users are denied real-time access to their money and that (ii) a user's banking privileges cannot be extended anywhere in the USA — a facility that is increasingly being demanded by users. This paper observes that the banking process may be mathematically mapped to a discrete-event simulation system with feedback loops wherein deposits, withdrawals, and transfers may be modeled as events that are introduced into the system asynchronously i.e., at irregular intervals of time. It proposes a new, distributed architecture for payments processing within a network of major banks as an alternative to the Federal Reserve System. This approach distributes the processing operations to multiple, concurrent, cooperating geographically distributed computers i.e., at many sites, to achieve real-time transaction processing. It utilizes the principles of asynchronous, distributed, discrete-event simulation algorithm utilizing pseudo- transaction (timestamps), and mathematically guarantees the accrcracy of every transaction. Given that the major banks are geographically distributed throughout the entire country, the distributed nature of the algorithm, proposed in this paper, is extremely appropriate. It offers the hope of a banking system that is available, transparently, to a user anywhere within the coverage area of the network. While the balances of accorents at each of the major banks are owned exclusively by the respective banks, thereby implying privacy and security, any transaction inserted anywhere in the system is guaranteed to be correctly routed to the target bank for execution. This architecture assumes that the banking nodes are partially connected through a broadband-ISDN Network. The choice of B-ISDN is timely given the importance of global, electronic banking in the world economy and CCITT's desire to standardize B-ISDN for all telecommunications in the world. This paper also reports on an implementation of a model of a network of major banking nodes on a network of SUN workstations, configrcred as a loosely-coupled parallel processor system, at Brown University. Performance analysis indicates that this approach achieves a very high throughput for transaction processing.

Local uniform mesh refinement on loosely-coupled parallel processors

Multiprocessor systems offer large gains in performance if algorithms for real problems can be found. We show how one algorithm for solving time dependent partial differential equations, local uniform mesh refinement, can be implemented on a multiprocessor system. Care is taken to insure that communications costs are kept under control, and an estimate of the performance of this algorithm for a range of configurations is presented. Experiments on a multiprocessor system are compared with the theory.

Solving PDEs on loosely-coupled parallel processors

Partial differential equations (PDEs) account for a large part of scientific computing. As a special domain, they have a number of features which makes their solution on parallel computers particularly attractive. One is the highly-ordered structure of most solution algorithms; there is a regular pattern of memory access. Another is the wide range of solution algorithms from which to choose. Loosely-coupled parallel processors, using a message passing interprocessor communication mechanism, appear to match the data communication requirements of algorithms for PDEs. However, there are many unanswered questions: What is the best communication topology? How fast should the communication be relative to the floating-point speed? How much memory should each node have? The answers to these questions depend on the algorithms chosen. In this paper, we will look at three different classes of algorithms for PDEs and discuss their implications. From these results, we can make recommendations about the design of the next generation of these parallel computers.