Loop Delay Research Articles

A 158-mW 360-MHz BW 68-dB DR Continuous-Time 1-1-1 Filtering MASH ADC in 40-nm CMOS

This article presents a 5-GS/s continuous-time (CT) multi-stage noise-shaping (MASH) analog-to-digital converter (ADC). The ADC consists of three first-order modulators with a 3-bit quantizer/digital-to-analog converter (DAC) per stage. An RC-hybrid stabilization DAC is used to compensate for the excess loop delay and excess phase shift. A delay matching all-pass input filter with a low-pass feedforward filter is employed to suppress input signal leakage. As a result, inter-stage DACs are waived in residue generation, and low-power, area-saving Gm-C integrators are enabled in the back-end stages. The MASH ADC was implemented in 40-nm CMOS and occupies 0.21 mm2. The ADC achieves 68-dB dynamic range (DR) and 65-dB signal-to-noise and distortion ratio (SNDR) over a 360-MHz bandwidth (BW). The ADC consumes 158 mW from 1/1.1/1.8 V supplies, yielding 159-dB Schreier figure-of-merit (FOM) and 151-fJ/Conv. Walden FOM.

Dynamic Grid Voltage-Based Impedance-Reshaped Control for the Stability Enhancement of Grid-Connected DC/AC Converter System under Bidirectional Power Flow

Considering the bidirectional three-phase DC/AC converter, it presents different impedance characteristics on AC side under different power flow directions, resulting in different stability margin. This may cause the system instability at high-power level. This directionally oriented stability difference has not been paid enough attention in the grid-connected converter control. To mitigate the stability variations under bidirectional power flow, a dynamic grid voltage-based impedance reshaping control is proposed in this paper. The proposed method extracts the grid voltage dynamic component, and correspondingly compensates the power output, which is capable of regulating the power output coordinated with voltage dynamics in both power flow directions, neutralizing the stability difference and enhancing the bidirectional power flow stability. Unlike the conventional unidirectional damping optimization control in the current loop, the proposed control method can maintain satisfied stability under bidirectional power flow through the grid side voltage, which can avoid increasing the current loop delay, and thus endow the converter flexible bidirectional power process capability. The effectiveness of the proposed method has been verified by both simulations and experiments.

532-nm-modulated pulse generation based on a time-delay loop and polarization rotation.

A simple and low-cost scheme of generating 532 nm modulated pulses is investigated both theoretically and experimentally. The modulator is an external cavity based on a temporal delay loop and polarization rotation that is realized by two half-wave plates. Propagating in the temporal delay loop multiple times and being outputted partially after each round trip, the intensity of the initial green laser pulse is modulated. By analyzing the polarization of the pulse in each round trip, the pulse train is modeled to simulate the waveform of the modulated pulse. This modulator is coupled with a sub-nanosecond 532-nm-laser source to verify the model of intensity modulation. In the experiment, by rotating the HWPs, modulated pulses with various temporal profiles are obtained. The fundamental modulation frequency is calculated to be 520 MHz, and the frequency of the second harmonic also exceeds 1 GHz. Such a scheme of intensity modulation can be applied in underwater detection and ranging.

LCL‐filter resonance suppression in grid‐connected inverter based on strictly real positive plant strategy

AbstractResonance is one of the most significant challenges in a voltage source inverter interfaced with the grid through an LCL filter. The capacitor current (CC) damping control methodology is considered due to its high‐quality of grid injected current feature. It is widely accepted that the proportional CC feedback compensation damping method becomes ineffective at critical resonance frequency due to control loop delays and may result in an unstable system under grid impedance or filter parameters variations. A suitable differential compensator placed in the CC feedback path can address this issue with a trade‐off between robustness and noise rejection capability. This paper offers a different design method called parallel feedforward compensation (PFC) method, which builds an almost strictly real positive (ASRP) plant and realized damping with enhanced stability features. In the proposed alternative, a compensator consisting of a damping gain and a sampled delay is placed across the filter plant and filter CC feedback loop and the joint output of this augmented plant is then transmitted back at the reference point on the input side of the inverter to attenuate the undesirable resonance peak. The control response and stability performance analysis show that the suggested methodology offers a wide damping region, high robustness, and improved control performance. Simulation and experimental results are presented to confirm the theoretical findings.

Dynamical analysis of a delayed p53 oscillator model with p53-Mdm2 positive feedback

The p53 oscillator is an essential cell fate controller after DNA damage. In general, the delayed p53-Mdm2 negative feedback loop is thought to be the foundational structure responsible for p53 oscillations. However, it is experimentally found that Mdm2 also has a positive effect on p53. Therefore, we redevelop a p53 model to investigate the effect of the p53-Mdm2 positive feedback loop and time delay on p53 oscillations. To study the effect of delay on the Hopf bifurcation, we analyze the characteristic equation of the linearized system and apply the central manifold method to determine the properties of the Hopf bifurcation. The theoretical results are proved numerically. Furthermore, we reveal that the delay induces not only oscillatory birth but also oscillatory death, depending on the parameters in the positive feedback. Finally, considering the biological background, we discuss the effects of the p53-Mdm2 positive feedback parameters on the amplitude of p53 oscillations. This work may be helpful for artificially altering p53 dynamics and even cell fate.

A new method for self-organized dynamic delay loop associated pipeline with reconfigurable computing system

<span>The minimization of propagation delay between pipeline stages is very important in wave propagation through pipeline-stages. The propagation delay can be minimized by minimizing the number of stages in a pipeline. In the proposed design a dynamic stage control is imparted in the pipeline. The propagation delay can be optimized in any type of pipeline by controlling number of stages dynamically. The pipeline interpretation helps a lot to overcome the flaws due to not ready sequence (NRS) and synchronization problems. It is observed that, in the pipeline design the basic and actively involved pipeline techniques are concerned with different challenges like clock, throughput, cell area, and sizes. As the data throughput increases the number of stages in pipeline also needs to be increased to meet the desired goal. In the case of unpredictable data speed, the definite number of pipeline stages creates severe problems. In this work a dynamic pipeline is integrated where the number of stages is dynamically changing depending up on data speed. In dynamic pipeline technique the circuit cell area of reconfigurable computing system (RCS) will be reduced dynamically at low-speed data transmission. In the high-speed data communication, the data speed is managed and controlled by dynamic delay loops.</span>

Effect of High Frequency Gain on the Performance of Optical Costas Loop in Face of Loop Delay

Objectives: Optical costas loops (OCLs) are widely used in optical communication as homodyne receivers. Due to use of different electronic counterparts and fibre optic cable inherent loop delay always presents in the system. The steady state behaviours of optical costas loop are highly affected by the presence of loop delay. Different nonlinear behaviours may be observed due to presence of delay. There are two main objectives of this article. Firstly, how OCL can be operated as stable receiver up to some large value of loop delay by using a proportional plus integrating type loop filter (LF). Secondly, how a controlled chaotic optical signal can be generated from OCL by choosing the system parameters in correct manner. Methods: To investigate system behaviours of OCL both analytical and numerical methods have been used. Stability analysis of OCL has been done by Routh-Hurwitz method. From stability analysis, it is possible to predict the stable and unstable behaviour of the OCL in presence of delay and how system stability can be improved by high frequency gain value of LF. Numerical methods have also been used to solve the nonlinear equation of OCL to observe real time behaviours. Findings: Analytical findings show that loop stability can be improved by increasing the value of high frequency gain of LF. For large value of loop delay, chaotic oscillation of phase error may be observed in OCL. The chaotic oscillation can also be controlled by high frequency gain with certain extent value of loop delay. All the numerical findings have been properly verified with numerical results. Novelty: This article describes how effects of loop delay can be controlled to run OCL in steady as well as in unsteady state. From designer’s point of view this study would be helpful to choose correct values of system parameters to improve the performance of OCL in optical communication. It also gives the idea for generation of chaotic optical signal, which is used in secured communications. Keywords: Optical Costas loop; Optical Phase locked loop Phase detector; Loop filter; Nonlinear dynamics; and optical communications

Applying stochastic network calculus to logical link control layer in underwater wireless communication: Underwater fish farming perspective

AbstractIn recent days, research in underwater fish farming has been seen as a sustainable method to land‐based fish farming due to the increasing global population and limitations in land‐based farming areas worldwide.The fish farming cage installations are usually operated in the depth area of seawater and are ideal circumstances for fish farming. Monitoring sensor‐based data collection from fish farming is highly efficient and more innovative. Due to the unique properties of seawater, the substantial challenge of an Underwater Wireless Sensor Network (UWSN) is guaranteeing reliable data communication between the underwater sensor nodes and surface nodes. To ensure reliable communication, the mathematical approach Stochastic Network Calculus (SNC) is considered for modeling the reliable data flow control in the logical link control layer to satisfy the requirements of the underwater fish farming application. This paper presents the SNC mathematical model construction of stochastic bounds for frame flow, window size, service element analysis, feedback loop analysis, delay, and backlog bounds derived in the proposed model. The proposed model produces the better frame delivery and throughput in an incremental order with respect to the simulation model. There is significant difference (4 to 12 percentage) between the stochastic and simulation model. Thus, the reliable frame flow can be adopted with the dynamic changes in the feedback loop to avoid the overflow by repeated requests.

Controlling birhythmicity in a new Dual Loop Optoelectronic Oscillator with an injection locked van der Pol oscillator

In the present literature, an attempt has been made to understand the birhythmic behaviour of a modified time delayed Dual Loop Optoelectronic Oscillator (DLOEO). To this end, an analytical solution of periodic oscillation is obtained using weakly nonlinear analysis. Two coexisting periodic oscillations are identified, considering shorter loop delay as a control parameter. Subsequently, to control the birhythmicity, a self-feedback mechanism is applied that incorporates the variable to be controlled and its canonical conjugate. Our study reveals that with proper control of the feedback strength, birhythmicity can be removed and monorhythmicity can be induced in the oscillator.

Processing-Speed Enhancement in a Delay-Laser-Based Reservoir Computer by Optical Injection

A delay-laser-based reservoir computer (RC) usually has its processing speed limited by the transient response of laser dynamics. Here, we study a simple all-optical approach to enhancing the processing speed by introducing optical injection to the reservoir layer of conventional RC that consists of a semiconductor laser with a delay loop. Using optical injection, the laser’s transient response effectively accelerates due to the speeded carrier-photon resonance. In the chaotic time-series prediction task, the proposed RC achieves good performance in a flexible range of injection detuning frequency under sufficient injection rate. Using proper injection parameters, the prediction error is significantly reduced and stabilized when using high processing speed. For achieving a prediction error below 0.006, the optical injection enhances the processing speed by an order of magnitude of about 5 GSample/s. Moreover, the proposed RC extends the advantage to the handwritten digit recognition task by achieving better word error rate.

A Technical Framework for Musical Biofeedback in Stroke Rehabilitation

In this article, we present a technical framework aimed at facilitating musical biofeedback research in poststroke movement rehabilitation. The framework comprises wireless wearable inertial sensors and software built with inexpensive and open-source tools. The software enables layered and adjustable music synthesis and has a generic movement–music mapping module. Using this, we designed digital musical interactions for balance, sit-to-stand, and gait training. Preliminary trials with subacute stroke patients indicated that the interactions were clinically feasible. Expert interviews with a focus group of clinicians were also conducted, where these interactions were deemed as meaningful and relevant to clinical protocols, with comprehensible feedback (albeit sometimes unpleasant or disturbing) for several patient types. We carried out system benchmarking, finding that the system has sufficiently short loop delays ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 90 ms) and a healthy sensing range ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$&gt;$</tex-math></inline-formula> 9 m) and is computationally efficient (11.1% peak CPU usage on a quad-core processor). Future studies will focus on using this framework with patients to both develop the interactions further and measure their effects on motor learning, performance retention, and psychological factors to help gauge their true clinical potential.

Hybrid Integrated Low Noise Optical Phase-Locked Loop Based on Self-Injection Locked Semiconductor Laser

The combined spectral linewidth of master and slave laser and loop propagation delay are the trade-offs for suppressing residual loop noise in optical phase-locked loop systems. To reduce the slave laser’s linewidth and shorten the loop delay, a heterodyne hybrid optical phase-locked loop system that packages self-injection locked semiconductor laser, photodiode, the electronic circuit is proposed. By employing a DFB laser diode coupled to a microring resonator based on Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> integrated waveguide platform, the slave laser realizes a narrow spectral linewidth of 2.8 kHz. Due to the full use of the external microring cavity, the optical path delay is shortened to 30 ps. In this way, the residual loop noise has been reduced to −70 dBc/Hz at as low as 10 Hz offset from the carrier frequency, and phase noise variance is 0.0018 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$rad^{2}$</tex-math></inline-formula> at 600 MHz carrier frequency for offset between 10 Hz and 10 MHz.

2D and 3D Visualization for the Static Bifurcations and Nonlinear Oscillations of a Self-Excited System with Time-Delayed Controller

This research focuses on the nonlinear vibration control of a self-excited single-degree-of-freedom system. The integral resonant controller (IRC) is introduced to stabilize the unstable motion and suppress nonlinear oscillations of the considered system. The nonlinear dynamical equations that govern the vibratory behaviors of the proposed closed-loop control system are investigated using perturbation analysis, where loop delays have been included in the studied model. The system bifurcation behaviors have been visualized in both the two and three-dimensional spaces, and corresponding dynamical behaviors have been explored numerically using the bifurcation diagrams, Poincaré map, time-response, zero-one chaotic test algorithm, and frequency spectrum. The obtained analytical investigations revealed that the uncontrolled system can oscillate with one of four vibration modes depending on the excitation frequency, which are mono-stable periodic motion, bi-stable periodic motion, periodic and quasi-period motion, and quasi-periodic motion only. In addition, it is found that the existence of time delays in the control loop can either improve or degrade the control performance. Therefore, an objective function has been introduced to design the optimum control parameters. Based on the derived objective function, it is found that the performance of the proposed control strategy is proportional to the product of the control and feedback gains and inversely proportional to the internal loop feedback gain when the loop delays are neglected. Moreover, it is reported that the controller performance is a periodic function of the total sum of the loop delays. Accordingly, the optimal operating conditions of the time-delayed integral resonant controller have been explained. Finally, numerical validations for all obtained analytical results have been performed, where an excellent correspondence between the analytical and numerical investigations has been demonstrated.

A 2.4–8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input–Output Phase Detection

This paper presents a phase rotator (PR)-based delay-locked loop (DLL) for a dynamic random-access memory interface in 28-nm CMOS technology. A direct input-output comparison using a sub-sampling technique reduces the effect of a timing mismatch of a replica delay line for synchronizing an input clock and output strobe clock. A divided clock samples the input clock for phase alignment. A 4-b analog-to-digital converter was used for input phase acquisition. The output phase is aligned with respect to the sampling clock phase using a bang-bang phase detector. Two DLLs for the input-output synchronization are implemented in a cascade structure, and the loop delay of the replica delay line is considerably reduced. In the proposed DLL, a PR delay line using an 8-phase clock generator is adopted for linearity to reduce the phase difference of the phase interpolation from π/2 to π/4. The resolution of the PR-DLL is 7-b of 2π, which consists of a 3-b coarse and a 4-b fine control. The DLL operates from 2.4 to 8 GHz, and the power dissipation at the maximum input frequency is 20.2 mW. The measured clock root mean square jitter was 1.68 ps. According to the simulation results, the phase mismatch between the input and output clocks was reduced by 80.5%.

A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp

This paper proposes a 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> order continuous-time delta-sigma modulator (CTDSM) with a single amplifier biquad (SAB) and excess loop delay (ELD) merged integrator. The integrator enables a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> order noise-shaping together with ELD compensation with just a single Opamp and feedback DAC. A three-stage Opamp with a hybrid frequency-compensation scheme is presented, which achieves high gain and large unity-gain bandwidth (UGBW) with low power. The circuit secures an extra order noise-shaping through a passive noise-shaping SAR (NS-SAR) quantizer (QTZ) while further incorporating a preliminary sampling and quantization (PSQ) technique, the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> order NS QTZ can run at 1.5 GHz with 6b. The design, implemented in 28 nm, obtains 74.4 dB SNDR with 50 MHz bandwidth while consuming 10.4 mW from 1.5 V and 1 V power supplies. The prototype attains a dynamic range of 80.6 dB with a Schreier FOM of 171.2 dB. With the presented integrator and Opamp, the loop filter only consumes 14 % of the total DSM power consumption.

Optical square-wave generation in a semiconductor laser with optoelectronic feedback.

We report self-sustained optical square-wave (SW) generation in a semiconductor laser diode subjected to delayed optoelectronic feedback on its injection current (J). This optoelectronic oscillator relies on nonlinear effects present in both the laser diode and in the optoelectronic feedback loop through amplifier saturation. The repetition rate of the SW is an integer multiple of the inverse of the loop delay, while the duty cycle can be tuned with J.

A Capacitor-Reused 2b/Cycle Active-Passive Second-order Noise-Shaping SAR ADC

In this manuscript, a novel 2nd-order noise-shaping successive-approximation register (NS-SAR) analog-to-digital converter (ADC) is introduced for potential application in wideband continuous-time (CT) ΔΣ modulators. The proposed NS-SAR employs a special active-passive residue filter that reuses the capacitor of the reference digital-to-analogue converter (DAC) of the SAR. Compared to the conventional NS-SAR that uses an active residue filter, the proposed approach saves one power-hungry amplifier and four replica DACs. An asynchronous 2b/cycle conversion scheme is adopted for a reduced excessive loop delay (ELD) in the modulator. Transistor-level simulations in a 65nm CMOS process are presented to demonstrate the principle of the proposed NS-SAR.

Computation of time-delay for Delayed Network Controlled Temperature Control System

This paper presents an Investigation on the stability of network controlled temperature control system having Time-Invariant feedback delays, by utilizing a direct method for TDS stability analysis. A PI controller based stability analysis for temperature control system with Time invariant feedback loop delay has been constructed in this paper. The stability problem has been formulated based on the transfer function model of the closed loop system with various time delays. For different subsets of the controller parameters, based on the stability criterion’s maximal permissible bound of the network link delay that the closed loop system can accommodate without losing the stability has been computed. The effectiveness of the obtained result was validated on a benchmark temperature control system using MATLAB simulation software.

A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications

A high-speed wide-range all-digital delay-locked loop (ADDLL) suitable for double data rate (DDR1)–DDR5 applications is proposed. The proposed architecture combines the advantages of synchronous mirror delay and delay-locked loop (DLL), which can solve the dynamic tracking problem without requiring a long locking time. In addition, the operating range of the aforementioned architecture is extended through harmonic locking detection and autocalibration technologies. For verification, an experimental chip was fabricated using a 90-nm standard CMOS process with a 1-V power supply. The core area occupies 381 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text {m} \times 234\,\,\mu \text{m}$ </tex-math></inline-formula> . The measurement results indicate that the operating range of the proposed ADDLL was from 0.1 to 2.7 GHz, and the peak-to-peak period jitter was less than 5 ps. The output error was less than 1.9%, and the maximum quadrature phase error was 3.61°.

A Buffer Management Algorithm Based on Dynamic Marking Threshold to Restrain MicroBurst in Data Center Network

The data center has become the infrastructure of most Internet services, and its network carries different types of business flow, such as query, data backup, control information, etc. At the same time, the throughput-sensitive large flows occupy a lot of bandwidth, resulting in the small flow’s longer completion time, finally affecting the performance of the applications. Recent proposals consider only dynamically adjusting the ECN threshold or reversing the ECN packet priority. This paper combines these two improvements and presents the HDCQ method for coordinating data center queuing, separating large and small flows, and scheduling in order to ensure flow completion time. It uses the ECN mechanism to design load-adaptive marking threshold update algorithms for small flows to prevent micro-bursts from occurring. At the same time, packets marked with ECN or ACK are raised in priority, prompting these packets to be fed back to the sender as soon as possible, effectively reducing the TCP control loop delay. Extensive experimental analysis on the network simulator (NS-2) shows that the HDCQ algorithm has better performance in the face of micro-burst traffic, reducing the average flow completion time by up to 24% compared with the PIAS.