Loop Body Research Articles

SPATIAL SEISMOLOGY OF A LARGE CORONAL LOOP ARCADE FROMTRACEAND EIT OBSERVATIONS OF ITS TRANSVERSE OSCILLATIONS

We present a study of transverse loop oscillations in a large coronal loop arcade, using observations from the Transition Region And Coronal Explorer (TRACE) and Extreme-ultraviolet Imaging Telescope (EIT). For the first time we reveal the presence of long-period transverse oscillations with periods between 24 minutes and 3 hr. One loop bundle, 690 Mm long and with an oscillation period of 40 minutes, is analyzed in detail and its oscillation characteristics are determined in an automated manner. The oscillation quality factor is similar to what has been found earlier for oscillations in much shorter loops. This indicates that the damping mechanism of transverse loop oscillations is independent of loop length or period. The displacement profile along the whole length of the oscillating loop is determined for the first time and consistently between TRACE and EIT. By comparing the observed profile with models of the three-dimensional geometry of the equilibrium and perturbed loop, we test the effect of longitudinal structuring (spatial seismology) and find that the observations cannot unambiguously distinguish between structuring and non-planarity of the equilibrium loop. Associated intensity variations with a similar periodicity are explained in terms of variations in the line-of-sight column depth. Also, we report intensity oscillations at the loop footpoint, which are in anti-phase with respect to the intensity oscillations in the loop body. Lastly, this observation offers the first opportunity to use the transverse oscillations of the arcade to model the Alfven speed profile in the global corona.

Quantum loop programs

Loop is a powerful program construct in classical computation, but its power is still not exploited fully in quantum computation. The exploitation of such power definitely requires a deep understanding of the mechanism of quantum loop programs. In this paper, we introduce a general scheme of quantum loops and describe its computational process. The function computed by a quantum loop is defined, and a denotational semantics and a weakest precondition semantics of a quantum loop are given. The notions of termination and almost termination are proposed for quantum loops. This paper only consider the case of finite-dimensional state spaces. Necessary and sufficient conditions for termination and almost termination of a general quantum loop on any mixed input state are presented. A quantum loop is said to be (almost) terminating if it (almost) terminates on any input state. We show that a quantum loop is almost terminating if and only if it is uniformly almost terminating. It is observed that a small disturbance either on the unitary transformation in the loop body or on the measurement in the loop guard can make any quantum loop (almost) terminating, provided that some dimension restriction is satisfied. Moreover, a representation of the function computed by a quantum loop is given in terms of finite summations of matrices. To illustrate the notions and results obtained in this paper, two simple classes of quantum loop programs, one qubit quantum loops, and two qubit quantum loops defined by controlled gates, are carefully examined, and to show their expressive power, quantum loops are applied in describing quantum walks.

Optimal Loop Unrolling and Shifting for Reconfigurable Architectures

In this article, we present a new technique for optimizing loops that contain kernels mapped on a reconfigurable fabric. We assume the Molen machine organization as our framework. We propose combining loop unrolling with loop shifting, which is used to relocate the function calls contained in the loop body such that in every iteration of the transformed loop, software functions (running on GPP) execute in parallel with multiple instances of the kernel (running on FPGA). The algorithm computes the optimal unroll factor and determines the most appropriate transformation (which can be the combination of unrolling plus shifting or either of the two). This method is based on profiling information about the kernel’s execution times on GPP and FPGA, memory transfers and area utilization. In the experimental part, we apply this method to several kernels from loop nests extracted from real-life applications (DCT and SAD from MPEG2 encoder, Quantizer from JPEG, and Sobel’s Convolution) and perform an analysis of the results, comparing them with the theoretical maximum speedup by Amdahl’s Law and showing when and how our transformations are beneficial.

Modulo scheduling without overlapped lifetimes

This paper describes complementary software- and hardware-based approaches for handling overlapping register lifetimes that occur in modulo scheduled loops. Modulo scheduling takes the N-instructions in a loop body and constructs an M-stage software pipeline. The length of each stage in the software pipeline is the Initiation Interval (II), which is the rate at which new loop iterations are started. An overlapped lifetime has a live range longer than the II, and as a consequence, the current iteration writes a new value to a register before a previous loop iteration has fin-ished using the old value. Hardware and software solutions for dealing with overlapped lifetimes have been proposed by re-searchers and also implemented in commercial products. These solutions include rotating register files, register queues, modulo variable expansion, and post-scheduling live range splitting. Each of these approaches has drawbacks for embedded systems such as an increase in silicon area, power consumption, and code size. Our approach, which is an improvement to the current solutions, prevents overlapped lifetimes through a combination of hardware and software techniques. The hardware element of our approach implements a register assignment latency that allows multiple in-flight writes to be pending to the same register. The software element of our approach uses dependence analysis and a constrained modulo scheduling algorithm to prevent overlapped lifetimes. We describe how to use these hardware and software techniques during modulo scheduling. Finally, we present the results of using our approach to compile embedded application code and present results in terms of modulo schedule quality and application performance.

Towards concurrency refactoring for x10

In this poster, we present our vision of refactoring support for languages with a partitioned global address space memory model as embodied in the X10 programming language. We examine a novel refactoring, extract concurrent, that introduces additional concurrency within a loop by arranging for some user-selected code in the loop body to run in parallel with other iterations of the loop. We discuss the mechanisms and challenges for implementing this refactoring and how development of this refactoring provides insight for designing future refactorings.

VLIW 기반 고성능 DSP에서의 SAD 알고리즘 최적화 스케줄링

SAD(Sum of Absolute Difference) 알고리즘은 동영상 인코더에서 가장 많은 시간이 소용되는 것으로 잘 알려진 움직임 추정에서 가장 자주 계산이 수행되는 알고리즘으로, 동영상 인코딩 수행시간을 줄이기 위해서 우선적으로 최적화 구현되어야 하는 알고리즘이다. 본 논문에서는 VLIW 기반 고성능 DSP 프로세서에서의 조건 분기를 갖는 SAD 알고리즘의 최적 스케줄링 구현 방법을 제안한다. 제안 방법은 먼저 조건 분기를 갖는 중첩 루프를 VLIW 구조가 제공하는 ILP(Instruction Level Parallelism) 능력을 잘 활용할 수 있도록 충분한 크기의 루프 몸체를 가지며 또한 빨리 루프를 탈출 할 수 있는 조건 분기를 갖는 단일 루프로 변환한 후에, 모듈로 스케줄링 기법을 적용하여 VLIW 기반 프로세서에서 최적화 스케줄링 구현을 한다. 제안된 구현 방안을 TMS320C6713에서 구현하고, 코드 크기 및 수행 시간에 대한 성능 분석을 하였다. 구현된 최적화 SAD 루틴은 코드 크기도 크지 않아 임베디드 응용에 적합하며, 이 SAD 구현을 사용한 H.263 인코더가 그렇지 않은 H.263 인코더보다 훨씬 좋은 성능을 보임을 실험을 통해 확인하였다. SAD (Sum of Absolute Difference) algorithm is the most frequently executing routine in motion estimation, which is the most demanding process in motion picture encoding. To enhance the performance of motion picture encoding on a VLIW processor, an optimal implementation of SAD algorithm on VLIW processor should be accomplished. In this paper, we propose an implementation of optimal scheduling of SAD algorithm with conditional branch on a VLIW-based high performance DSP. We first transform the nested loop with conditional branch of SAD algorithm into a single loop with conditional branch which has a large enough loop body to utilize fully the ILP capability of VLIW DSP and has a conditional branch to make the escape from loop to be achieved as soon as possible. And then we apply a modulo scheduling technique to the transformed single loop. We test the proposed implementation on TMS320C6713, and analyze the code size and performance with respect to processing time. Through experiments, it is shown that the SAD implementation proposed in this paper has small code size appropriate for embedded applications, and the H.263 encoder with the proposed SAD implementation performs better than other H.263 encoder with other SAD implementations.

Airway Resistance and Airflow Dynamics after Fat Injection into Vocal Folds

The aim of this prospective study was to verify whether vocal fold fat augmentation (VFFA) modifies upper airway patency. To the best of our knowledge, this is the first study analyzing the impact of VFFA on laryngeal resistance to airflow. Twenty-one consecutive patients 16 to 74 years of age underwent 24 VFFA operations because of glottic incompetence due to laryngeal hemiplegia (13 patients) or vocal fold tissue defects (8 patients). Flow-volume loop spirometry and body plethysmography were performed before and 1 to 6 months after surgery. There were no significant differences between preoperative and postoperative pulmonary volumes (FVC and FEV1), expiratory flows (PEF, FEF50), or inspiratory flows (PIF, FIF50), although a slight increase in inspiratory flows meant that FEF50/FIF50 slightly decreased. Specific airway resistance (sRaw) increased after VFFA, but not in a statistically significant manner (p = .078). None of the patients experienced postoperative stridor. One obese woman with laryngeal hemiplegia had postoperative effort dyspnea; her respiratory studies showed a reduction in inspiratory flows and an increase in sRaw, and demonstrated progressive improvement. Flow-volume loop spirometry showed that VFFA does not significantly modify respiratory airflows, although a slight increase of inspiratory airflows suggested an improvement in variable extrathoracic obstruction. Body plethysmography proved to be a sensitive procedure that highlighted the subtle increase in upper airway resistance. Hence, VFFA can be considered a relatively safe procedure for achieving vocal fold medialization, and spirometry and plethysmography can be useful for preoperative assessment and postoperative follow-up.

Interruptible iterators

This paper introduces interruptible iterators, a language feature that makes expressive iteration abstractions much easier to implement. Iteration abstractions are valuable for software design, as shown by their frequent use in well-designed data structure libraries such as the Java Collections Framework. While Java iterators support iteration abstraction well from the standpoint of client code, they are awkward to implement correctly and efficiently, especially if the iterator needs to support imperative update of the underlying collection, such as removing the current element. Some languages, such as CLU and C# 2.0, support iteration through a limited coroutine mechanism, but these mechanisms do not support imperative updates. Interruptible iterators are more powerful coroutines in which the loop body is able to interrupt the iterator with requests to perform updates. Interrupts are similar to exceptions, but propagate differently and have resumption semantics. Interruptible iterators have been implemented as part of the JMatch programming language, an extended version of Java. A JMatch reimplementation of the Java Collections Framework shows that implementations can be made substantially shorter and simpler; performance results show that this language mechanism can also be implemented efficiently.

Modelling thermomechanical behaviour of multi-axis machine tools

This paper describes a method to measure and model the thermally induced positioning errors of multi-axis machines. These errors result from changes in temperature distribution of such a machine. To achieve a reduction of the machine's tool positioning errors a generally applicable model has been developed. First the temperature distribution of a machine tool is computed from a limited number of sensors. Using this calculated temperature distribution and a deformation model based on the machine's structural loop and rigid body kinematics the tool positioning error is computed. To validate the developed thermomechanical model a new measuring method based on three-dimensional length measurements has been used.

Symbolic method of verification of definite iterations over altered data structures

To extend the application domain of the symbolic verification method, definite iterations over altered data structures, which are found to reduce to standard finite iterations, are introduced. The suggested reduction is applicable to definite iterations over altered data structures that contain an exit statement by a condition depending on the variables modified by the loop body. The suggested generalization of the symbolic method makes it applicable to verifying programs over pointers. To illustrate the discussion, the verification of two programs designed for processing linear lists-searching for an element with reordering and elimination of zero elements--is described.

Three Algorithms for Improving the Effectiveness of Software Pipelining: Comparison and Combination

Software pipelining is a loop scheduling technique that extracts instruction level parallelism by overlapping the execution of several consecutive iterations. One of its drawbacks is the high register requirements, which may lead to software pipelining failure due to insufficient static general registers in Itanium. This paper evaluates the register requirements of software-pipelined loops and presents three new methods for software pipelining loops that require more static general registers than those available in Itanium processor. They reduce register pressure by either reducing instructions in the loop body or allocating stacked non-rotating registers or rotating register in register stack to serve as static registers. These methods are better than the existing techniques in that they further improve performance gain from software pipelining by increasing software-pipelined loops. These methods have been implemented in open research compiler (ORC) targeted for Itanium processor, and they perform well on loops of the programs in NAS Benchmarks. For some benchmarks, the performance is improved by more than 21%.

Spirometric and plethysmographic assessment of upper airway obstruction in laryngeal hemiplegia.

Laryngeal hemiplegia (LH) is the most common disorder of laryngeal motility. It is deemed not to cause obstruction of the upper airway; in fact, the main symptoms are dysphonia and breathiness, and respiratory impairment is not commonly reported. The aim of this study was to objectively assess upper airway patency in 41 patients affected by LH (mean age, 54.4 +/- 15.2 years; 27 female) and 30 controls (mean age, 50.0 +/- 16.1 years; 19 female) by means of flow-volume loop spirometry and body plethysmography to measure specific airway resistance (sRaw) at increasing respiratory frequencies. The causes of LH were cervical surgery (28), tumor infiltration (5), and unexplained (8). None of the patients or controls was affected by lower airway disease. Spirometry showed that the patients had inspiratory flows (PIF, FIF50) significantly lower than those of the controls (p < .0001), whereas the expiratory flows (FEV1, FEF50) were normal, with the exception of peak expiratory flow (PEF), which was reduced, especially in female patients. The mean FEF50/FIF50 ratio (about unity in the normal subjects) was >1, as is typical of variable extrathoracic obstruction. Plethysmography showed that the values of sRaw of the LH group were not statistically different from those of the controls at 30 +/- 5 breaths per minute, but they progressively and significantly increased at 60 +/- 5 (p < .01) and 90 +/- 5 breaths per minute (p < .002), whereas no significant sRaw change was observed in the controls. These results show that LH causes obstruction of the upper airway that can be assessed and quantified by means of spirometry and body plethysmography. A dynamic narrowing due to inspiratory medialization of the paralytic vocal fold and flow turbulence during hyperventilation seem to be the causes of patency impairment. The flow-volume loop is an excellent, inexpensive, and easily available means of functionally evaluating upper airway obstruction, but some patients have difficulty in performing an inspiratory test that requires maximal effort, and the flow reduction during forced ventilation may be partially due to the effort dependency of the tests themselves. Plethysmographic assessment of airway resistance may be a valid alternative or complement, as it reveals an increase in sRaw at increasing respiratory frequencies.

An algorithm for mapping loops onto coarse-grained reconfigurable architectures

With the increasing demand for flexible yet highly efficient architecture platforms for media applications, there is a growing interest in the Coarse-grained Reconfigurable Architectures (CRAs). While many CRAs have demonstrated impressive performance improvement, the lack of compilation technology for such architectures causes a bottleneck in the current design process. In this paper, we present a novel mapping algorithm designed to support Reconfigurable ALU Array (RAA) architectures, that represent a significant class of CRAs. More specifically we present a core mapping algorithm that addresses the problem of placing and routing the operations of a loop body onto the ALU array, to be executed in a loop pipelined fashion. Experimental results using our mapping algorithm on a typical RAA show that our algorithm not only has very fast compilation time but can also generate quality mappings exhibiting high memory bandwidth utilization and low global interconnection requirements. Comparison with manual mapping also indicates that our algorithm can generate near-optimal mappings for several loops.

Performance-constrained hierarchical pipelining for behaviors, loops, and operations

Behavioral specifications of DSP systems generally contain a number of nested loops. In order to obtain high date rates for such systems, it is necessary to pipeline the system within the behavior, within the loop bodies, and also within the operations. In order to hierarchically pipeline a performance-constrained system, an important step consists of distributing the performance constraint among the loops in such a manner that the constraint is satisfied and design cost is minimized. This paper presents an algorithm for propagating constraints and hierarchically pipelining a given throughput-constrained system. Along with pipelining, the algorithm schedules the operations within the loop bodies and selects components for them, with the aim of minimizing cost while satisfying the constraint propagated to the loop body. Results demonstrate the necessity of pipelining across the three granularity levels in order to obtain high performance designs. They also demonstrate the feasibility and quality of our approach, the indicate that it may be efficiently used for synthesizing or estimating within system-level design.

Statement-Level Communication-Free Partitioning Techniques for Parallelizing Compilers

This paper addresses the problem of communication-free partition of iteration spaces and data spaces along hyperplanes. To finding more possible communication-free hyperplane partitions, we treat statements within a loop body as separate schedulable units. Instead of using the information about data dependence distance or direction vectors, our technique explicitly formulates array references as transformations from statement-iteration spaces to data spaces. Based on these transformations, the necessary and sufficient conditions for communication-free partition along hyperplanes to be feasible have been proposed. This approach can be applied to all programs with an imperfectly nested loop or sequences of imperfectly nested loops, whose array references are affine functions of outer loop indices or loop invariant variables. The proposed approach is more practical than existing methods in finding the data and computation distribution patterns that can cause the processor to execute fully-parallel on multicomputers without any interprocessor communication.

Genetic Programming with simple loops

A kind of loop function LoopN in Genetic Programming (GP) is proposed. Different from other forms of loop function, such as While-Do and Repeat-Until, LoopN takes only one argument as its loop body and makes its loop body simply runN times, so infinite loops will never happen. The problem of how to avoid too many layers of loops in Genetic Programming is also solved. The advantage of LoopN in GP is shown by the computational results in solving the mower problem.

A Space-Time Representation Method of Iterative Algorithms for the Design of Processor Arrays

A novel Space-Time Representation (STR) of iterative algorithms for their systematic mapping onto regular processor arrays is proposed. Timing information is introduced in the Dependence Graph (DG) by the definition and the construction of the Space-Time DG (STDG). Any variable instance of the loop body, independently of the number of the loop indices, is characterized by an integer vector composed by its indices, as space part, and an additional time index, representing its execution time according to a preliminary timing. The main advantage of the STR is that the need for the uniformization of the algorithm is avoided. Moreover, it is proven that in the STDG dependence vectors having opposite directions do not exist and therefore a linear mapping of the STDG onto the desired processor array can always be derived. Efficient 2D and 1D regular architectures are produced by applying the STR to the original description of the Warshall-Floyd algorithm for the Algebraic Path Problem.

Modulo scheduling with reduced register pressure

Software pipelining is a scheduling technique that is used by some product compilers in order to expose more instruction level parallelism out of innermost loops. Module scheduling refers to a class of algorithms for software pipelining. Most previous research on module scheduling has focused on reducing the number of cycles between the initiation of consecutive iterations (which is termed II) but has not considered the effect of the register pressure of the produced schedules. The register pressure increases as the instruction level parallelism increases. When the register requirements of a schedule are higher than the available number of registers, the loop must be rescheduled perhaps with a higher II. Therefore, the register pressure has an important impact on the performance of a schedule. This paper presents a novel heuristic module scheduling strategy that tries to generate schedules with the lowest II, and, from all the possible schedules with such II, it tries to select that with the lowest register requirements. The proposed method has been implemented in an experimental compiler and has been tested for the Perfect Club benchmarks. The results show that the proposed method achieves an optimal II for at least 97.5 percent of the loops and its compilation time is comparable to a conventional top-down approach, whereas the register requirements are lower. In addition, the proposed method is compared with some other existing methods. The results indicate that the proposed method performs better than other heuristic methods and almost as well as linear programming methods, which obtain optimal solutions but are impractical for product compilers because their computing cost grows exponentially with the number of operations in the loop body.

Combining Retiming and Scheduling Techniques for Loop Parallelization and Loop Tiling

Tiling is a technique used for exploiting medium-grain parallelism in nested loops. It relies on a first step that detects sets of permutable nested loops. All algorithms developed so far consider the statements of the loop body as a single block, in other words, they are not able to take advantage of the structure of dependences between different statements. In this paper, we overcame this limitation by showing how the structure of the reduced dependence graph can be taken into account for detecting more permutable loops. Our method combines graph retiming techniques and graph scheduling techniques. It can be viewed as an extension of Wolf and Lam's algorithm to the case of loops with multiple statements. Loan independent dependences play a particular role in our study, and we show how the way we handle them can be useful for fine-grain loop parallelization as well.

Resource-Directed Loop Pipelining: Exposing Just Enough Parallelism

Many techniques have been proposed for exploiting instruction-level parallelism, ranging from the optimal and expensive but ignoring resource constraints, to various forms of introducing resource constraints. One of the most aggressive of these techniques is resource-constrained software pipelining (RCSP). RCSP works by repeatedly scheduling successive iterations of a loop in parallel until the data and resource dependence structure of the loop causes the process to converge on a repeating scheduling pattern. This repeating pattern is then used as the new loop body. In principle, this process can be made optimal with respect to full unrolling and scheduling of the loop. Of course, this is not the same as absolute optimality; however, given the NP-hard nature of the problem and the results of Schwiegelshohn et al., this may be the strongest form possible for general loop pipelining. The main drawback of RCSP is that, in practice, its space/time overhead can be fairly expensive. In this paper, we present resource-directed loop pipelining (RDLP), a new approach that attempts to retain many of the advantages of RCSP while minimizing the expense. It does so by allowing the availability of target resources to in some sense guide the application of parallelism exposing and parallelizing transformations. One of the key features of RDLP is the separation of control heuristics from transformations that allow the loop pipelining to be as general as the underlying system of code motion transformations. Results are presented which show that even with very unsophisticated heuristics, RDLP achieves roughly the same performance as RCSP, while providing a fourfold decrease in the space/time cost; moreover, we show that RDLP exposes 'just enough' parallelism-incurs a minimum of code explosion-to maximally utilize resources.