Lookup Table Size Research Articles

A machine learning based efficient and compact full-spectrum correlated k-distribution model

The full-spectrum correlated-k-distribution (FSCK) look-up table previously developed by Wang et al. (2018) provides an efficient means for accurate calculations of radiative properties in nonhomogeneous media, which was constructed for gas mixtures of three species, i.e., CO2, CO and H2O within a large range of thermodynamic states. However, the total size of the FSCK look-up table is about 3.2 GB. In order to obtain accurate k-values for arbitrary thermodynamic states from the tabulated values, a 6-D linear interpolation method has to be employed. In practical applications, transferring and loading such a huge database are inconvenient and time-consuming. In this study, we presented a machine learning approach to accurately fit the FSCK look-up table, in order to provide an efficient and compact FSCK model. Without interpolation on the fly, correct k-distributions for any arbitrary thermodynamic states can be obtained directly and the total size of the trained machine learning model is only about 35 MB.

Huffman-Coded Sphere Shaping and Distribution Matching Algorithms via Lookup Tables

In this paper, we study amplitude shaping schemes for the probabilistic amplitude shaping (PAS) framework as well as algorithms for constant-composition distribution matching (CCDM). Huffman-coded sphere shaping (HCSS) is discussed in detail, which internally uses Huffman coding to determine the composition to be used and relies on conventional CCDM algorithms for mapping and demapping. Numerical simulations show that HCSS closes the performance gap between distribution matching schemes and sphere shaping techniques such as enumerative sphere shaping (ESS). HCSS is based on an architecture that is different from the trellis-based setup of ESS. It allows to tailor the used HCSS compositions to the transmission channel and to take into account complexity constraints. We further discuss in detail multiset ranking (MR) and subset ranking (SR) as alternatives to arithmetic-coding (AC) CCDM. The advantage of MR over AC is that it requires less sequential operations for mapping. SR operates on binary alphabets only, which can introduce some additional rate loss when a nonbinary-to-binary transformation is required. However, the binomial coefficients required for SR can be precomputed and stored in a lookup table (LUT). We perform an analysis of rate loss and decoding performance for the proposed techniques and compare them to other prominent amplitude shaping schemes. For medium to long block lengths, MR-HCSS and SR-HCSS are shown to have similar performance to ESS. SR-HCSS and uniform 64QAM are compared in additive white Gaussian noise simulations and shaping gains of 0.5 dB and 1 dB are demonstrated with 1 kbit and 100 kbit LUT size, respectively.

A Latency-Effective Pipelined Divider for Double-Precision Floating-Point Numbers

In this article, we propose an effective algorithm of pipelined dividers for double-precision floating-point numbers. This reduces the latency of the previous pipelined dividers without increasing the lookup table size. The experimental results show that the proposed divider reduces the overall latency up to 16% compared to the previous divider.

High speed low area OBC DA based decimation filter for hearing aids application

This brief presents a decimation filter for hearing aid application using distributed arithmetic (DA) approach. In this paper, we propose a reconfigurable offset-binary code (OBC) DA based finite impulse response (FIR) filter with a shared look-up table (LUT) updating scheme. The size of the LUTs in DA increases exponentially with the order of filters. Shared LUT based DA structure is a solution to reduce this large memory requirement for higher order filters. The proposed shared LUT updating scheme uses LUT partitioning in which coefficients are spilt into small length vectors and it ensures a drastic reduction in the size of LUTs. The proposed DA filter is synthesized on CMOS 90 nm technology using Synapsis ASIC Design Compiler. The proposed design achieves high speed at a reduced area-delay product (ADP) when compared with recent designs. The proposed architecture is implemented and tested on Virtex 5vsx95-1ff1136 FPGA and the results show that the proposed design involves less number of slices and offers high speed than existing designs. A three-stage decimation filter of hearing aids is designed with the proposed FIR filter and is implemented on the target device by Matlab simulink and Xilinx system generator.

Reduced-size lookup tables enabling higher-order QAM with all-silicon IQ modulators.

We experimentally demonstrate 20 Gbaud 256QAM and 40 Gbaud 128QAM in an all-silicon IQ modulator. We combine a linear equalizer and a nonlinear predistortion implemented in a lookup table (LUT). We achieve bit error rate (BER) below the 20% forward error correction threshold; linear equalization alone cannot achieve this performance. To keep LUT size manageable, we use one dimensional LUTs and prune entries. We achieve good BER even when LUT size is halved. Finally, we verify the generality of the proposed methods on different data sets.

Efficient implementation of lightweight block ciphers on volta and pascal architecture

Lightweight block ciphers based on symmetric cipher are tailored to addressing security issues for highly constrained Internet of things devices. In this article, we explore general software implementations of lightweight ciphers on GPU architectures, with a special focus on LED, Piccolo and PRESENT. First, we implement the lightweight block ciphers using lookup table based technique. Then we analyze the effect of different factors on the encryption performance, such as the size of lookup table, the parallelism level, the use of different type of memory and the idle state caused by data transmission. We evaluated the three lightweight block ciphers on Nvidia Tesla V100 and Nvidia GTX1060 GPUs. Finally, the experimental result shows a great improvement on all the investigated ciphers compared to the unoptimized implementations.

A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation

This paper proposes a configurable direct digital frequency synthesizer (DDFS) based on the lookup-table (LUT)- rotation architecture. To break through the limitation of the single mode, the proposed DDFS is the first attempt which supports four-mode switching on chip. Taking the advantages of small LUT size and pipelined rotation, the DDFS achieves both high-speed and high-resolution properties. The multi-bit rotation tree is helpful to reduce the latency and register usage, which improves the agility and energy efficiency of the DDFS. A partition problem is raised in this paper, and we estimate the optimal solution through both the theory and experiment. Based on the partition, an output can achieve the highest spurious-free dynamic range (SFDR) with as small as possible LUT size. The functionality of the proposed DDFS has been validated in a Xilinx ZedBoard field-programmable gate array. The synthesis and layout results show that the chip achieves maximum 102-dBc SFDR and 2.2-GHz clock frequency. The power consumption and latency cycles reach minimum 6.9 mW/GHz and 7 cycles, which are 20% and 30% reduction compared with the state-of-the-art DDFS.

A 2-D Predistortion Based on Profile Inversion for Fully Digital Cartesian Transmitter

A novel 2-D digital predistortion (DPD) algorithm for fully digital Cartesian transmitter is proposed. The nonlinearity of the digital power amplifier in the digital transmitter necessitates DPD for linearization. In order to shorten the setup time of predistortion coefficients in the lookup table (LUT), a profile inversion-based method is adopted. Compared to the traditional adaptive iterative method, the profile inversion method for DPD in this paper shortens the setup time to $15~\mu \text{s}$ , which is possible for Long Term Evolution (LTE) time division duplex digital transmitter system to execute calibration within every frame. The algorithm is experimentally verified in a fully digital transmitter implemented in 65-nm general process CMOS technology with LUT size of 0.19 mm2, chip size of 2.7 mm2. The digital transmitter has achieved −35- and −32-dBc adjacent channel leakage ratio with 10-MHz LTE and 20-MHz 802.11g WiFi baseband feed in signals, respectively. The DPD improves the linearity of the transmitter by 21 dB for a 2-D constellation signal.

The acceleration algorithm for projection decomposition of dual-energy computed tomography image reconstruction based on projection matching

Dual-energy computed tomography (CT) reconstruction imaging technology is an important development direction in the field of CT imaging. The mainstream model of dual-energy CT reconstruction algorithm is the basis material decomposition model, and the projection decomposition is the crucial technique. The projection decomposition algorithm based on projection matching was a general method. With establishing the energy spectrum lookup table, we can obtain the stable solution by the least squares matching method. But the computation cost will increase dramatically when size of lookup table enlarges and it will slow down the computer. In this paper, an acceleration algorithm based on projection matching is proposed. The proposed algorithm makes use of linear equations and plane equations to fit the lookup table data, so that the projection value of the decomposition coefficients can be calculated quickly. As the result of simulation experiment, the acceleration algorithm can greatly shorten the running time of the program to get the stable and correct solution.

Adaptive segmentation methodology for hardware function evaluators

This paper presents a new adaptive function segmentation methodology to evaluate mathematical functions in hardware systems through piece-wise polynomial approximation methods. In contrast to conventional segmentation techniques, this methodology automatically adjusts the segmentation strategy through a function shape analysis based on the first- and second-order derivatives. Additionally, a particle swarm optimization algorithm is implemented to search for the best segmentation parameters that satisfy the designer-given signal-to-quantization-noise ratio specification and minimize the number of polynomials. The main advantages are a significant lookup table size reduction, increased approximation accuracy of highly nonlinear sections, and the automatic generation of a hierarchy-less segmentation solution. Hence, the proposed methodology enables efficient development of hardware accelerated surrogate models such as wireless channel emulators and other signal processing applications on inexpensive platforms that rely on fixed-point number representation as a compromise between performance, and output accuracy.

Fast Low-Complexity Triple-Error-Correcting BCH Decoding Architecture

An efficient decoding architecture for triple-error-correcting BCH codes is proposed by utilizing a lookup table (LUT) that stores the roots of the error locator polynomial instead of using the Chien search. Two roots of the polynomial equation are precomputed and stored in the LUT in order to relax the hardware complexity. To relax the complexity further, a new method to compress the LUT is additionally proposed. While a large portion of the LUT is filled with unnecessary information in the previous designs, this brief eliminates the redundant information by investigating an algebraic property of the equation. For BCH codes over GF(210), the LUT size is reduced to 18% of the previous work. As a result, the proposed decoding architecture reduces the decoding latency by 38% and the equivalent gate count by up to 40% compared to the previous work, achieving a fast low-complexity triple-error-correcting BCH decoder.

Efficient digit‐serial modular multiplication algorithm on FPGA

For cryptographic applications, such as DSA, RSA and ECC systems, the crypto-processors are required to perform modular multiplication (MM) on large integers over Galois field. A new digit-serial MM method is presented by using a variable size lookup table. The proposed modular multiplier can be designed for any digit-size d and modulus M which only requires simple operations such as addition and shifting. Based on theoretical analysis, the efficient digit-serial MM architecture requires the latency of $O\lpar \lceil n/d\rceil + d + 2\rpar $ O ( ⌈ n / d ⌉ + d + 2 ) clock cycles. As a result, the developed architecture can achieve less area–delay product on hardware when compared with previous designs.

Implementation of memory-efficient linear pipelined IPv6 lookup and its significance in smart cities

The recent trend towards IPv6 (Internet protocol version 6) has gained a great deal of interest with regard to smart cities due to its increased address space. A vital issue in designing a router is to establish the output port of an incoming IP packet along with its destination. Thus, the IP lookup architecture must achieve high speeds, supporting IPv6 with quick real-time updates to serve perpetually developing routing tables. The problem with IP lookup is that of achieving a throughput of more than 100 gigabits per second. In addition, it is difficult to store all the IP lookups in the on-chip memory devices. This paper proposes a new pipeline design called the linear pipelined IPv6 lookup architecture that overcomes the shortcomings of the POLP (parallel optimized linear pipeline) and BPFL (balanced parallelized frugal lookup) algorithms. The new B-tree algorithm is based on the idea of specific prefixes along with robust routing tables. The linear pipelined IP lookup design has been implemented in Verilog HDL using an Altera Quartus Stratix II device. Three different sizes of lookup tables are utilized to assess the proposed method. The logic elements, SRAM, memory and maximum frequency results are better for the proposed method compared with the POLP and BPFL methods.

Reduced-Area Constant-Coefficient and Multiple-Constant Multipliers for Xilinx FPGAs with 6-Input LUTs

Multiplication by a constant is a common operation for many signal, image, and video processing applications that are implemented in field-programmable gate arrays (FPGAs). Constant-coefficient multipliers (KCMs) are often implemented in the logic fabric using lookup tables (LUTs), reserving embedded hard multipliers for general-purpose multiplication. This paper describes a two-operand addition circuit from previous work and shows how it can be used to generate and add pre-computed partial products to implement KCMs. A novel method for pre-computing partial products for KCMs with a negative constant is also presented. These KCMs are then extended to have two to eight coefficients that may be selected by a control signal at runtime to implement time-multiplexed multiple-constant multiplication. Synthesis results show that proposed pipelined KCMs use 27.4% fewer LUTs on average and have a median LUT-delay product that is 12% lower than comparable LogiCORE IP KCMs. Proposed pipelined KCMs with two to eight selectable coefficients use 46% to 70% fewer LUTs than the best LogiCORE IP based alternative and most are faster than using a LogiCORE IP multiplier with a coefficient lookup function. They also outperform the state-of-the-art in the literature, using 22% to 57% fewer slices than the smallest pipelined adder graph (PAG) fusion designs and operate 7% to 30% faster than the fastest PAG fusion designs for the same operand size and number of selectable coefficients. For KCMs and KCMs with selectable coefficients of a given operand size, the placement and routing of LUTs remains the same for all positive and negative constant values, which is advantageous for runtime partial reconfiguration.

SCOPE-Based Emulators for Fast Generation of Synthetic Canopy Reflectance and Sun-Induced Fluorescence Spectra

Progress in advanced radiative transfer models (RTMs) led to an improved understanding of reflectance (R) and sun-induced chlorophyll fluorescence (SIF) emission throughout the leaf and canopy. Among advanced canopy RTMs that have been recently modified to deliver SIF spectral outputs are the energy balance model SCOPE and the 3D models DART and FLIGHT. The downside of these RTMs is that they are computationally expensive, which makes them impractical in routine processing, such as scene generation and retrieval applications. To bypass their computational burden, a computationally effective technique has been proposed by only using a limited number of model runs, called emulation. The idea of emulation is approximating the original RTM by a surrogate machine learning model with low computation time. However, a concern is whether the emulator reaches sufficient accuracy. To this end, we analyzed key aspects of emulator development that may impact the precision of emulating SCOPE-like R and SIF spectra, being: (1) type of machine learning, (2) type of dimensionality reduction (DR) method, and (3) number of components and lookup table (LUT) size. The machine learning family of Gaussian processes regression and neural networks were found best suited to function as emulators. The classical principal component analysis (PCA) remains a robust DR method, but the number of components needs to be optimized depending on the complexity of the spectral data. Based on a small Latin hypercube sampling LUT of 500 samples (70% used for training) covering a selection of SCOPE input variables, the best-performing emulators can reconstruct any combination for the selected SCOPE input variables with relative errors along the spectral range below 2% for R and 4% for SIF. That is sufficient for a precise reconstruction for the large majority of possible combinations, and errors can be further reduced when increasing LUT size for training. As a proof of concept, we imported the best-performing emulators into a newly developed Automated Scene Generator Module (A-SGM) to generate a R and SIF synthetic scene of a vegetated surface. Using emulators as alternative of SCOPE reduced the processing time from the order of days to the order of minutes while preserving sufficient accuracy.

Spatial Interpolated Lookup Tables (LUTs) Models for Ergodic Capacity of MIMO FSO Systems

We propose low complexity, adaptive multivariate precomputed B-spline and Barycentric Lagrange interpolation-based lookup table ( $ {B}^{2}$ LUT) models for the estimation of channel capacity of multiple-input-multiple-output free-space optical communication systems over generalized Malaga $( {\mathcal{ M}})$ -distributed atmospheric turbulence channels. The models require low memory for efficient operation and exploit precomputed weights to achieve fast and stable operation. The models can significantly reduce the size of lookup table, thereby reducing the computational cost. Similarly, the models can enhance the speed by up to 15 orders of magnitude and beyond without loss of fidelity compared with the current analytical models.

Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

In modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty. A part of this area overhead comes from the increased amount of configuration memory which rises exponentially as the LUT size increases. In this paper, we first present a detailed analysis of a previously proposed FPGA architecture which allows sharing of LUTs memory (SRAM) tables among NPN-equivalent functions, to reduce the area as well as the number of configuration bits. We then propose several methods to improve the existing architecture. A new clustering technique has been proposed which packs NPN-equivalent functions together inside a Configurable Logic Block (CLB). We also make use of a recently proposed high performance Boolean matching algorithm to perform NPN classification. To enhance area savings further, we evaluate the feasibility of more than two LUTs sharing the same SRAM table. Consequently, this work explores the SRAM table sharing approach for a range of LUT sizes (4–7), while varying the cluster sizes (4–16). Experimental results on MCNC benchmark circuits set show an overall area reduction of ~7% while maintaining the same critical path delay.

Fast and Parallel AAC Decoder Architecture for a Digital Radio Mondiale 30 Receiver

An embedded real-time indexing engine for live radio stations requires a high-speed parallel advanced audio coding (AAC) decoder architecture to decode hundreds of compressed audio streams broadcast in the digital radio mondiale band. Several AAC hardware core units must be integrated into a single chip and synchronized with a global controller to achieve such high performance. This paper proposes a new parallel AAC decoder architecture to address this challenge. The proposed architecture includes multiple AAC decoder core units, each of which achieves a speed-up by a factor of 2 compared with the existing AAC decoder core units while using optimal logic resources. The proposed architecture overcomes several challenges faced by existing architectures. The Huffman decoder module decodes one word per clock cycle regardless of word length, and a smaller lookup table size is achieved for the inverse quantization module. The inverse modified discrete cosine transform architecture is fully pipelined, and the resource sharing technique is used to reduce the logic area. An initial prototype is implemented on an FPGA platform.

Design Tradeoffs and Predistortion of Digital Cartesian RF-Power-DAC Transmitters

Digital RF transmitter architectures offer several advantages over conventional analog transmitters, including reduced area, reconfigurability, compatibility with scaling, and the ability to use highly efficient switching-class power amplifiers (PAs). However, the nonlinear transfer functions from the switch conductance to the output RF amplitude and phase of these switching-class PAs and the inherent interaction between I and Q paths in digital Cartesian architectures necessitate the use of 2-D digital predistortion (2D-DPD) for linearization. In this brief, we discuss the 2D-DPD of a class $E/F_{\mathrm{odd}}$ PA-based Cartesian RF-power-digital to analog converter (DAC) transmitter. The effects of parameters associated with the 2D-DPD such as the rotation of the static nonlinearity constellation, size of predistortion look-up tables (LUTs), and interpolation technique on system performance metrics such as error vector magnitude (EVM) and output power are discussed. We also investigate design tradeoffs related to output power, efficiency, and the effective number of bits in such transmitters. This brief is supported by measurement results from a watt-level 2.4-GHz 9-b Cartesian RF-power-DAC transmitter implemented in 65-nm CMOS.

$\alpha$Route: Routing on Names

One of the crucial building blocks for Information Centric Networking (ICN) is a name based routing scheme that can route directly on content names instead of IP addresses. However, moving the address space from IP addresses to content names brings the scalability issues to a whole new level, due to two reasons. First, name aggregation is not as trivial a task as the IP address aggregation in BGP routing. Second, the number of addressable contents in the Internet is several orders of magnitude higher than the number of IP addresses. With the current size of the Internet, name based, anycast routing is very challenging specially when routing efficiency is of prime importance. We propose a name-based routing scheme $\alpha$ Route for ICN that offers efficient bandwidth usage, guaranteed content lookup and scalable routing table size. $\alpha$ Route consists of two components: an alphanumeric Distributed Hash Table (DHT) and an overlay to underlay (Internet topology) mapping algorithm. Simulation results show that $\alpha$ Route performs significantly better than Content Centric Network (CCN) in terms of network bandwidth usage, lookup latency and load balancing.