Lookup Table Implementation Research Articles

Software performance characterisation of block cipher structures using S-boxes and linear mappings

A new framework is presented for evaluating the performance characteristics of block cipher structures composed of S-boxes and maximum distance separable (MDS) mappings. In particular, a novel performance metric is introduced and applied to nested substitution-permutation networks and Feistel networks with round functions composed of S-boxes and MDS mappings. Within each cipher structure, many cases are considered based on two types of S-boxes (4×4 and 8×8) and parameterised MDS mappings. In the study of each case, the performance is analysed based on a table lookup implementation. Although this implementation method is the typical approach used for software realisation, it may also be applicable to hardware realisation in some instances. Cipher security, in the form of resistance to differential and linear attacks, is applied as a basis which is used to normalise the performance in the analysis. Because the discussed structures are similar to many existing ciphers such as AES and Camellia, the analysis provides a meaningful mechanism for seeking efficient ciphers through a wide comparison of security, performance, and implementation methods.

Noise-predictive maximum likelihood (NPML) detection

Sequence detectors for the digital magnetic recording channel that are based on noise-predictive partial-response equalization are described. Called Noise-Predictive Maximum Likelihood (NPML) detectors, they arise by imbedding a noise prediction/whitening process into the branch metric computation of a Viterbi detector. NPML detectors can be realized in a form that allows RAM table look-up implementation of the imbedded feedback. Alternatively, the noise prediction/whitening mechanism can be implemented as an infinite impulse response (IIR) filter. For a Lorentzian channel with operating points in the range 0.5<PW50/T<3.5, IIR predictors with at most two zeros and two poles offer the best possible performance. Simulation results obtained for Lorentzian channels show that a judicious tradeoff between performance and state complexity leads to practical schemes offering substantial performance gains over both PRML and extended PRML detectors. An important practical advantage of the family of NPML detectors is that they can be conveniently integrated into existing PRML architectures.

Fast base extension and precise scaling in RNS for look-up table implementations

Both base extension and scaling are fundamental operations in residue computing and several techniques have been proposed previously for their efficient implementation. Using look-up tables, the best result (log/sub 2/ n table took-up cycles, where n is the number of residue moduli in the system) has been obtained by using the Chinese remainder theorem (CRT) at the expenses of a redundant representation of the numbers and of an approximated scaling. The CRT approach is reconsidered and it is shown that the same average time performances (log/sub 2/ n lookup cycles) can be achieved without any redundancy and with a precise result for scaling.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Time optimal mixed radix conversion for residue number applications

A new method is proposed for converting residue integers into a mixed radix notation. The method is based upon a modified formulation of the Chinese Remainder Theorem, and permits both conventional logic and look-up table implementations. Moreover, it represents the first method enabling optimal, residue-to-weighted system, asymptotic conversion time. To prove this, a constructive VLSI design has been devised, exhibiting time O(logs), where s is the total number of input bits. If compared with the existing mixed radix converting techniques, the method proposed considerably enhances the conversion time. To conclude, it is shown that, at the present state of the technology, practical ECL IC's implementations achieve 35-40 ns conversion times with RAMs and 60-70 ns with logic circuity for dynamic ranges up to 300 bits

Implementation of dynamic look-up tables

Look-up tables are used extensively in telecommunications networks in such areas as multiplexing, switching, routing and reassembly. There are also many applications involving look-up tables outside the field of telecommunications, such as electronic dictionaries and database search algorithms. Essentially, look-up tables map sets of input numbers onto arbitrary sets of output numbers. The paper discusses two new methods for the design of high speed, dynamic look-up tables and compares them with other common look-up table implementations.

Residue multipliers using factored decomposition

A technique for residue multiplication is described where the modulus is a non-prime integer. If the modulus m can be decomposed into two or more relatively prime factors, then multiplication can be done as a set of concurrent multiplication operations using the relatively prime factors as moduli. If a factor is prime, then multiplication is performed with an index calculus technique, otherwise a direct table look-up is used. An all ROM table look-up implementation of this technique is considered and a specific example is given for a modulo-28 multiplier. Hardware requirements for non-prime moduli up to 1024 are calculated and analyzed and compared with those for prime moduli of similar magnitude. Finally, an extension of the decomposition technique is discussed which allows further levels of modulus decomposition.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Enumerable multitrack (d, k) block codes

Multitrack run-length-limited (d, k) modulation codes were recently introduced as a method to increase storage densities in magnetic and optical recording systems. These codes are a generalization of the usual run-length-limited (d, k) codes and provide for increased storage density by relaxing the k-constraint and encoding multiple tracks in parallel. This paper introduces a method to construct multitrack (d, k) block codes which are implemented via an enumeration scheme based on the trellis description of the (d, k) constraints. This implementation results in memory requirements which increase only linearly with block length as opposed to the exponential increases arising from look-up table implementations of block codes. >

A failure detection method for integrated voice/data packet networks

A failure detection strategy at the data-link layer, implementable between frame-relay network nodes, is described for integrated voice/data packet networks. This strategy makes it possible to respond to link failures early enough to maintain data-session continuity. A simple, two-phase approach is proposed. In the first phase, the presence of a bit error rate violation along the packet link during short, fixed-length time segments is determined. In the second phase, the failure decision is made on the basis of a sequential algorithm. A simple table lookup implementation of the algorithm that requires no real-time computation is described. >

Lower bounds for VLSI implementation of residue number system architectures

Since the number of components that can fit on a single chip is large and rapidly growing, the asymptotic analysis and computational complexity have become applicable to the VLSI systems. We propose a model of computation devoted to VLSI structures based on Residue Number System (RNS). The developed model employs the ‘cut theorem’ which has been used by most of the abstract VLSI models. It is not as general as other reported models, but it gives tighter lower bounds and more accurate measures of performance for RNS structures. This computational model relates the area and time complexities with the inherent properties of RNS, the moduli size and the dynamic range. The model supports the look-up table implementation approach and it is technology-independent.

New Realization of DFT Applied to CCITT No. 5 Telephone Signaling System

This paper describes a digital multifrequency signal receiver based on the discrete Fourier transform (DFT) principle. The new lookup table implementation for fast multiplication of an input PCM sample and a kernel sample leads to simple hardware for the operation of 128 time-multiplexed channels of the CCIT No. 5 line signal receiver. Overlap operation and guard logics are also employed to meet the signaling system requirements.

A Measure of Computational Work

The computational work of a process is measured in terms of the information in a memory for its table-lookup implementation. This measure is applied first to simple logical and arithmetic processes, and then more complicated processes comprising organizations (called synergisms) of several subprocesses. The computational advantages of Cartesian, compositional, and sequential synergisms are investigated and illustrated by means of the work measure. The relation between the work of a process and the work capacity of a facility on which it is implemented is examined, and a concept of efficiency of implementations is formulated. A few areas for further investigation are outlined.