Lookup Table Circuit Research Articles

Design and Implementation of DDS Signal Generator Based on FPGA

With the rapid development of semiconductor technology, the digital circuit of the control chip gradually replaces the analog circuit of the traditional signal generator, which improves the performance of the signal generator and reduces the cost of research, development and production. This paper proposes a design scheme that takes FPGA chip as the control center. The signal generator system mainly includes DAC module, FPGA module and key module. The system uses Verilog language to develop the sine wave digital signal generation and key switching frequency control logic circuit on FPGA. The frequency control word circuit in the FPGA module provides multiple frequency sine wave selection, and the look-up table circuit realizes the reading of different phases by controlling the read address of the ROM. The 14-bit high-speed DAC module converts the digital signals sent by FPGA into analog signals. The DAC module integrates low-pass filter processing to increase the smoothness of the signal. After testing, the system meets the design requirements.

Design of an energy-efficient nonvolatile lookup table circuit using active-load-localized circuitry with self-terminated writing/reading

An energy-efficient nonvolatile lookup table (LUT) circuit, where both write and read currents are automatically terminated if desired write/read operations are completed, is proposed. The use of self-terminated writing makes it possible to cut off wasted write current by continuously monitoring voltage transitions owing to the resistance change in the storage element. In addition, wasted read current can be cut off by utilizing the voltage drop in active-load-localized circuitry as a read completion signal. In fact, the proposed 6-input LUT circuit reduces 59% of write energy and 47% read energy with only 5% of hardware overhead compared with those of a conventional circuit style under a 45 nm CMOS technology.

Design of a cost-efficient controller for realizing a data-shift-minimized nonvolatile field-programmable gate array

Data shifting occupies an important function as a lookup table (LUT) circuit in a field-programmable gate array (FPGA), while its write energy is critical in magnetic tunnel junction (MTJ)-based nonvolatile FPGAs (NV-FPGAs). Minimizing data shifting by only permuting the order of the output data stream from the stored data in an LUT is an energy-efficient approach to solving the above problem. However, a concrete and energy-efficient controller design has not been discussed. In this paper, we propose a cost-efficient controller for realizing data-shift-minimized MTJ-based NV-FPGA. The hardware overhead in the proposed controller is significantly reduced by sharing the common functionality. In fact, the hardware overhead of the proposed controller is 68% smaller that of without hardware sharing. It is also demonstrated that the power consumption of the 512 bit shift register using MTJ-based LUT circuits with proposed controller is 88% smaller than that of SRAM-based one.

Design of a highly reliable, high-speed MTJ-based lookup table circuit using fractured logic-in-memory structure

A magnetic tunnel junction-based lookup table (LUT) circuit based on the fractured logic-in-memory structure, which can operate one multi-input LUT circuit as well as several LUT circuits with a smaller number of inputs with a compact circuitry, is proposed. Since a complex NMOS tree for performing a combinational logic function is separated from a read-current path, the resistance of the series-connected NMOS transistors is greatly reduced, which makes it possible to enhance the read margin and to reduce the circuit delay. The read margin can also be improved by increasing the gate widths of the NMOS transistors that are shared among several memory cells with a small area overhead. In fact, the read margin of the proposed six-input LUT circuits is 30.9% higher compared with that of a conventional circuitry. The circuit delay of the proposed 6-input LUT circuit is 69% smaller the that of the conventional circuitry.

Design of the RRAM-Based Polymorphic Look-Up Table Scheme

The polymorphic gates are the circuit cells that deliver different functions with the different external input, supply voltage or temperature. It is an effective method to resist the reverse engineering attacks, for the attackers cannot distinguish the correct function based on the netlist of the circuit. The researchers have found out that the RRAM based Look-Up Table (LUT) has higher performance and less area, comparing with the CMOS based counterparts. However, the attackers can tell the functions of the previous proposed RRAM based LUTs by measuring the resistance states of the RRAM cells. This work proposes an RRAM based polymorphic gate, which implements 16 basic logic functions with 8 RRAM cells in 4 working cycles. Furthermore, the multi-input LUT scheme is proposed based on the polymorphic gate. It is difficult for the attackers to distinguish the circuit function, because the function of the LUT is determined by the applied voltages and the resistance states of the RRAM devices, and the n-input LUT circuit is implemented with the constant area regardless of the number of inputs.

Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices

A circuit optimization technique of nonvolatile logic-in-memory (NVLIM)-based lookup table (LUT) circuits in conjunction with magnetic-tunnel junction (MTJ) devices is proposed. Three important points should be considered for the circuit optimization technique of the NVLIM-based LUT circuit. One is optimizing DC and transient characteristics of the read current path, another is minimizing the effect of capacitance of both read-access transistors and write-access transistors, the other is how to design the selector circuit. As a typical example, the NVLIM-based LUT circuits is designed using 55 nm CMOS technology with two types of MTJ devices; the output delay, power and area of the circuit are evaluated. As a result, the output delay in the NVLIM-based 6-input LUT circuit is reduced by 47% compared to that of conventional SRAM-based implementation with 27% lower active power consumption as well as 67% of area reduction.

Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting

A magnetic-tunnel-junction (MTJ)-oriented nonvolatile lookup table (LUT) circuit, in which a low-power data-shift function is performed by minimizing the number of write operations in MTJ devices is proposed. The permutation of the configuration memory cell for read/write access is performed as opposed to conventional direct data shifting to minimize the number of write operations, which results in significant write energy savings in the data-shift function. Moreover, the hardware cost of the proposed LUT circuit is small since the selector is shared between read access and write access. In fact, the power consumption in the data-shift function and the transistor count are reduced by 82 and 52%, respectively, compared with those in a conventional static random-access memory-based implementation using a 90 nm CMOS technology.

A Compact Memristor-CMOS Hybrid Look-Up-Table Design and Potential Application in FPGA

Due to the conventional look-up-table (LUT) using the static random access memory (SRAM) cell, field programmable gate arrays (FPGAs) almost reach the limitation in term of the density, speed, and configuration overhead. This paper proposes an improved memristor-based LUT (MLUT) circuit which is compatible with the mainstream LUT circuit in FPGA. Any arbitrary combined logic functions can be implemented in the MLUT through specific configurations. Then the MLUT shows superior advantages over the conventional LUT such as smaller area overhead and fewer data transmission. As a case study, a one-bit full adder is simulated to verify that the design is of practice in PSPICE. Moreover, the adder can be cascaded into multibit full adder demonstrating competitiveness against the conventional configurable logic block in FPGA technology. MLUT can be a candidate to replace the conventional SRAM-based LUT and further improves the performance of FPGAs.

Radiation-hardened MRAM-based LUT for non-volatile FPGA soft error mitigation with multi-node upset tolerance

In this paper, we have developed a radiation-hardened non-volatile lookup table (LUT) circuit utilizing spin Hall effect (SHE)-magnetic random access memory (MRAM) devices. The design is motivated by modeling the effect of radiation particles striking hybrid complementary metal oxide semiconductor/spin based circuits, and the resistive behavior of SHE-MRAM devices via established and precise physics equations. The models developed are leveraged in the SPICE circuit simulator to verify the functionality of the proposed design. The proposed hardening technique is based on using feedback transistors, as well as increasing the radiation capacity of the sensitive nodes. Simulation results show that our proposed LUT circuit can achieve multiple node upset (MNU) tolerance with more than 38% and 60% power-delay product improvement as well as 26% and 50% reduction in device count compared to the previous energy-efficient radiation-hardened LUT designs. Finally, we have performed a process variation analysis showing that the MNU immunity of our proposed circuit is realized at the cost of increased susceptibility to transistor and MRAM variations compared to an unprotected LUT design.

Design of a variation‐resilient single‐ended non‐volatile six‐input lookup table circuit with a redundant‐magnetic tunnel junction‐based active load for smart Internet‐of‐things applications

A variation-resilient single-ended six-input lookup table circuit, which makes it possible to implement any arbitrary six-input logic gates, is proposed. Since operating point is optimally tuned by the redundant magnetic tunnel junction devices after chip fabrication, adequate p-channel metal-oxide semiconductor (PMOS) feedback can be performed, which results in variation-resilient, energy-efficient operation. In fact, the energy consumption of the proposed circuit is 66% smaller than that of the conventional single-ended circuit.

Single event double node upset tolerance in MOS/spintronic sequential and combinational logic circuits

Spin-transfer torque random access memory (STT-RAM) is an emerging storage technology that is considered widely thanks to its attractive features such as low power consumption, nonvolatility, scalability and high density. STT-RAMs are comprised of a hybrid design of CMOS and spintronic units. Magnetic tunnel junction (MTJ) as the basic element of such hybrid technology is inherently robust against radiation induced faults. However, the peripheral CMOS component for sensing the resistance of the MTJs are prone to be affected by energetic particles. This paper proposes low power, nonvolatile and radiation hardened latch and lookup table circuits based on hybrid CMOS/MTJ technology for the next generation integrated circuit devices. Simulation results revealed that, the proposed circuits are fully robust against single event upsets (SEU) and also single event double node upsets (SEDU) that are of the main reliability challenging issues in current sub-nanometer CMOS technologies.

Power Optimization of Configurable Logic Block in FPGA via Controlling Logic State of Virtual Ground Voltage

In this article, power optimization is investigated in Configurable Logic Block (CLB) of Field Programmable Gate Array (FPGA) for 65nm technology via controlling Virtual Ground Voltage (Vssv) state that follows Power-Gated standard. Initially different Configurable Logic Block are designed through the logic gates and then expanded via adding Look Up Table circuit (LUT) in inputs; afterwards, the samples of Configurable Logic blocks are investigated in two logic states of Virtual Ground Voltage =0 and Virtual Ground Voltage =1 regarding the power dissipation; whereas 100µs is time reference for simulation of time controller of Virtual Ground Voltage function. First Configurable Logic Block are kept at logic state of Virtual Ground Voltage =1(power gated) for 10µs out of 100µs and remaining time at logic state of Virtual Ground Voltage =0 (power not gated); then the simulation test is repeated up to 50µs in 5 steps for each Configurable Logic Block sample. Finally the result shows that reduction being at logic state of Virtual Ground Voltage =0 in a constant time period has linear effect on decreasing average power. With the Configurable Logic Block in operation for 50% of the total time in Virtual Ground Voltage =1 logic state, the average power reduces up to 49% in the best case scenario. Meanwhile the Configurable Logic Block can still preserve its logic state.

Energy-Efficient Nonvolatile Reconfigurable Logic using Spin Hall Effect-based Lookup Tables

In this paper, we leverage magnetic tunnel junction (MTJ) devices to design an energy-efficient nonvolatile lookup table (LUT), which utilizes a spin Hall effect (SHE) assisted switching approach for MTJ storage cells. SHE–MTJ characteristics are modeled in Verilog-A based on precise physical equations. Functionality of the proposed SHE–MTJ-based LUT is validated using SPICE simulation. Our proposed SHE—MTJ-based LUT (SHE–LUT) is compared with the most energy-efficient MTJ-based LUT circuits. The obtained results show more than 6%, 37%, and 67% improvement over three previous MTJ-based designs in term of read energy consumption. Moreover, the reconfiguration delay and energy of the proposed design is compared with that of the MTJ-based LUTs which utilize the spin transfer torque (STT) switching approach for reconfiguration. The results exhibit that SHE–LUT can operate at 78% higher clock frequency while achieving at least 21% improvement in terms of reconfiguration energy consumption. The operation-specific clocking mechanisms for managing the SHE–LUT operations are introduced along with detailed analyses concerning tradeoffs. Results are extended to design a 6-input fracturable LUT using SHE–MTJs.

Six-input lookup table circuit with 62% fewer transistors using nonvolatile logic-in-memory architecture with series/parallel-connected magnetic tunnel junctions

A compact 6-input lookup table (LUT) circuit using nonvolatile logic-in-memory (LIM) architecture with series/parallel-connected magnetic tunnel junction (MTJ) devices is proposed for a standby-power-free field-programmable gate array. Series/parallel connections of MTJ devices make it possible not only to reduce the effect of resistance variation, but also to enhance the programmability of resistance values, which achieves a sufficient sensing margin even when process variation is serious in the recent nanometer-scaled VLSI. Moreover, the additional MTJ devices do not increase the effective chip area because the configuration circuit using MTJ devices is simplified and these devices are stacked over the CMOS plane. As a result, the transistor counts of the proposed circuit are reduced by 62% in comparison with those of a conventional nonvolatile LUT circuit where CMOS-only-based volatile static random access memory cell circuits are replaced by MTJ-based nonvolatile ones.