Longer Gate Length Research Articles

Simulation study of total ionizing dose effect of gamma radiation on 15 nm bulk FinFET

FinFET is a new mainstream semiconductor device that is widely used in space applications. This paper studies the effects of radiation damage typically encountered in space applications by simulating the effects of total ionizing dose (TID) from 0 to 1 Mrad on a 15 nm n-type bulk FinFET. In particular we have simulated the effects of radiation damage on the transfer characteristic curve, threshold voltage and subthreshold swing of the FinFET. We have also varied some device process parameters such as gate length, fin width and fin height in order to assess their impact on the device susceptibility to radiation damage and our results show that the device structure with longer gate length, wider fin width and taller fin height have better performance. In addition, the higher channel doping concentration, the use of SiO2 in the gate, and the low device operating temperature can also effectively reduce the TID effects.

Trapping effects on AlGaN/GaN HEMT characteristics

This paper describes device simulation studies of surface and buffer trapping effects on static I-V, output-admittance (Y22), and transient characteristics of AlGaN/GaN HEMTs. The TCAD simulation model considering surface donors at EC − 0.5 eV and buffer traps at EC − 0.47 eV have been used to quantitatively reproduce the measured DC, Y22 frequency dispersion, gate-lag (GL) and drain-lag (DL) transients of AlGaN/GaN HEMT with 0.25 µm gate length. Moreover, simulated GL and DL transient responses of AlGaN/GaN HEMT with a longer gate length (0.5 µm) are validated with the reported experimental results. The impact of barrier trap at EC − 0.45 eV on the HEMT properties is also explored. It is shown that by matching simulation results with experimental data, it is possible to identify the trap (surface or buffer) responsible for a particular trapping induced degradation as well as its concentration and capture cross-section.

Comprehensive Investigation on Electrical Properties of nLDMOS and pLDMOS Under Mechanical Strain

In this paper, we have comprehensively studied the performance boosts of both nLDMOS and pLDMOS under the mechanical strain. The electrical properties of LDMOS under the uniaxial tensile and compressive strains along the channel direction are examined thoroughly. We find that the uniaxial tensile strain benefits the nLDMOS, and the uniaxial compressive strain benefits the pLDMOS. Because the mechanical strain affects carriers' transportation in bulk Si and inverted channel distinctly, the strain effects are strongly correlated with the gate voltage, drain voltage, and devices' dimensions. It is found that the LDMOS with the longer gate length is more preferred for the strain. The piezoresistance coefficients of both nLDMOS and pLDMOS under the uniaxial strain are evaluated for the first time. It is also shown that the mechanical strain can enhance the drain current without the degradation of the breakdown voltage, which suggests a downshift of the ON-resistance versus breakdown voltage curve.

Quantum Transport Study of Si Ultrathin-Body Double-Gate pMOSFETs: <inline-formula> <tex-math notation="LaTeX">${I}$ </tex-math> </inline-formula>–<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math> </inline-formula>, <inline-formula> <tex-math notation="LaTeX">${C}$ </tex-math> </inline-formula>–<inline-formula> <tex-math notation="LaTeX">${V}$ </tex-math> </inline-formula>, Energy Delay, and Parasitic Effects

A comprehensive quantum transport study of ultrathin-body silicon double-gate pMOSFETs with gate length ${L}_{\textsf {g}}= \textsf {14}$ , 10, and 7 nm is performed by in-house developed nonequilibrium Green’s function solver employing the six-band ${k} \cdot {p}$ Hamiltonian. The effects of channel length, body thickness, as well as confinement and transport crystal orientations are studied systematically. Both ${I}$ – ${V}$ and ${C}$ – ${V}$ characteristics are analyzed in this paper. Furthermore, the CMOS performance benchmarking results, such as switching delay, energy consumption, and their product, are calculated with the influence of parasitic resistances and capacitances treated in an appropriate way. It is found that the crystal orientation effect on drive current is significant at both long and short channel lengths, while its effect on effective capacitance is more observable at ${L}_{\textsf {g}} = \textsf {7}$ nm. The drive current at ${L}_{\textsf {g}} = \textsf {14}$ nm and ${L}_{\textsf {g}} = \textsf {7}$ nm can be well explained by average ballistic hole velocity and source-to-drain tunneling ratio, respectively. Meanwhile, the effective capacitance is not only determined by the density of states but also affected by the distribution of holes in the confined direction. Both intrinsic and extrinsic performance assessments suggest that (001)/[100] and (110)/[001] are the optimal confinement/transport crystal orientation configurations at ${L}_{\textsf {g}}= \textsf {7}$ nm, while ${(}\textsf {110}{)}/[\overline {1}\textsf {10}]$ and ${(}\textsf {110})/[\overline {1}\textsf {11}]$ are the best choices at longer gate lengths. As ${L}_{\textsf {g}}$ shrinks, both intrinsic and extrinsic performances will be better at a scaled body thickness.

Effect of Polarization Coulomb Field Scattering on Parasitic Source Access Resistance and Extrinsic Transconductance in AlGaN/GaN Heterostructure FETs

With the measured parasitic source access resistance under a different forward gate–source current for the AlGaN/GaN heterostructure FETs (HFETs) with different device sizes, the variation of the measured parasitic source access resistance with the polarization charge distribution at the AlGaN/GaN interface was compared and analyzed. It is found that the variation of the parasitic source access resistance originates from the polarization Coulomb field (PCF) scattering, and the effect of PCF scattering on the parasitic source access resistance is more significant for the device with a longer gate length or a shorter gate–source distance. The behaviors of the measured extrinsic transconductance for the fabricated AlGaN/GaN HFETs confirm the effect of PCF scattering. The possibility is demonstrated to take advantage of this effect to improve the performance of AlGaN/GaN HFETs.

Scaling Length Theory of Double-Gate Interband Tunnel Field-Effect Transistors

A scaling theory of double-gate interband tunnel field-effect transistors (TFETs) using a physics-based 2-D analytical model is presented. Ignoring the mobile charge in the channel, the electrostatic potential profile and electric field are analytically solved, and the current is calculated by integrating the band-to-band tunneling generation rate over the volume of the device. The analytical model has excellent agreement with the numerical results obtained from a commercial simulator and atomistic nonequilibrium Green function simulations for both heterojunction and homojunction TFETs. The analytical model allows us to quantitatively extract the electrostatic scaling lengths in TFETs and compare the short-channel effect of TFETs with that of MOSFETs. We conclude that double-gate TFETs exhibit superior short-channel performance than their MOSFETs counterparts at a longer gate length (greater than four times the scaling length), but the scalability of the TFETs degrades at a faster rate than MOSFETs do at smaller gate lengths (less than four times the scaling length).

DC and RF Performance of AlN/GaN MOS-HEMTs

This paper reports the DC and RF characteristics of AlN/GaN MOS-HEMTs passivated with thin Al2O3 formed by thermal oxidation of evaporated aluminium. Extraction of the small-signal equivalent circuit is also described. Device fabrication involved wet etching of evaporated Al from the Ohmic contact regions prior to metal deposition. This approach yielded an average contact resistance of ∼0.76Ω.mm extracted from transmission line method (TLM) characterisation. Fabricated two-finger AlN/GaN MOS-HEMTs with 0.2µm gate length and 100µm gate width showed good gate control of drain currents up to a gate bias of 3V and achieved a maximum drain current, IDSmax of ∼1460mA/mm. The peak extrinsic transconductance, Gmax, of the device was ∼303mS/mm at VDS =4V. Current-gain cut-off frequency, fT, and maximum oscillation frequency, fMAX, of 50GHz and 40GHz, respectively, were extracted from S-parameter measurements. For longer gate length, LG =0.5µm, fT and fMAX were 20GHz and 30GHz, respectively. These results demonstrate the potential of AlN/GaN MOS-HEMTs for high power and high frequency applications.

Optimal Dual-$V_{T}$ Design in Sub-100-nm PD/SOI and Double-Gate Technologies

Dual-threshold-voltage (VT) CMOS is an effective way to reduce leakage power in high-performance very-large-scale-integration circuits. In this paper, we explore the technology design space for dual-threshold-voltage transistor design in deep-sub-100-nm technology nodes. We propose a technique of achieving high-VT (HVT) devices using thicker gate-sidewall offset spacers to increase the channel length without increasing the printed-gate length. The effectiveness of all the dual-VT technology options-increasing channel doping, increasing gate length, and proposed technique of increasing spacer thickness-is analyzed at transistor and basic logic gate level. Results on 65-nm partially depleted silicon-on-insulator and double-gate technologies indicate that the proposed technique yields lower dynamic power consumption and lower performance penalty compared with longer gate length and high body-doping devices. Our proposed technique, however, incurs extra fabrication mask similar to achieving HVT by increasing body doping.

Effects of phonon scattering on electron transport in double-gate MOSFETs

Current-voltage characteristics of double-gate silicon-on-insulator MOSFETs have been calculated within non-equilibrium Green’s function formalism including g-type, f-type, and acoustic phonon scatterings. Contribution of f-type phonons to the current reduction is smaller than that of g-type phonons. Effects of the phonon scatterings on the drain current at off-states are weaker than those at on-states. At off-states, phonon-assisted tunneling partially compensates a current loss due to scattering for shorter gate lengths, while polaronic current component appears for longer gate lengths.

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

The authors present a study on the layout dependence of the silicon-germanium source/drain (Si1-xGex S/D) technology. Experimental results on Si1-xGex S/D transistors with various active-area sizes and polylengths are combined with stress simulations. Two technologically important configurations are investigated: the nested transistor, where a polygate is surrounded by other gates, and isolated transistors, where the active area is completely surrounded by isolation oxide. The channel stress, caused by epitaxial Si1-xGex is reduced substantially when the active area is decreased from a large size towards typical values for advanced CMOS technology nodes. Nested transistors with longer gate lengths are more sensitive towards layout scaling than shorter gates. Increasing recess depth and germanium concentration gives larger channel stress, but does not change layout sensitivity. Increased lateral etching leads to higher stress, as well as to reduced layout sensitivity. In small-size transistors, there exists an optimal recess depth, beyond which the stress in the channel will not increase further. For isolated transistor structures, the interaction between Si1-x Gex and the isolating oxide can even lead to stress reduction when the recess depth is increased. When technology advances, active-area dimensions will be scaled together with gate lengths and widths. For typical sizes of advanced silicon CMOS Si1-xGe x S/D transistors, simulations indicate that the channel stress can be maintained in future technology nodes

Is Gate Line Edge Roughness a First-Order Issue in Affecting the Performance of Deep Sub-Micro Bulk MOSFET Devices?

An experimental study of the effects of gate line edge roughness (LER) on the electrical characteristics of bulk MOSFET devices was performed. Device simulation had previously predicted that gate LER causes off-state current to increase. In our experiments, gate LER was deliberately introduced in devices with 40 nm or longer physical gate length, and we found about 3X I/sub OFF/ increase (for 40 nm gate length) in the I/sub OFF/-I/sub ON/ plot. In our devices, Source/Drain (S/D) extensions are produced by implants self-aligned to gate edges. Simulation results indicate that what really matters is the roughness induced of the S/D to channel junctions by gate LER. Implantation scattering and dopant diffusion cause the S/D to channel junctions to be smoother than the gate edges. This will partially reduce the differences in the I/sub OFF/-I/sub ON/ curves caused by differing amounts of gate LER. By optimizing our process flows, we obtained a minimized gate LER (EdgeRMS<2 nm). We believe that the consequence of this minimized LER is secondary to the impact of other process variations across wafer for devices with 40 nm or longer gate length.

Short-channel AlGaN/GaN HEMTs with 70 nm T-gate

The authors have fabricated AlGaN/GaN HEMTs with gate-lengths down to 70 nm to investigate DC- and high frequency characteristics and the breakdown behaviour, respectively. Comparisons with HEMTS fabricated on the same wafer but with a longer gate-length (2µm) are presented as well. The 70 nm devices have a transconductance of ~155 mS/mm, fT is 43 GHz and fmax ~100 GHz. The breakdown voltage reaches 27 V at ID = 550 mA/mm.