Abstract

A comprehensive quantum transport study of ultrathin-body silicon double-gate pMOSFETs with gate length ${L}_{\textsf {g}}= \textsf {14}$ , 10, and 7 nm is performed by in-house developed nonequilibrium Green’s function solver employing the six-band ${k} \cdot {p}$ Hamiltonian. The effects of channel length, body thickness, as well as confinement and transport crystal orientations are studied systematically. Both ${I}$ – ${V}$ and ${C}$ – ${V}$ characteristics are analyzed in this paper. Furthermore, the CMOS performance benchmarking results, such as switching delay, energy consumption, and their product, are calculated with the influence of parasitic resistances and capacitances treated in an appropriate way. It is found that the crystal orientation effect on drive current is significant at both long and short channel lengths, while its effect on effective capacitance is more observable at ${L}_{\textsf {g}} = \textsf {7}$ nm. The drive current at ${L}_{\textsf {g}} = \textsf {14}$ nm and ${L}_{\textsf {g}} = \textsf {7}$ nm can be well explained by average ballistic hole velocity and source-to-drain tunneling ratio, respectively. Meanwhile, the effective capacitance is not only determined by the density of states but also affected by the distribution of holes in the confined direction. Both intrinsic and extrinsic performance assessments suggest that (001)/[100] and (110)/[001] are the optimal confinement/transport crystal orientation configurations at ${L}_{\textsf {g}}= \textsf {7}$ nm, while ${(}\textsf {110}{)}/[\overline {1}\textsf {10}]$ and ${(}\textsf {110})/[\overline {1}\textsf {11}]$ are the best choices at longer gate lengths. As ${L}_{\textsf {g}}$ shrinks, both intrinsic and extrinsic performances will be better at a scaled body thickness.

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