Log-MAP Algorithm Research Articles

Low Complexity Stopping Rule for Turbo Decoding: the Max-log Criterion

This paper presents a new stopping criterion for turbo decoding. It is based on the selection of the maximum log-alphas calculated by the log-MAP algorithm. The sum of these maximum alphas is compared with a threshold value. Then, a decision on the end of decoding is taken. Simulation results show that the max-log criterion offers the same performance as the sum-alpha and sum-log criteria, while maintaining the same complexity level. The max-log criterion uses only the max operator to select maximum alphas and a summation. Therefore, the proposed criterion is faster and offers lower complexity.

Concatenated turbo polar-convolutional codes based on soft cancellation algorithm

This paper presents the Parallel and Serial Concatenated Turbo Polar-Convolutional Codes (CTPCCs) to improve the performance of polar codes in the finite code length regime. Both proposed concatenated codes use the Systematic Polar Code (SPC) and Recursive Systematic Convolutional (RSC) code as constituent codes. The iterative decoding algorithms of the proposed systems consist of a Soft Cancellation (SCAN) decoder with a single internal iteration for the SPC and SOVA or LogMap decoder for the RSC code. The simulation results show that the performance of the Parallel Concatenated Turbo Polar-Convolutional Code (PCTPCC) at low signal-to-noise ratios (SNRs) is better than that of the Serial Concatenated Turbo Polar-Convolutional Code (SCTPCC) and also better than the performance of other Turbo Polar Codes (TPCs). At BER=10−2, the proposed PCTPCC with SOVA and LogMap algorithms has about 0.3 dB and 0.25 dB performance gains over the SCTPCC models, respectively. In the high SNR regions, the performance of the SCTPCC with the LogMap algorithm significantly outperforms that of other models. At BER=10−6, the proposed SCTPCC models with SOVA and LogMap algorithms outperform the PCTPCC model by gains of 0.3 dB and 0.25 dB, respectively. The PCTPCC model with the SOVA decoder is superior to other models in terms of complexity.

Research and Implementation of Turbo Coding Technology in High-Speed Underwater Acoustic OFDM Communication

It is demonstrated that the fully parallel turbo decoding algorithm can achieve an approximate error correction decoding performance when 36 iterations are used and when the log-map algorithm with 6 iterations is used. By comparison, it is shown that it can achieve much higher decoding rates than the log-map algorithm for various frame lengths of LTE standard turbo codes at the cost of higher hardware resource requirements. According to the fully parallel turbo decoding algorithm, this paper proposes a scheme for implementing a fully parallel turbo decoder on FPGA, detailing the overall structure and processing of the decoder hardware implementation, the design of the algorithm block processing unit, and the interleaving module. The performance of the decoder is tested by fixed-point simulation for different frame lengths of turbo coding in LTE standard, and it is proved that the fully parallel turbo decoder can be applied to turbo coding of various frame lengths. Both simulation and experimental results show that the distributed cancellation method and the joint estimation cancellation method have good results for both time-domain impulse noise and large-amplitude single frequency noise cancellation, while the joint estimation cancellation method of large-amplitude single frequency noise cancellation first has better performance.

An FPGA Implementation of the Log-MAP Algorithm for a Dirty Paper Coding CODEC

This work describes the log-MAP (BCJR) algorithm implementation of a close to capacity dirty paper coding CODEC. The CODEC consists of eight deep pipeline processors. It decodes blocks of 975 bits in 26.9 ms using less than 9.7% of low-cost FPGA (and no DSP blocks). Two pipelines, for alpha and beta, calculate the values of gamma (of the BCJR) to reduce the storage requirements. The final log-likelihood ratio (LLR) is calculated together with alpha, reusing intermediate results. The number of bits used by the different signals of the processor is easily configurable. It was set to six bits to the channel measure signals and eight bits to log of probability signals like alpha, beta, and others. The CODEC clock was 100 MHz. The achieved bit rate is 36.2 Kbps per CODEC, but multiple CODECs can be fit into a single chip. The CODEC is 3.49 dB from the channel capacity.

A state metrics compressed decoding technique for energy-efficient turbo decoder

In the energy resource-constrained wireless applications, turbo codes are frequently employed to guarantee reliable data communication. To both reduce the power dissipation of the turbo decoder and the probability of data frame retransmission in the physical layer, memory capacity reduced near optimal turbo decoder is of special importance from the perspective of practical implementation. In this regard, a state metrics compressed decoding technique is proposed. By inserting two modules in the conventional turbo decoding architecture, a smaller quantization scheme can be applied to the compressed state metrics. Furthermore, structure of the inserted modules is described in detail. We demonstrate that one or two rounds of compression/decompression are performed in most cases during the iterative decoding process. At the cost of limited dummy decoding complexity, the state metrics cache (SMC) capacity is reduced by 53.75%. Although the proposed technique is a lossy compression strategy, the introduced errors only have tiny negative influence on the decoding performance as compared with the optimal Log-MAP algorithm.

Improved Turbo Decoding With Multivariable Taylor Series Expansion

In this letter, a new method is proposed to approximate $n$ -input ( $n>2$ ) max* operation. Bi-variable Taylor series expansion, for the first time, is applied to approximate the correction term of $n$ -input ( $n>2$ ) max* operation. It avoids the recursive computation of bi-variable Jacobian logarithm. To improve the approximation performance, multiple expansion points are considered. The proposed method is evaluated for 3GPP LTE turbo codes. The simulation results show that the approximation with five expansion points, applied with scaling factor to extrinsic information, has performance degradation of 0.01 dB compared with radix-4 Log-MAP algorithm. Furthermore, the approximation with three expansion points will bring minor performance loss but almost the same computational complexity compared with five expansion points.

High performance gain demodulate system for hybrid fiber-coaxial

Gigabit capable of Hybrid Fiber-Coaxial (HFC) represented an increase. The goals of the next generation HFC system are to efficiently utilize the precious last 100m of the coaxial cable and to achieve a Gigabit transmission rate. This target demands higher requirements regarding the physical layer (PHY) throughput. Firstly, the PHY architecture of next generation HFC system is given in detail. Secondly, in order to meet challenging high PHY throughput, a class of Low Density Parity Check (LDPC) code is selected as the Forward Error Correction (FEC) scheme, the ultimate choice is made on the basis of system with a better bit error rate performance. Finally, this paper combines the characteristics of Gray code symbol mapping for Quadrature Amplitude Modulation (QAM) constellation to design a soft decision algorithm based on signal diversity. Especially in terms of power efficiency, this algorithm can beyond the performance of log-MAP algorithm.

Trimming Soft-Input Soft-Output Viterbi Algorithms

In the soft-input soft-output Viterbi algorithm (SOVA), the log-likelihood ratio (LLR) of each bit is determined by the minimum metric difference between the ML path and its competitive paths. This paper proposes to trim large metric differences in order to reduce the complexity of SOVA. By trimming the metric differences, only a small number of backtracking operations are carried out, while many LLRs may be omitted as the result of the lack of metric differences. By revealing the relationship among neighboring LLRs, the omitted LLRs are estimated from its neighoring LLRs as well as intrinsic information. The extrinsic information transfer chart analysis demonstrates that the proposed algorithm has similar convergence behavior as the Log-MAP algorithm, if the trimming factor $M$ is moderate. Other analyses verify that our approach provides good LLR quality with only at most $1/M$ backtracking operations of SOVA. Simulation results show that it outperforms SOVA and performs as well as its variants and the Log-MAP algorithm.

Enhancement the Performance of OFDM based on Multiwavelets Using Turbo Codes

In wireless communication systems, the main challenge is to provide a high data rate and reliable transmission over a frequency selective fading channel. Orthogonal Frequency Division Multiplexing (OFDM) is a very attractive technique for high data rate transmission with better bandwidth efficiency. In this paper, the effectiveness of turbo codes is utilized to develop a new approach for an OFDM system based on a Discrete Multiwavelet Critical-Sampling Transform (OFDM-DMWCST). The use of turbo coding in an OFDM-DMWCST system is useful in providing the desired performance at higher data rates. Two types of turbo codes were used in this work, i.e., Parallel Concatenated Convolutional Codes (PCCCs) and Serial Concatenated Convolutional Codes (SCCCs). In both types, the decoding is performed by the iterative decoding algorithm based on the log-MAP (Maximum A Posteriori) algorithm. The simulation results showed that, the turbo-coded OFDM-DMWCST system achieves large coding gain with lower Bit-Error-Rate (BER), therefore, offering a higher data rate under different channel conditions. In addition, the PCCCs offer better performance than SCCCs.

Performance of CO-OFDM system with RS-Turbo concatenated code

In this paper, the RS-Turbo concatenated code is applied to coherent optical orthogonal frequency division multiplexing (CO-OFDM) system. RS(186,166,8) and Turbo code with code rate of 1/2 are employed for RS-Turbo concatenated code. Two decoding algorithms, which are Max-Log-MAP algorithm and Log-MAP algorithm, are adopted for Turbo decoding, and the iteration Berlekamp-Massey (BM) algorithm is adopted for RS decoding. The simulation results show that the bit error rate (BER) performance of CO-OFDM system with RS-Turbo concatenated code is significantly improved at high optical signal to noise ratio (OSNR), and the iteration number is reduced compared with that of the Turbo coded system. Furthermore, when the Max-Log-MAP algorithm is adopted for Turbo decoding, the transmission distance of CO-OFDM system with RS-Turbo concatenated code can reach about 400 km without error, while that of the Turbo coded system can only reach about 240 km when BER is lower than 10-4 order of magnitude.

Low-Complexity Error Correction for ISO/IEC/IEEE 21451-5 Sensor and Actuator Networks

ISO/IEC/IEEE 21451-5 standard provide a wireless communication model to facilitate access of smart sensors and actuators to a network. However, the 21451-5 standard integrates different wireless communication protocols in a sensor network system, and the overall complexity is higher than traditional sensor networks. Moreover, 21451-5 sensor networks that used in industrial control systems require better bit-error rate performance, and error correction is one of the key issues for the sensor networks. To address these obstacles, the double binary convolutional turbo code is applied to the 21451-5 sensor and actuator networks, and a low-complexity decoding solution is proposed for the iterative decoding, in which the focus is concentrated on simplification of the multivariable max <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">*</sup> operator. In the implementation of a multivariable max <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">*</sup> operator, this research shows recursion of the Jacobian logarithm is not necessary, and the computational error is small. Furthermore, we propose to approximate the Jacobian logarithm with simple compare, shifting, and addition operations. Since errors introduced by recursion of the Jacobian logarithm are removed, decoding performance of the proposed solution is superior to that of the near optimal decoding algorithm, and only slightly reduced as compared with the Log-MAP algorithm. By hardware implementation analysis, decoding complexity related to the multivariable max <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">*</sup> operator is substantially reduced.

Performance Analysis and Implementation of SISO Iterative Receiver for SCCC

Serial concatenated convolutional codes (SCCC) have gained a great interest in recent years for outperforming PCCC at high SNR and lower error floor. In this paper, the BER performance of SCCC based on different decoding algorithm such as Log-MAP algorithm, Max-Log-MAP algorithm and improved Max-Log-MAP algorithm are investigated. In order to achieve a flexible high throughput, low complexity and multi-rate decoding process, some improved methods are proposed.

DESIGN AND IMPLEMENTATION OF TURBO CODER FOR LTE ON FPGA

Recent wireless communication standards such as 3GPP-LTE, WiMax, DVB-SH and HSPA incorporates turbo code for its excellent performance. This work provides an overview of the novel class of channel codes referred to as turbo codes, which have been shown to be capable of performing close to the Shannon Limit. It starts with a brief discussion on turbo encoding, and then move on to describing the form of the iterative decoder most commonly used to decode turbo codes. Here, Turbo decoder uses original MAP algorithm instead of using the approximated Max log-MAP algorithm thereby it reduces the number iterations to decode the transmitted information bits. This paper presents the FPGA (Field Programmable Gate Array) implementation simulation results for Turbo encoder and decoder structure for 3GPP-LTE standard.

Fast Demodulation Algorithm for Rate Compatible Modulation by Log-Map Principle

Rate compatible modulation (RCM) is a promising technology to smooth rate adaption of physical layer in wireless network, and do not request the accurate channel estimation. Since RCM demodulation adopt probability convolution operator in belief propagation algorithm, it greatly bring big computing complexity. This paper proposes fast demodulation algorithm for RCM by using log-map principle. First, we propose a new demodulation algorithm by a novel approach to convert arithmetic domain to logarithm domain. Then, we design a parallel manner that to find multivariable computation in Log-MAP algorithm for hard implementation. Finally, we evaluate fast demodulation algorithm by two evaluation metrics BER and goodput, respectively. Our analysis show that the demodulation complexity can be reduced about 90%. While experimental results show that the fast demodulation algorithm performance only has a marginal loss.

A Low Complexity Implementation in Hardware on Simplified Log-MAP Algorithm for T-TCM Decoding

A simplified decoding algorithm for turbo trellis-coded modulation (T-TCM) is proposed, which is easy to implement in hardware. The algorithm exploits a new piece-wise function to replace the logarithmic term of the Jacobian logarithm based on the MacLaurin Series. Simulation results show that the proposed algorithm can archive log-MAP-similar decoding performance with a much lower computational complexity. It can reduce about 40% of calculation in contrast to the improved MAX-Log-MAP.

Reduced complexity Log-MAP algorithm with Jensen inequality based non-recursive max∗ operator for turbo TCM decoding

In this paper, a reduced complexity Log-MAP algorithm based on a non-recursive approximation of the max∗ operator is presented and studied for turbo trellis-coded modulation (TTCM) systems. In the algorithm, denoted as AvN Log-MAP, the max∗ operation is generalized and performed on n≥2 arguments. The approximation is derived from the Jensen inequality. The non-recursive form of the max∗ calculations allows to achieve significant reduction in the decoding effort in comparison to the conventional Log-MAP algorithm. Bit-error rate performance simulation results for serial and parallel TTCM schemes in the additive white Gaussian noise and uncorrelated Rayleigh fading channels show that the AvN Log-MAP algorithm performs close to the Log-MAP. Performance and complexity comparisons of the AvN Log-MAP algorithm against the Log-MAP and several relevant reduced complexity turbo decoding algorithms proposed in the literature reveal, that it offers favorable low computational effort for the price of small performance degradation.

MC-CDMA based SDR for Next Generation Wireless Communication

Recent innovations in wireless technology have made a need to propose hybrid systems to achieve excellent data rates and performance. One such system is multi-carrier code division multiple access (MC-CDMA), a combination of direct sequence code division multiple access (DS-CDMA) and orthogonal frequency division multiplexing (OFDM) systems. It offers high data rate, flexible bandwidth allocation and enhanced performance to each user simultaneously. Owing to these advantages, this system is chosen to be interfaced with the physical layer of software defined radio (SDR). SDR is defined as a reprogrammable hardware that suits emerging standards of next generation wireless communication. In MC-CDMA system, when the orthogonality is not maintained in the OFDM part, it leads to multiple access interference (MAI). To overcome the effects of MAI and to reduce complex detection to a great extent, super orthogonal turbo codes is chosen for the system. In this paper, MC-CDMA based SDR system is constructed using super orthogonal turbo codes with log-MAP algorithm. The simulation results show that the performance is remarkable when compared to a turbo system using recursive systematic codes (RSC). The BER performance of both the systems is analyzed for different iterations.

Turbo Code Design and Implementation of High-Speed Parallel Decoder

Due to the high complexity Turbo decoding algorithm, implemented the hardware decoder logic of consumes more resources and storage resources, decode delay larger. In order to meet LTE systems, high reliable transmission of high data rate needs high speed Turbo decoder design faces enormous challenges. This topics select based on LTE system of parallel Turbo Code decoders hardware design and achieved as research direction, select FPGA(Virtex-6) as hardware design and achieved of platform, from Log-MAP algorithm of Sentinel of, and State measure value handed owned calculation in the of owned a of processing, and Diego generation decoding algorithm of parallel of, and parallel interwoven Manager design, and key path optimization technology, aspects analysis, design achieved has LTE Turbo Code high-speed parallel decoders. DOI: http://dx.doi.org/10.11591/telkomnika.v11i4.2393 Full Text: PDF

Research and Realization by FPGA of Turbo Codes

Turbo Code is a channel coding with excellent error-correcting performance in the condition of low noise-signal ratio.It has a superior decoding performance approaching the Shannon limit by adopting the random coding and decoding. This paper focuses on Turbo code and its implementation with FPGA and deeply analyzes the decoding theory and algorithm of Turbo code. Firstly, it analyzes the decoding theory of Turbo code. Then, it discusses key issues in the process of implementation with the most excellent and complicated Max—log—MAP algorithm. At last, it ends up with the Turbo encoder and decoding algorithm which hardware is successfully implemented finally.

Comments on "A New Parity-Check Stopping Criterion for Turbo Decoding"

A parity-check stopping (PCS) criterion for turbo decoding is proposed in , which shows its priority compared with the stopping criteria of Sign Change Ratio (SCR), Sign Difference Ratio (SDR), Cross Entropy (CE) and improved CE-based (Yu) method. But another well-known simple stopping criterion named Hard-Decision-Aided (HDA) criterion has not been compared in . In this letter, through analysis we show that using max-log-MAP algorithm, PCS is equivalent to HDA; while simulations demonstrate that using log-MAP algorithm, PCS has nearly the same performance as HDA.