Logic States Research Articles

Comparing Shor and Steane error correction using the Bacon-Shor code.

Quantum states decohere through interaction with the environment. Quantum error correction can preserve coherence through active feedback wherein quantum information is encoded into a logical state with a high degree of symmetry. Perturbations are detected by measuring the symmetries of the state and corrected by applying gates based on these measurements. To measure the symmetries without perturbing the data, ancillary quantum states are required. Shor error correction uses a separate quantum state for the measurement of each symmetry. Steane error correction maps the perturbations onto a logical ancilla qubit, which is then measured to check several symmetries simultaneously. We experimentally compare Shor and Steane correction of bit flip errors using the Bacon-Shor code implemented in a chain of 23 trapped atomic ions. We find that the Steane method produces fewer errors after a single round of error correction and less disturbance to the data qubits without error correction.

Gate control of superconducting current: Mechanisms, parameters, and technological potential

In conventional metal-oxide semiconductor (CMOS) electronics, the logic state of a device is set by a gate voltage (VG). The superconducting equivalent of such effect had remained unknown until it was recently shown that a VG can tune the superconducting current (supercurrent) flowing through a nanoconstriction in a superconductor. This gate-controlled supercurrent (GCS) can lead to superconducting logics like CMOS logics, but with lower energy dissipation. The physical mechanism underlying the GCS, however, remains under debate. In this review article, we illustrate the main mechanisms proposed for the GCS, and the material and device parameters that mostly affect it based on the evidence reported. We conclude that different mechanisms are at play in the different studies reported so far. We then outline studies that can help answer open questions on the effect and achieve control over it, which is key for applications. We finally give insights into the impact that the GCS can have toward high-performance computing with low-energy dissipation and quantum technologies.

Research Data Management in German Academia from a Multiple Logic Perspective

The requirements for research data management (RDM) have increased. Due to academia’s neoliberalization, however, researchers already face a high workload within a hypercompetitive environment. The demand to integrate RDM as an additional task into academics’ day-today actions seems to be quixotic. To deepen our understanding of early career researchers’ (ECRs) daily work arbitrage, we need to know more about their behavior, actions, and decisions in relation to RDM. Drawing on a multiple institutional logics perspective at the micro-level, we conducted 40 semistructured interviews at German higher education institutions (HEIs) to investigate how ECRs respond to institutional logics in the context of RDM. Our findings revealed three profiles – the conformist, the waverer, and the resister – that make use of different response strategies to the state, market, professional, and community logic. We contribute to institutional logic research at the micro-level and, in addition, broaden prior research on HEIs and RDM by taking neoliberal academia into account.

Institutional logics and organizational green transformation: Evidence from the agricultural industry in emerging economies

While the agricultural green transformation has garnered significant attention on the political stage as a crucial strategy for climate change mitigation and sustainable development, there remains a notable gap in our understanding of the prevailing logics that shape organizational decisions on this change in emerging economies. Drawing on the institutional logics perspective, this study explores the impact of state logic (manifested through green credit policy) and market logic (manifested through analyst attention) on agriculture-related firms' (ARFs') green transformation, as well as the moderating effects of organizational transparency and environmental, social, and governance (ESG) level. Using longitudinal data on 201 publicly listed ARFs in China from 2008 to 2020, we find that both state and market logics exert unique effects on facilitating the green transformation of ARFs. More notably, a complementarity between the two logics in offering value for ARFs’ green transformation is revealed. This complementary effect becomes more pronounced for organizations with a higher level of transparency or a superior ESG profile. Our study contributes to the neo-institutional perspective of organizational green transformation, a better understanding of conflicting institutional logics in emerging economies, and research on agricultural sustainability.

Reducing the error rate of a superconducting logical qubit using analog readout information

Quantum error correction enables the preservation of logical qubits with a lower logical error rate than the physical error rate, with performance depending on the decoding method. Traditional decoding approaches rely on the binarization (“hardening”) of readout data, thereby ignoring valuable information embedded in the analog (“soft”) readout signal. We present experimental results showcasing the advantages of incorporating soft information into the decoding process of a distance-3 (d=3) bit-flip surface code with flux-tunable transmons. We encode each of the 16 computational states that make up the logical state |0L⟩, and protect them against bit-flip errors by performing repeated Z-basis stabilizer measurements. To infer the logical fidelity for the |0L⟩ state, we average across the 16 computational states and employ two decoding strategies: minimum-weight perfect matching and a recurrent neural network. Our results show a reduction of up to 6.8% in the extracted logical error rate with the use of soft information. Decoding with soft information is widely applicable, independent of the physical qubit platform, and could allow for shorter readout durations, further minimizing logical error rates. Published by the American Physical Society 2024

Optimization of Decoder Priors for Accurate Quantum Error Correction.

Accurate decoding of quantum error-correcting codes is a crucial ingredient in protecting quantum information from decoherence. It requires characterizing the error channels corrupting the logical quantum state and providing this information as a prior to the decoder. We introduce a reinforcement learning inspired method for calibrating these priors that aims to minimize the logical error rate. Our method significantly improves the decoding accuracy in repetition and surface code memory experiments executed on Google's Sycamore processor, outperforming the leading decoder-agnostic method by 16% and 3.3%, respectively. This calibration approach will serve as an important tool for maximizing the performance of both near-term and future error-corrected quantum devices.

Investigation of the TaOx unipolar switching memory on high efficiency computing

Memristor has shown great potential application for data storage, neuromorphic computing chip, and memory logic, but its bi-directional operation from setting in positive bias voltage region to resetting in a negative bias voltage region would introduce a complex control circuit. Herein, a memristor with the structure of Au/TaOx/F-doped SnO2 presents unipolar switching behavior, enabling the memristor to operate the set and reset processing in a single voltage direction. By comparison with bipolar switching memristor, using this unipolar switching memristor to operate the logic expression of the letter “D” based on American standard code for information interchange (ASCII) can reduce power consumption by 55.56% while switching the logic state from “0” to “1” and then back to “0” can save up to 48% of power consumption. This work provides a feasible method for the low power consumption computing as well as a road to simplify circuit design.

Core-shell architecture and channel suppression: unleashing the potential of SC_RCS_DGJLFET

In this investigation, a suppressed channel-rectangular core–shell double gate junctionless field effect transistor (SC_RCS_DGJLFET) is simulated to enhance the junctionless device’s performance. This study leverages a core–shell architecture and channel suppression technique to improve the gate controllability over the channel region which helps in substantial depletion of the shells in the OFF state of the device. When compared to conventional double gate JLFETs (C_DGJLFET) and rectangular core–shell double gate JLFETs (RCS_DGJLFET), the performance of the SC_RCS_DGJLFET is superior in terms of IOFF, ION/IOFF ratio, DIBL and subthreshold slope (SS). The SC_RCS_DGJLFET achieves an ultra-low IOFF of 7.033 × 10−16 A, indicating a low leakage current with an impressive ION/IOFF = 5.092 × 1011 . Other performance parameters such as subthreshold slope and DIBL has also been improved for the SC_RCS_DGJLFET device. Subthreshold slope has been decresesd by 4.76% whereas the DIBL decreased by 33.82% when compared to existing RCS_DGJLFET. Additionally, to analyze the effect of doping on the device performance, the core doping in SC_RCS_DGJLFET is varied for fixed shell doping. The study found that fixing core doping to an appropriate value is a crucial parameter to achieve good device performance. The impact of variation of oxide extension towards the source and drain LextS/LextD in SC_RCS_DGJLFET is also studied for the first time in the core–shell architecture which has further improved the device’s performance. Finally, a CMOS inverter is designed using the proposed device that provides valuable insights into its suitability for digital circuit applications and verifies its performance benefits compared to existing transistor technologies. The SC_RCS_DGJLFET based CMOS inverter shows a sharp transition in voltage transfer characteristics (VTC), indicating fast switching speed and precise signal processing capabilities when compared to a CMOS inverter based on a conventional double gate junctionless field effect transistor (C_DGJLFET). Moreover, the transient characteristics of the SC_RCS_DGJLFET based CMOS inverter exhibit an improved output voltage swing, suggesting enhanced dynamic behaviour and stability during logic state transitions.

Realization of ultra-compact and high contrast ratio all-optical 4-to-2 encoder based on 2D photonic crystals

Optical encoders are widely used circuits in digital systems. One of the most critical features of an optical encoder is the power values in two logic states; low and high. The difference between these two values is expressed with the contrast ratio (CR) parameter. This research has designed and simulated an optical encoder based on a two-dimensional (2D) photonic crystal with four inputs and two outputs. The results show that the proposed structure has low power in low mode and high intensity in high mode. This difference in two logical modes has caused the proposed encoder to have CR = 19.8 dB, which is improved compared to previous works. Also, the proposed structure is very compact and its footprint is as small as 96.88 µm2. The data speed for the designed encoder is BR=2Tb/s\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$BR = 2{\ ext{ Tb/s}}$$\\end{document}. This encoder can be used in high-speed optical integrated circuits with low error according to the obtained values.

A hot-emitter transistor based on stimulated emission of heated carriers

Hot-carrier transistors are a class of devices that leverage the excess kinetic energy of carriers. Unlike regular transistors, which rely on steady-state carrier transport, hot-carrier transistors modulate carriers to high-energy states, resulting in enhanced device speed and functionality. These characteristics are essential for applications that demand rapid switching and high-frequency operations, such as advanced telecommunications and cutting-edge computing technologies1–5. However, the traditional mechanisms of hot-carrier generation are either carrier injection6–11 or acceleration12,13, which limit device performance in terms of power consumption and negative differential resistance14–17. Mixed-dimensional devices, which combine bulk and low-dimensional materials, can offer different mechanisms for hot-carrier generation by leveraging the diverse potential barriers formed by energy-band combinations18–21. Here we report a hot-emitter transistor based on double mixed-dimensional graphene/germanium Schottky junctions that uses stimulated emission of heated carriers to achieve a subthreshold swing lower than 1 millivolt per decade beyond the Boltzmann limit and a negative differential resistance with a peak-to-valley current ratio greater than 100 at room temperature. Multi-valued logic with a high inverter gain and reconfigurable logic states are further demonstrated. This work reports a multifunctional hot-emitter transistor with significant potential for low-power and negative-differential-resistance applications, marking a promising advancement for the post-Moore era.

Design of All-Optical D Flip Flop Memory Unit Based on Photonic Crystal.

This paper proposes a unique configuration for an all-optical D Flip Flop (D-FF) utilizing a quasi-square ring resonator (RR) and T-Splitter, as well as NOT and OR logic gates within a 2-dimensional square lattice photonic crystal (PC) structure. The components realizing the all-optical D-FF comprise of optical waveguides in a 2D square lattice PC of 45 × 23 silicon (Si) rods in a silica (SiO2) substrate. The utilization of these specific materials has facilitated the fabrication process of the design, diverging from alternative approaches that employ an air substrate, a method inherently unattainable in fabrication. The configuration underwent examination and simulation utilizing both plane-wave expansion (PWE) and finite-difference time-domain (FDTD) methodologies. The simulation outcomes demonstrate that the designed waveguides and RR effectively execute the operational principles of the D-FF by guiding light as intended. The suggested configuration holds promise as a logic block within all-optical arithmetic logic units (ALUs) designed for digital computing optical circuits. The design underwent optimization for operation within the C-band spectrum, particularly at 1550 nm. The outcomes reveal a distinct differentiation between logic states '1' and '0', enhancing robust decision-making on the receiver side and minimizing logic errors in the photonic decision circuit. The D-FF displays a contrast ratio (CR) of 4.77 dB, a stabilization time of 0.66 psec, and a footprint of 21 μm × 12 μm.

Design and implementation of software modularization in T-type three-level inverter

Abstract This paper addresses the issues of logical allocation state constraints, invalid state switching, and program redundancy in the software design process of the signal processor in the T-type three-level inverter. It combines the importance and advantages of modular thinking in software design to propose a solution method for software modularization based on functional analysis and hierarchical module division. The article presents simulation tests and experimental results of the software modularization of the T-type three-level inverter implemented based on FPGA/CPLD chips, validating the feasibility and effectiveness of this design approach.

Robust and Deterministic Preparation of Bosonic Logical States in a Trapped Ion.

Encoding logical qubits in bosonic modes provides a potentially hardware-efficient implementation of fault-tolerant quantum information processing. Here, we demonstrate high-fidelity and deterministic preparation of highly nonclassical bosonic states in the mechanical motion of a trapped ion. Our approach implements error-suppressing pulses through optimized dynamical modulation of laser-driven spin-motion interactions to generate the target state in a single step. We demonstrate logical fidelities for the Gottesman-Kitaev-Preskill state as high as F[over ¯]=0.940(8), a distance-3 binomial state with an average fidelity of F=0.807(7), and a 12.91(5)dB squeezed vacuum state.

All-2D-Materials Subthreshold-Free Field-Effect Transistor with Near-Ideal Switching Slope.

The Boltzmann Tyranny, set by thermionic statistics, dictates the lower limit of switching slope (SS) of a MOSFET to be 60 mV/dec, the fundamental barrier for low-dissipative electronics. The large SS leads to nonscalable voltage, significant leakage, and power consumption, particularly at short channels, making transistor scaling an intimidating challenge. In recent decades, an array of steep-slope transistors has been proposed; none is close to an ideal switch with ultimately abrupt switching (SS ∼ 0 mV/dec) between the binary logic states. We demonstrated an all-2D-materials van-der-Waals-heterostructure (vdW)-based FET that exhibits ultrasteep switching (0.33 mV/dec), a large on/off current ratio (∼107), and an ultralow off current (∼0.1 pA). The "Subthreshold-Free" operation achieved by the collective behavior of functional materials enables FET switching directly from the OFF-state to the ON-state with entirely eliminated subthreshold region, behaving as the ideal logic switch. Two-inch wafer-scale device fabrication is demonstrated. Boosted by device innovation and emerging materials, the research presents an advancement in achieving the "beyond-Boltzmann" transistors, overcoming one of the CMOS electronics' most infamous technology barriers that have plagued the research community for decades.

All-Optic Logical Operations Based on the Visible-Near Infrared Bipolar Optical Response.

The burgeoning need for extensive data processing has sparked enthusiasm for the development of a novel optical logic gate platform. In this study, junction field-effect phototransistors based on molybdenum disulfide/Germanium (MoS2/Ge) heterojunctions are constructed as optical logic units. This device demonstrates a positive photoresponse that is attributed to the photoconductivity effect occurring upon irradiation with visible (Vis) light. Under the illumination of near-infrared (NIR) optics with wavelengths within the communication band, the device shows a negative photoresponse, which is associated with the interlayer Coulomb interactions. The current state of the device can be effectively modulated as different logical states by precisely tuning the wavelength and power density of the optical. Within a 3×3 MoS2/Ge phototransistor array, five essentially all-optical logic gates ("AND," "OR," "NAND," "NOT," and "NOR") can be achieved in every signal unit. Furthermore, three complex all-optical logical operations are demonstrated by integrating two MoS2/Ge phototransistors in series. Compared to electronic designs, these all-optical logic devices offer a significant reduction in transistor number, with savings of 50-94% when implementing the above-mentioned functions. These results present opportunities for the development of photonic chips with low power consumption, high fidelity, and large volumes.

A Non-Linear Successive Approximation Finite State Machine for ADCs with Robust Performance

This work presents the detailed design of a Successive Approximation Analog to Digital Data Converter (SAR ADC) using bulk 180 nm CMOS IC technology. The focus of the study is on replacing the typical Successive Approximation Register array with a Finite State Machine. This converter features a fully differential and bipolar architecture, which leads to the logic SAR nonlinear behavior. A novel digital control logic mitigates the conversion errors through the conditions in the previous logic states. The logic scheme, in combination with a robust continuous comparator, demonstrates tolerance to Process, Voltage, and Temperature variations. The architecture does not include calibration or additional redundancies in post-layout simulations to emphasize the exclusive benefits of the new SAR logic. The proposed SAR ADC achieves a 14.07 effective number of bits with 7.04 fJ/conversion step Walden figure of merit in biomedical applications.

Design of a Photonic Crystal Exclusive-OR Gate Using Recurrent Neural Networks

In this paper, a novel approach to design a photonic crystal exclusive-OR (XOR) gate with high performance using recurrent neural network (RNN) is proposed, integrating the principles of symmetry and asymmetry inherent in photonic structures. The proposed model realizes the nonlinearities and dispersion properties in photonic systems, optimizing the waveguide paths and interference patterns to improve the performance of the logic gate. Simulation results demonstrate that the presented RNN design not only achieves high fidelity in the logical operation but also significantly enhances the functionality of the all-optical gate. This integration of machine learning with photonic crystal technology opens a new era for developing compact, energy-efficient photonic circuits for high-speed optical computing. Finally, the performance of the designed all-optical gate is compared with other related methods, which shows that the proposed gate outperforms other works. The results show that the obtained output power of the proposed all-optical XOR gate is 0, 0.813, 0.82, and 1 × 10−7 in the logical states.

Nonequilibrium formulation of varying-temperature bit erasure

Landauer’s principle states that erasing a bit of information at fixed temperature T costs at least kBTln⁡2 units of work. Here we investigate erasure at varying temperature, to which Landauer’s result does not apply. We formulate bit erasure as a stochastic nonequilibrium process involving a compression of configuration space, with physical and logical states associated in a symmetric way. Erasure starts and ends at temperature T, but temperature can otherwise vary with time in an arbitrary way. Defined in this way, erasure is governed by a set of nonequilibrium fluctuation relations that show that varying-temperature erasure can done with less work than kBTln⁡2 . As a result, erasure and the complementary process of bit randomization can be combined to form a work-producing engine cycle.

Ferroelectric control of layer-polarized anomalous Hall effects in bilayer and trilayer RuCl2

Layer-polarized anomalous Hall effect (LP-AHE) attracts great interest in the fields of both condensed-matter physics and device applications. However, previous research on implementing the LP-AHE based on the paradigm of topological systems and persistent electric fields has hindered its further development. Here, we go beyond the paradigm and for the first time explore the LP-AHE in polar stacked trilayers, in addition to the bilayer. A general design principle for realizing the layer-locked valleys, spins, Berry curvatures and LP-AHE in bilayer and trilayers is mapped out based on comprehensive analysis of symmetry. Bilayers and trilayers, formed by polar stacking ferrovalley monolayers typically possessing ferromagnetism and hexagonal structure, exhibits valley polarization and out-of-plane electron polarization. Through interlayer sliding, the electric polarization and sign of valley polarization can be simultaneously reversed, yielding the sliding ferroelectricity and ferroelectricity-valley coupling. Owing to the MˆzTˆ symmetry between AB and BA stacked bilayers, the interlayer sliding lead to the opposite sign of Berry curvatures and anomalous Hall velocity, implementing the LP-AHE. The interlayer sliding and Mˆz symmetry between ABC and CBA stacked trilayer lead to the layer controllable LP-AHE. We further demonstrate the feasibility of this design principle in the bilayer and trilayer constructed from ferrovalley H–RuCl2 monolayers through first-principles calculations. Our work not only provides a new route to control the valley-dependent logic state without an external magnetic field, but also greatly enrich the research on LP-AHE.

Deterministic Generation of Qudit Photonic Graph States from Quantum Emitters

We propose and analyze deterministic protocols to generate qudit photonic graph states from quantum emitters. We show that our approach can be applied to generate any qudit graph state and we exemplify it by constructing protocols to generate one- and two-dimensional qudit cluster states, absolutely maximally entangled states, and logical states of quantum error-correcting codes. Some of these protocols make use of time-delayed feedback, while others do not. The only additional resource requirement compared to the qubit case is the ability to control multilevel emitters. These results significantly broaden the range of multiphoton entangled states that can be produced deterministically from quantum emitters. Published by the American Physical Society 2024