Logical Instructions Research Articles

Dynamic vectorization

Several ILP limit studies indicate the presence of considerable ILP across dynamically far-apart instructions in program execution. This paper proposes a hardware mechanism, dynamic vectorization (DV), as a tool for quickly building up a large logical instruction window. Dynamic vectorization converts repetitive dynamic instruction sequences into vector form, enabling the processing of instructions from beyond the corresponding program loop to be overlapped with the loop. This enables vector-like execution of programs with relatively complex static control flow that may not be amenable to static, compile time vectorization. Experimental evaluation shows that a large fraction of the dynamic instructions of four of the six SPECInt92 programs can be captured in vector form. Three of these programs exhibit significant potential for ILP improvements from dynamic vectorization, with speedups of more than a factor of 2 in a scenario of realistic branch prediction and perfect memory disambiguation. Under perfect branch prediction conditions, a fourth program also shows well over a factor of 2 speedup from DV. The speedups are due to the overlap of post-loop processing with loop processing.

Design of a low-cost wire bond tape ball grid array package : R.D. Schueller and A.P. Plepys. Circuit World, 1996, 22(3), 10

This paper presents the first single-chip superconductor FLUX-1 microprocessor designed in the rapid single flux quantum logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction (JJ) technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit microprocessor with a parallel architecture and a target clock frequency of 17–20 GHz. It includes the pipelined instruction memory, 8 integer arithmetic-logic units interleaved with eight registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a multi-chip module carrier. The FLUX-1 instruction set consists of ∼25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 JJs on a 10.6×13.2mm2 die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.

Microprogrammed ALU for a Low Cost Logical Controller

The purpose of the paper is to present the basic design principles of a high-speed, low-cost microprogrammed ALU, integrated in the central processing unit of a Programmable Logical Controller (PLC) as a special LSI circuit. By extending the group of logical instructions of of the PLC with a minimum numberofstatements which act as logic separators such as "open bracket","closed bracket" and"equal", a complete set of logic functions can be implemented using an Algorithmic state Machine(ASM) as ALU.For a defined set of logic instructions, four basic types of powerful general logic expressions are proposed, which cover practically all process control requirements in PLC applications. A detailed description of thehardware architecture of the ALU is given as well as of the data flow between the working registers ;also, suggestions for one-chip VLSI implementation and integration in the central processing unit of the PLC are made.

Scientific reasoning during adolescence: The influence of instruction in science knowledge and reasoning strategies

AbstractThe mechanism linking instruction in scientific topics and instruction in logical reasoning strategies is not well understood. This study assesses the role of science topic instruction combined with logical reasoning strategy instruction in teaching adolescent students about blood pressure problems. Logical reasoning instruction for this study emphasizes the controlling‐variables strategy. Science topic instruction emphasizes variables affecting blood pressure. Subjects receiving logical reasoning instruction link their knowledge of blood pressure variables to their knowledge of controlling variables more effectively than those receiving science topic instruction alone—their specific responses show how they attempt to integrate their understanding.

Computers and Water Resources Education: A Projection

The future impact of computers on water resources education is assessed in terms of the nature of the educational process (logical analysis, instruction, and invention), of the components of the water resources field (water cycle analysis and water cycle modification), and of the principal elements of computer technology of relevance to water resources (machines, programs and data bases, networks, work stations, field station, and robots). Advances in computer technology make it possible to envision, through education and research, the rethinking of the organization and operation of the water resource field, the enhancement of a global‐systemic view of water resources, the strengthening of socio‐technological analyses, the expansion of artificial intelligence approaches, and the creation of custom‐made computer chips for water resources (“hydrochips”).

Functional testing of computer hardware and data-transmission channels based on minimising the magnitude of undetected errors

The paper introduces a criterion for test generation based on minimising the expected magnitude of undetected errors. This criterion is used to develop a best strategy for testing, using the linear checks approach. The detailed analysis is carried out for single unidirectional and bidirectional errors and for multiple unidirectional errors. Specific results concerning the efficiency of the approach are given for basic arithmetical and logical instructions. This approach may be useful in the field testing of hardware which carries out data manipulation and in which small numerical errors can be tolerated; it may also be useful for testing digital transmission channels.

Remarks on simulation of Boolean functions

Recently M. Morris Mano presented a method for performing Boolean OR, AND and NOT operations by means of arithmetic and conditional transfer operations in a decimal computer lacking builtin logical instructions [1]. When A , B , C are variables whose defined value is 0 or 1 and a , b , c are the corresponding integer variables with values 0 or 1, his Boolean OR was defined by: “The result of an OR operation of Boolean variables is the same as the arithmetic addition of the a , b , c integer variables after which the following test is made: (a) If the sum is equal to zero, the result is correct; (b) If the sum is larger than zero, the answer is 1.”

A programming language

This programming language was constructed for a three-address computer, having a 9-digit binary operation code and 20-digit addresses. The instruction repertoire of the computer has all the basic arithmetical, logical and manipulative instructions. There are instructions for unconditional transfer of control and instructions for conditional transfer according to an indicator, set by the previous instruction. The computer has a large external storage system. This programming language has been in use since October 1982. During this time several test and production problems have been run, differing in size and subject. In all cases the time taken for programming was small. The time spent on processing one symbol of information corresponds to the execution of 1,000–2,000 machine instructions. The programs compiled by the compiler are 1.5–2.5 times longer than the programs coded manually. The time taken for the solution of a problem by means of a program compiled by this compiler is 1.5–5 times longer than that taken by hand coded programs. This ratio depends strongly on the number of loops and variable addresses, and also on the number of procedures.

On trees of a graph and their generation

The efficiency with which a complex electrical network may be analyzed by a digital computer depends, largely, upon the efficiency with which the trees of the corresponding graph are generated. This paper is a presentation of those properties of a set of trees that aid us in generating the trees of a given graph. Two different methods for generating trees of a graph are described. Both these methods are extremely efficient for graphs whose nullities are small in comparison to their ranks, especially if the computer is supplied with bit-wise logical instructions. An important theoretical question, that of testing a given set of trees for “completeness,” is also considered.

A Computational Method for Network Topology

This paper deals with methods for listing all possible trees and multitrees, and for determining the relative signs of tree determinants and multitree determinants, which are necessary for the analysis of networks. A connected linear graph having <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</tex> elements and all of its possible subgraphs has been studied by mapping on an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</tex> -dimensional vector space having <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</tex> base vectors, and a method for finding out a number of new trees from one tree, or a set of trees, has been derived. Also, a method of computation for determining the relative signs of tree determinants has been developed. These computations can be performed easily and effectively by a digital computer provided with bitwise logical instructions.

Processing Data in Bits and Pieces

A data-handling unit is described which permits binary or decimal arithmetic to be performed on data fields of any length from one to sixty-four bits. Within the field, character structure can be further specified: these processing entities, called bytes, may be from one to eight bits long. Fields may be stored with or without algebraic sign. On all operations, the relative offset or shift between the operand from memory and that from the accumulator can be specified. Besides the arithmetic operations, three new logical instructions allow any of the sixteen logical connectives of two variables to operate upon each pair of bits in the memory and accumulator operands. The variable field length, variable byte-size features, extend the use of connective operations to a surprisingly wide variety of logical, house-keeping, and editing tasks. These arithmetic and connective instructions are general and powerful programming tools which greatly simplify complex manipulations. Programming of typical tasks, with both the new instructions and with the instruction set of a conventionally-organized computer, has shown that the new set requires substantially fewer instructions to be written, stored, and executed. Furthermore, the new instruction set has considerably fewer distinct operations than the more conventional set. This is possible because the general-purpose instructions of the new set replace many ad hoc instructions which deal with pieces of instructions or data words, or which perform shifting, packing, or editing functions. The initial application of the variable field length data-processing unit is in the IBM Stretch computer.

Frequency Analysis of Digital Computers Operating in Real Time

When used in a control system, the digital computer operates in real time and interacts dynamically with other parts of the system. It is desirable to examine its effect by the use of conventional techniques of servo-mechanism design, namely, frequency analysis. An important feature of most digital computers is that the data passing through them are in sampled form. Frequency analysis has already been applied to the process of sampling and sampled-data systems. The present paper extends this approach to operations performed on the data in sampled form, such as by a digital computer. A real-time linear digital-computer program can be represented by a transfer function. Thus, the computer with its program is a filter whose analysis and design can proceed along lines familiar in network theory and servo design. The error analysis of familiar numerical formulas is illustrated. Various properties of programs are studied in both the s-domain (complex frequency) and the z-domain (complex delay). Tests for stability (or convergence) are described and illustrated. Programming is discussed from a new point of view, and a new programming method is developed. It is indicated how such studies could conceivably affect the logical design or instruction code of a computer.