Logical Address Research Articles

PGAS in-memory data processing for the Processing Unit of the Upgraded Electronics of the Tile Calorimeter of the ATLAS Detector

The ATLAS detector, operated at the Large Hadron Collider (LHC) records proton-proton collisions at CERN every 50ns resulting in a sustained data flow up to PB/s. The upgraded Tile Calorimeter of the ATLAS experiment will sustain about 5PB/s of digital throughput. These massive data rates require extremely fast data capture and processing. Although there has been a steady increase in the processing speed of CPU/GPGPU assembled for high performance computing, the rate of data input and output, even under parallel I/O, has not kept up with the general increase in computing speeds. The problem then is whether one can implement an I/O subsystem infrastructure capable of meeting the computational speeds of the advanced computing systems at the petascale and exascale level.We propose a system architecture that leverages the Partitioned Global Address Space (PGAS) model of computing to maintain an in-memory data-store for the Processing Unit (PU) of the upgraded electronics of the Tile Calorimeter which is proposed to be used as a high throughput general purpose co-processor to the sROD of the upgraded Tile Calorimeter. The physical memory of the PUs are aggregated into a large global logical address space using RDMA- capable interconnects such as PCI- Express to enhance data processing throughput.

Clustered page-level mapping for flash memory-based storage devices

Recent consumer devices such as smartphones, smart TVs and tablet PCs adopt NAND flash memory as storage device due to its advantages of small size, reliability, low power consumption, and high performance. The unique characteristics of NAND flash memory require an additional software layer, called flash translation layer (FTL), between traditional file systems and flash memory. In order to reduce the garbage collection cost, FTLs generally try to separate hot and cold data. Previous hot and cold separation techniques monitor the storage access patterns within storage device, or exploit file system hints from host system. This paper proposes a novel clustered page-level mapping, called CPM, which can separate hot and cold data efficiently by allocating different flash memory block groups to different logical address regions. CPM can reduce the FTL map loading overhead during garbage collection and it does not require any high-cost monitoring overhead or host hint. This paper also proposes a K-associative version of CPM, called K-CPM, which allows different logical address regions to share a physical block group in order to achieve high block utilizations. Experimental results show that CPM improves the storage I/O performance by about 54% compared with a previous page-level mapping FTL, and K-CPM further improves the performance by about 19.4% compared with CPM.

GA-MAP: An Error Tolerant Address Mapping Method in Data Center Networks Based on Improved Genetic Algorithm

Address configuration is a key problem in data center networks. The core issue of automatic address configuration is assigning logical addresses to the physical network according to a blueprint, namely logical-to-device ID mapping, which can be formulated as a graph isomorphic problem and is hard. Recently years, some work has been proposed for this problem, such as DAC and ETAC. DAC adopts a sub-graph isomorphic algorithm. By leveraging the structure characteristic of data center network, DAC can finish the mapping process quickly when there is no malfunction. However, in the presence of any malfunctions, DAC need human effort to correct these malfunctions and thus is time-consuming. ETAC improves on DAC and can finish mapping even in the presence of malfunctions. However, ETAC also suffers from some robustness and efficiency problems. In this paper, we present GA-MAP, a data center networks address mapping algorithm based on genetic algorithm. By intelligently leveraging the structure characteristic of data center networks and the global search characteristic of genetic algorithm, GA-MAP can solve the address mapping problem quickly. Moreover, GA-MAP can even finish address mapping when physical network involved in malfunctions, making it more robust than ETAC. We evaluate GA-MAP via extensive simulation in several of aspects, including computation time, error-tolerance, convergence characteristic and the influence of population size. The simulation results demonstrate that GA-MAP is effective for data center addresses mapping.

Map cache management using dual granularity for mobile storage systems

NAND flash memories have been used in many mobile consumer devices as storage media because they are small, fast, shock-resistant, and energy-efficient. However, the flash storage systems based on these flash devices need a special software layer, the FTL, to translate logical addresses from a host system to physical addresses in NAND flash memories. Recently, the flash storage systems in mobile devices tend to employ a page-level mapping scheme as they are required to yield higher access bandwidth. Unlike common SSDs, which often keep the majority of mapping information in fast but volatile DRAM, the flash storage systems in mobile consumer devices keep only a limited subset of mapping information in a small-sized SRAM due to the restrictions in size, cost, and power consumption. For this reason, many cache management schemes proposed for SSDs may not be suitable for the flash storage systems in mobile consumer devices, though most map cache management schemes used in mobile storage are basically designed for SSD. This paper proposes a novel cache management scheme targeting mobile consumer devices. The proposed scheme uses different management granularities in allocating and evacuating cache space. Experimental results show that the proposed scheme improves map cache performance by up to 36% compared to the existing cache management techniques.

A BIRA for Memories With an Optimal Repair Rate Using Spare Memories for Area Reduction

The test cost and yield improvement of embedded memories have become very important as memory capacity and density have grown. For embedded memories, built-in redundancy analysis (BIRA) is widely used to improve yield by replacing faulty cells with a 2-D redundancy architecture. However, the most important factor in BIRA is the reduction of hardware overhead while keeping optimal repair rate. Most BIRA approaches require extra hardware overhead in order to store and analyze faults in the memory. These approaches do not utilize spare memories during the redundancy analysis (RA) procedure. However, the proposed BIRA minimizes area overhead by utilizing a part of the spare memory as an address mapping table (AMT). Since storing the faulty memory addresses take most of the extra hardware overhead, the reduced logical addresses produced by the AMT are used to reduce the extra hardware overhead. In addition, the reduced addresses are stored in content-addressable memories (CAMs) and used in the RA procedure. The proposed BIRA can achieve an optimal repair rate by using an exhaustive search RA algorithm. The proposed RA algorithm compares the repair solution candidates with all the fault addresses stored in the proposed CAMs to guarantee an exhaustive search. The experimental results show that the proposed BIRA requires a smaller area overhead than that of the previous state-of-the-art BIRA with an optimal repair rate.

English

There are so many devices coming in the market all which need device drivers. Writing device driver is OS specific. In Linux, device driver will be added dynamically. All the current information including added modules will be updated in /proc file system in Linux. Every process will be having its own process address space which can be viewed by the administrator. The central concept of virtual memory is the insertion of a level of indirection between the memory address space seen by a program and the address space of the actual memory in the system. The addresses are seen by a program as virtual addresses; they are also sometimes called logical addresses, and simply addresses when the context makes it clear that they pertain to the address space of a particular program

Virtually Separable Block Management in Flash Storage System

File systems treats Flash storage device as a traditional storage media with their logical address. However inside the Flash storage device, Flash Translation Layer (FTL) remaps logical address to physical address to hide physical limitation of Flash memory cells. Due to the address translation, intentional logical separation of file system’s layout does not directly applied to physical separation. As a result, the separate-intended file systems’ requests are mixed in physical location, which degrades write throughput, as well as Flash’s lifecycle. In this paper, we propose virtually separable Block management scheme for Flash storage system by introducing new common command interface and separable Block management in FTL. The experimental results show that the proposed scheme increases IO performance, as well as reduces flash-internal overhead.

Design and Prototype of a Solid-State Cache

The availability of high-speed solid-state storage has introduced a new tier into the storage hierarchy. Low-latency and high-IOPS solid-state drives (SSDs) cache data in front of high-capacity disks. However, most existing SSDs are designed to be a drop-in disk replacement, and hence are mismatched for use as a cache. This article describes FlashTier , a system architecture built upon a solid-state cache (SSC), which is a flash device with an interface designed for caching. Management software at the operating system block layer directs caching. The FlashTier design addresses three limitations of using traditional SSDs for caching. First, FlashTier provides a unified logical address space to reduce the cost of cache block management within both the OS and the SSD. Second, FlashTier provides a new SSC block interface to enable a warm cache with consistent data after a crash. Finally, FlashTier leverages cache behavior to silently evict data blocks during garbage collection to improve performance of the SSC. We first implement an SSC simulator and a cache manager in Linux to perform an in-depth evaluation and analysis of FlashTier's design techniques. Next, we develop a prototype of SSC on the OpenSSD Jasmine hardware platform to investigate the benefits and practicality of FlashTier design. Our prototyping experiences provide insights applicable to managing modern flash hardware, implementing other SSD prototypes and new OS storage stack interface extensions. Overall, we find that FlashTier improves cache performance by up to 168% over consumer-grade SSDs and up to 52% over high-end SSDs. It also improves flash lifetime for write-intensive workloads by up to 60% compared to SSD caches with a traditional flash interface.

AS B-tree: A Study of an Efficient B + -tree for SSDs *

Recently, flash memory has been utilized as the primary storage device in mobile devices. SSDs have been gaining popularity as the primary storage device in laptop and desktop computers and even in enterprise-level server machines. SSDs have an array of NAND flash memory packages and are therefore able to achieve concurrent parallel access to one or more flash memory packages. In order to take advantage of the internal parallelism of an SSD, it is beneficial for DBMSs to request input/output (I/O) operations on sequential logical block addresses (LBAs). However, the B^(+)-tree structure, which is a representative index scheme of current relational DBMSs, produces excessive I/O operations in random order when its node structures are updated. Therefore, the conventional B^(+)-tree structure is unfavorable for use in SSDs. In this paper, we propose the Always Sequential (AS) B-tree which consists of the Legacy B^(+)-tree structure, a Sequential Writer, a Write Buffer, an Address Mapping Table, and a Node Validation Manager. All of the modified nodes in the Legacy B^(+)-tree are stored in the Write Buffer. If the Write Buffer is full, the Sequential Writer contiguously writes each node of the Write Buffer at the end of the file. To support this algorithm, the Address Mapping Table links NodeIDs of the Legacy B^(+)-tree to the LBA of the corresponding node. Because AS B-tree writes the modified nodes on sequential LBAs in this same manner, it is able to take advantage of the internal parallelism of SSDs. In the experiments presented as part of this paper, AS B-tree enhanced the insertion performance of the conventional B^(+)-tree by 21%. We also confirmed AS B-tree demonstrates better performance than other flash-aware indexes in search-oriented workloads.

Connect Internet with Sensors by 6LoWPAN

In home network design, sensors are implemented based on IEEE 802.15.4 specification , which is a standard for low-rate wireless personal networks, and use 6LoWPAN as its network protocol, which is necessary to translate its internal IPv6 address into an external IPv4 address. In order to connect home networks with the Internet, a simplified framework of mapping protocol stacks and assigning logical addresses is proposed in this paper, in which the most important is a Hush function for matching IPv6 and IPv4 addresses. In addition, we design a dynamic address protocol and a port-mapping model to handle with frequent network structure change caused by sensor regular movement or energy exhaustion. For experiment, we have built a home sensor network gateway to show the feasibility of the model and the experiment results show that our gateway has low delay time and can act quick ly in respon se to sensor movement, taking less message switching process to restructure the home network. The framework is effective and robust, even if the home network is unstable and dynamic.

March Test for Static Neighborhood Pattern-Sensitive Faults in Random-Access Memories

A multibackground March test (March-76N) for a model of static neighborhood pattern sensitive faults (NPSFs) in N ´ 1 random-access memories is presented. March-76N is able to cover both simple and linked NPSFs. As any other test dedicated to the NPSFs, March-76N assumes that the storage cells are arranged in a rectangular grid and the mapping from logical addresses to physical cell locations is known completely. With a length of 76N, this March test is more efficient than other published tests dedicated to this model. Ill. 4, bibl. 16, tabl. 4 (in English; abstracts in English and Lithuanian).DOI: http://dx.doi.org/10.5755/j01.eee.119.3.1369

The Paging Mechanism and MMC Module in XS128 Flash

In this paper we analyze the paging mechanism of XS128 Flash memory in detail, elaborate the functions and theory of Memory Mapping Control (MMC) module which integrated in S12XS serials MCU. We also introduce some registers which involved in MMC to realize the paging mechanism. Besides, we put forward the concepts of Local address, Logical address and Global address in XS128 Flash module, and give the basic theory on the conversion of these addresses.

AS B-트리: SSD를 사용한 B-트리에서 삽입 성능 향상에 관한 연구

최근 플래시 메모리 및 SSD가 노트북이나 PC의 저장장치로 사용되는 것뿐 아니라, 기업용 서버의 차세대 저장장치로 주목 받고 있다. 대용량의 데이터를 처리하는 데이터베이스에서는 삽입, 삭제, 검색을 빠르게 하기 위해 다양한 색인 기법을 사용하는데 그 중B-트리 구조가 대표적인 기법이다. 하지만 플래시 메모리 상에서는 하드디스크와 달리 덮어쓰기(overwrite) 연산을 수행하기 위해서는 먼저 해당 블록(block)에 대하여 플래시 메모리의 연산 중 가장 비용이 많이 요구되는 삭제(erase) 연산을 수행 해야만 한다. 이러한 문제점을 극복하기 위해 플래시 메모리 사이에 위치하는 플래시 변환 계층(Flash memory Translation Layer)을 사용한다. 이 플래시 변환 계층은 수정한 데이터를 동일한 논리 주소에 덮어쓰기를 하더라도 실제로 임의의 다른 물리 주소에 저장하도록 하여 이 문제를 해결할 수 있다. NAND 플래시 메모리를 배열 형태로 포함하고 있는 SSD는 한 개 이상의 플래시 메모리 패키지를 병렬로 접근할 수 있다. 이러한 병렬 접근 방식을 사용하여 쓰기 연산 성능을 향상하기 위해서는 연속한 논리 주소에 쓰기 연산을 요청하는 것이 유리하다. 하지만 B-트리는 구성 노드에 대한 삽입 삭제 연산 시에 대부분 연속되지 않은 논리 주소 공간에 대한 갱신 연산이 일어나게 된다. 따라서 SSD의 병렬 접근 방식을 최대한 활용할 수 없게 된다. 본 논문에서는 수정한 노드를 연속한 논리 주소에 쓰도록 하는 AS B-트리 구조를 제안하여 SSD의 병렬 접근 방식을 최대한 활용할 수 있도록 하였다. 구현 및 실험한 결과 AS B-트리에서의 삽입 시간이 B-트리보다 21% 개선된 것을 확인하였다. Recently flash memory has been being utilized as a main storage device in mobile devices, and flashSSDs are getting popularity as a major storage device in laptop and desktop computers, and even in enterprise-level server machines. Unlike HDDs, on flash memory, the overwrite operation is not able to be performed unless it is preceded by the erase operation to the same block. To address this, FTL(Flash memory Translation Layer) is employed on flash memory. Even though the modified data block is overwritten to the same logical address, FTL writes the updated data block to the different physical address from the previous one, mapping the logical address to the new physical address. This enables flash memory to avoid the high block-erase cost. A flashSSD has an array of NAND flash memory packages so it can access one or more flash memory packages in parallel at once. To take advantage of the internal parallelism of flashSSDs, it is beneficial for DBMSs to request I/O operations on sequential logical addresses. However, the B-tree structure, which is a representative index scheme of current relational DBMSs, produces excessive I/O operations in random order when its node structures are updated. Therefore, the original b-tree is not favorable to SSD. In this paper, we propose AS(Always Sequential) B-tree that writes the updated node contiguously to the previously written node in the logical address for every update operation. In the experiments, AS B-tree enhanced 21% of B-tree's insertion performance.

A Memory Global Optimization Approach in Virtualized Cloud Computing Environments

The combination of cloud computing and virtualization technology introduces a new pattern on resource allocation and utilization.Resource-on-demand based on virtualization can promote the resource utilization,increase the quality of service(QoS) and decrease the total cost of ownership(TCO).However,the resource boundaries of physical servers restrain the global optimization of resources.This paper proposes a memory optimization framework based on a two-tiered address space scheme,in which idle memory in a cloud platform can be remapped into a logical address space to provide reliable memory storage service.This paper also extends the virtual machine monitor to reclaim the idle memory in VMs.The experiment results show the work can accelerate the memory-intensive VMs through efficiently leveraging the memory allocation.

A hybrid flash translation layer with adaptive merge for SSDs

The Flash Translation Layer (FTL) in Solid-State Disks (SSDs) maps logical addresses to physical addresses for disk drive virtualization. In order to reduce garbage collection overhead, we propose full associative striped block-level mapping. In addition, an adaptive merge is proposed to avoid excessive data block reconstructions during garbage collection. With these mechanisms, the write latency is improved up to 78% in comparison with the previous multichannel hybrid FTLs in a sample PC trace. The performance improvements stem from 52% reduced garbage collection.

Location-Based Spiral Clustering Algorithm for Avoiding Inter-Cluster Collisions in WSNs

Wireless sensor networks (WSN) consist of a large amount of sensor nodes distributed in a certain region. Due to the limited battery power of a sensor node, lots of energy-efficient schemes have been studied. Clustering is primarily used for energy efficiency purpose. However, clustering in WSNs faces several unattained issues, such as ensuring connectivity and scheduling inter-cluster transmissions. In this paper, we propose a location-based spiral clustering (LBSC) algorithm for improving connectivity and avoiding inter-cluster collisions. It also provides reliable location aware routing paths from all cluster heads to a sink node during cluster formation. Proposed algorithm can simultaneously make clusters in four spiral directions from the center of sensor field by using the location information and residual energy level of neighbor sensor nodes. Three logical addresses are used for categorizing the clusters into four global groups and scheduling the intra- and inter-cluster transmission time for each cluster. We evaluated the performance with simulations and compared it with other algorithms.

SSD 플래시 변환 계층 상에서 논리 주소 매핑의 성능 향상을 위한 HAMM(Hybrid Address Mapping Method)

ABSTRACT Flash memory based SSDs are currently being considered as a promising candidate for replacing hard disks due to several superior features such as shorter access time, lower power consumption and better shock resistance. However, SSDs have different characteristics from hard disk such as difference of unit and time for read, write and erase operation and impossibility for over-writing. Because of these reasons, SSDs have disadvantages on hard disk based systems, so FTL(Flash Translation Layer) is designed to increase SSDs’ efficiency. In this paper, we propose an advanced logical address mapping method for increasing SSDs’ performance, which is named HAMM(Hybrid Address Mapping Method). HAMM addresses drawbacks of previous block-mapping method and super-block-mapping method and takes advantages of them. We experimented our method on our own SSDs simulator. In the experiments, we confirmed that HAMM uses storage area more efficiently than super-block-mapping method, given the same buffer size. In addition, HAMM used smaller memory than block-mapping method to construct mapping table, demonstrating almost same performance.Keywords : Solid State Disks, Flash Translation Layer, Logical Address Mapping

IEEE 802.15.5 WPAN mesh standard-low rate part: Meshing the wireless sensor networks

This paper introduces a new IEEE standard, IEEE 802.15.5,which provides mesh capability for wireless personal area network (WPAN) devices. The standard provides an architectural framework enabling WPAN devices to promote interoperable, stable, and scalable wireless mesh topologies. It is composed of two parts: low-rate WPAN mesh and high-rate WPAN mesh. In this paper, we present only low-rate WPAN mesh because it is designed to support wireless sensor networks. IEEE 802.15.5 low-rate part is a light-weight scalable mesh routing protocol that caters well to the requirements of resource-constrained wireless sensor networks. By binding logical addresses to the network topology, IEEE 802.15.5 obviates the need for route discovery. This eliminates the initial route discovery latency, saves storage space and reduces the communication overhead and energy consumption. A distributed link state scheme is further built atop the block addressing scheme to improve the quality of routes, robustness, and load balancing. The routing scheme scales well with regard to various performance metrics. The standard also provides enhanced functions such as multicast, reliable broadcast, power saving, time synchronization, route tracing and portability. We also present the performance evaluation of major functions performed with a 50-nodes tested deployed over a whole floor (100 × 140 ft2) at CUNY Engineering building. The results testify that the IEEE 802.15.5 will serve well for wireless personal area networks and wireless sensor networks.

Scale-free, self-organizing very large sensor networks

In this paper we introduce SFSN, an algorithm for self-organization of Very Large Sensor Networks (VLSN). The 10 6 or more tiny and inexpensive sensors of a VLSN are indistinguishable from one another; they do not have either a physical or a logical address, as required by the traditional communication protocols. The self-organization scheme limits the number of partners each sensor collaborates with, thus, it limits the amount of communication and the complexity of coordination. The system is scalable, the amount of state information each node has to maintain is strictly limited regardless of the total number of sensors in the network. The systems we consider mimic biological systems where individual cells of the same type are indistinguishable.

Workload-driven adaptive log buffer-based FTL

Flash translation layer (FTL) is generally used for NAND flash memory in order to handle the mapping between logical page address and physical page address. Log buffer-based FTLs provide good performances with small-sized mapping information. In designing the log buffer-based FTL, one important factor is to determine the mapping architecture between data block and log block, called associativity. While previous static schemes use fixed associativities, our scheme adjusts the associativity dynamically based on the run-time workload variation improving the performance by 5∼16% compared to the static scheme.