Logic Synthesis Tools Research Articles

MAxPy: A Framework for Bridging Approximate Computing Circuits to Its Applications

This paper presents MAxPy, a framework for bridging approximate computing (AxC) circuit design to its applications. MAxPy is an application-agnostic framework able to automatically build a cycle-accurate Python model of an approximate hardware design. This model can easily be emulated and integrated as a module in Python-based applications. We are herein proposing this framework aiming to build an AxC toolbox stimulating open research in academia to promote the integration of the existing and future open-source (i) AxC benchmarks, (ii) approximate logic synthesis tools, and (iii) P unit insights. In this paper, we demonstrate the use of MAxPy to explore the AxC design space of a Sobel filter hardware design as a case study exploiting a set of approximate adders combined with the data-driven approximate logic synthesis via probabilistic pruning. Then, we present a Pareto front for circuit area, energy, and delay reduction versus the application-level metrics: edge detection accuracy and structural similarity index (SSIM). The Pareto front results of the multiple AxC techniques herein explored show circuit area savings ranging from 40.4% to 59.1% for a 98.1% to 99.6% accuracy on edge detection application MAxPy code is open source in: github.com/MAxPy-Project

DeLoSo: Detecting Logic Synthesis Optimization Faults Based on Configuration Diversity

Logic synthesis tools are the core components of digital circuit design, which convert programs written in hardware description languages into gate-level netlists, and optimize the netlists. However, the netlist optimization is complex, with numerous optimization parameters to be configured. Any minor optimization faults in logic synthesis tools may cause circuit diagrams to significantly deviate from the original design, posing risks in target systems. We propose DeLoSo, the De tector of Lo gic S ynthesis o ptimization faults, the first method specifically designed to identify potential faults in the optimization processes of logic synthesis tools. DeLoSo relies on netlist differences and parameter variations to guide the generation of diverse Logic Synthesis Optimization Configuration (LSOC) combinations to thoroughly test the optimization process. DeLoSo consists of three components: LSOC generator, which generates diverse LSOC combinations through configuration recombination and mutation; LSOC diversity evaluator, which assesses the diversity of optimization configurations; and LSOC validator, which validates the generated LSOC combinations to discover optimization faults. DeLoSo identified 19 faults in two established logic synthesis tools (i.e., Vivado and Yosys); 15 of them have been fixed by vendors. Particularly, the community maintainers of Yosys have considered incorporating DeLoSo into Yosys’ existing test suite.

Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models

While high-level synthesis (HLS) tools offer faster design of hardware accelerators with different area versus delay tradeoffs, HLS-based delay estimates often deviate significantly from results obtained from ASIC logic synthesis (LS) tools. Current HLS tools rely on simple additive delay models which fail to capture the downstream optimizations performed during LS and technology mapping. Inaccurate delay estimates prevent fast and accurate design-space exploration without performing time-consuming LS tasks. In this work, we exploit different machine learning models which automatically learn to map the different downstream optimizations onto the HLS critical paths. In particular, we compare graph-based and nongraph-based learning models to investigate their efficacy, devise hybrid models to get the best of the both worlds. To carry out our learning-assisted methodology, we create a dataset of different HLS benchmarks and develop an automated framework, which extends a commercial HLS toolchain, to extract essential information from LS critical path and automatically matches this information to HLS path. This is a nontrivial task to perform manually due to difference in level of abstractions. Finally, we train the proposed hybrid models through inductive learning and integrate them in the commercial HLS toolchain to improve delay prediction accuracy. Experimental results demonstrate significant improvements in delay estimation accuracy across a wide variety of benchmark designs. We demonstrate that the graph-based models can infer essential structural features from the input design, while incorporating them into traditional nongraph-based models can significantly improve the model accuracy. Such “hybrid” models can improve delay prediction accuracy by 93% compared to simple additive models and provide <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$175\times $ </tex-math></inline-formula> speedup compared to LS. Furthermore, we discuss key insights from our experiments, identifying the influence of different HLS features on model performance.

Digital Image Blending by Inexact Multiplication

Digital image blending is commonly used in applications such as photo editing and computer graphics where two images are combined to produce a desired blended image. Digital images can be blended by addition or multiplication, and usually exact addition or multiplication is performed for image blending. In this paper, we evaluate the usefulness of inexact multiplication for digital image blending. Towards this, we describe how an exact array multiplier can be made inexact by introducing vertical cut(s) in it and assigning distinct combinations of binary values to the dangling inputs and product bits. We considered many 8-bit digital images for blending and the blended images obtained using exact and inexact multipliers are shown, which demonstrates the usefulness of inexact multiplication for image blending. For 8 × 8 image blending, one of our inexact array multipliers viz. IAM01-VC8 was found to achieve 63.3% reduction in area, 21% reduction in critical path delay, 72.3% reduction in power dissipation, and 78.1% reduction in energy compared to the exact array multiplier. In addition, IAM01-VC8 achieved 60.6% reduction in area, 9.7% reduction in critical path delay, 64.7% reduction in power dissipation, and 68.1% reduction in energy compared to the high-speed exact 8 × 8 multiplier that was automatically synthesized using a logic synthesis tool. The exact and inexact multipliers were physically realized using 32/28 nm CMOS process technology.

Logic-Depth-Aware Technology Mapping Method for RSFQ Logic Circuits With Special RSFQ Gates

This article proposes a method for generating RSFQ logic circuits utilizing special RSFQ gates in logic synthesis. It is suited for the standard technology mapping flow used in logic synthesis tools and enables generating RSFQ circuits utilizing confluence buffers (CBs) and resettable DFFs (RDFFs), to reduce the number of clocked gates by reduction of logic depth. A library of supergates, each consisting of several gates, is used to compose a resultant circuit in the technology mapping. In this article, a library containing supergates including those special gates is generated and is utilized to design circuits with the gates. First, a generation of a supergate library is proposed to introduce CBs and RDFFs, which realize logic OR without clock pulses and a fused function of logic AND and NOT, respectively. The generated library contains supergates including the special gates and they are used to compose the resultant circuits with the special gates. A mapping approach is also proposed. It distinguishes non-clocked gates such as CBs and clocked gates. It takes the number of inserted DFFs for path balancing into account to reduce the number of clocked gates. The method was implemented into the state-of-the-art academic EDA tool, i.e., ABC, and was evaluated. Evaluation results show that the number of clocked gates is reduced by about 30% from the original ABC with path-balancing DFFs.

CGP-based Logic Flow: Optimizing Accuracy and Size of Approximate Circuits

Logic synthesis tools face tough challenges when providing algorithms for synthesizing circuits with increased inputs and complexity. Machine learning techniques show high performance in solving specific problems, being an attractive option to improve electronic design tools. We explore Cartesian Genetic Programming (CGP) for logic optimization of exact or approximate Boolean functions in our work. The proposed CGP-based flow receives the expected circuit behavior as a truth-table and either performs the synthesis starting from random circuits or optimizes a circuit description provided in the format of an AND-Inverter Graph. The optimization flow improves solutions found by other techniques, using them for bootstrapping the evolutionary process. We use two metrics to evaluate our CGP-based flow: (i) the number of AIG nodes or (ii) the circuit accuracy. The results obtained showed that the CGP-based flow provided at least 22.6% superior results when considering the trade-off between accuracy and size compared with two other methods that brought the best accuracy and size outcomes, respectively.

Sum Propagate Adders

Binary adders are present in every digital computer system. Even if their structure has evolved significantly over the last decades following the progress in logic and circuit design, the scaling of implementation technologies, and the improvement of logic synthesis tools, the fundamental carry-propagation algorithm that guides their operation remains unchanged. This work takes a different path and explores the possibility of performing addition by propagating directly the sum bits of previous bit positions instead of carries. The transformation of binary carry-propagate addition to an equivalent sum propagate addition opens up a whole new design space that spans from ripple-sum to sum-lookahead adders. New parallel-prefix structures that follow the sum-propagation paradigm are presented using a newly introduced associative prefix operator. Sum-propagate and carry-propagate adders have asymptotically the same area and delay complexity. In practice, however, carry propagate adders exhibit better characteristics when implemented in currently established implementation technologies. This gap is expected to reduce in the future using multiple-independent-gate transistors that are promising functionality-enhanced beyond CMOS device technologies, and allow the cost-efficient implementation of AND-XOR operations involved in sum-propagate adders.

Low‐power fast Fourier transform hardware architecture combining a split‐radix butterfly and efficient adder compressors

Fast Fourier transform (FFT) is the most common low-complexity implementation of the discrete Fourier transform, intensively employed to process real-world signals in smart sensors for the internet of things. Butterflies play a central role as the FFT computing core data path since it calculates complex terms employing several multipliers. A low-power FFT hardware architecture combining split-radix decimation-in-time butterfly and 5-2 adder compressors (ACs) is proposed and implemented. The circuits are described in Verilog hardware description language and synthesized using the Cadence Genus synthesis tool. The circuits are mapped onto a 65-nm CMOS ST standard cell library. Results reveal that the proposed FFT hardware architecture using the split-radix butterfly is 13.28% more power efficient than the radix-4 one. The results further show that, by combining 5-2 AC within the split-radix butterfly, our proposal saves up to 43.1% of the total power dissipation considering the whole FFT hardware architecture, compared with the state-of-the-art radix-4 butterfly employing the adder automatically selected by the logic synthesis tool.

Exploring high-order adder compressors for power reduction in sum of absolute differences architectures for real-time UHD video encoding

The sum of absolute difference (SAD) calculation is one of the most computing-intensive operations in video encoders compatible with recent standards, such as high-efficiency video coding (HEVC). SAD hardware architectures employ an adder tree to accumulate the coefficients from the absolute difference between two video blocks. This paper employs high-order adder compressors (HOAC) structures into SAD hardware architectures to achieve ultra-high definition (UHD) encoding in real time, using block sizes compatible with HEVC. The proposed HOAC architectures are power-efficient and enable low-power SAD hardware accelerators. Our throughput analysis shows that the HOAC-based SAD hardware architecture is capable of encoding UHD 4K ( $$3840\times 2160$$ ) videos in real-time at 60 frames per second. The architectures were entirely designed as dedicated ASIC blocks and were synthesized to ST 65 nm CMOS standard cells. Synthesis results show that SAD architectures using 64-2, 32-2, 16-2 and 8-2 compressors built from 4-2 compressors are significantly more efficient in terms of circuit area and total power dissipation when compared with SAD architectures using conventional adders selected by a commercial logic synthesis tool.

Fast Adjustable NPN Classification Using Generalized Symmetries

NPN classification of Boolean functions is a powerful technique used in many logic synthesis and technology mapping tools in both standard cell and FPGA design flows. Computing the canonical form is the most common approach of Boolean function classification. This article proposes two different hybrid NPN canonical forms and a new algorithm to compute them. By exploiting symmetries under different phase assignment as well as higher-order symmetries, the search space of NPN canonical form computation is pruned and the runtime is dramatically reduced. Nevertheless, the runtime for some difficult functions remains high. Fast heuristic method can be used for such functions to compute semi-canonical forms in a reasonable time. The proposed algorithm can be adjusted to be a slow exact algorithm or a fast heuristic algorithm with lower quality. For exact NPN classification, the proposed algorithm is 40× faster than state-of-the-art. For heuristic classification, the proposed algorithm has similar performance as state-of-the-art with a possibility to trade runtime for quality.

QDI Constant-Time Counters

Counters are a generally useful circuit that appear in many contexts. Because of this, the design space for clocked counters has been widely explored. However, the same cannot be said for robust clockless counters. To resolve this, we designed an array of constant response time counters using the most robust clockless logic family, quasi-delay-insensitive (QDI) circuits. We compare our designs to their closest QDI counterparts from the literature, showing significant improvements in design quality metrics including transistor count, energy per operation, frequency, and latency in a 28-nm process. We also compare our designs against prototypical synchronous counters generated by commercial logic synthesis tools.

P3

This article presents the first privacy-preserving localization method based on provably secure primitives for smart automotive systems. Using this method, a car that is lost due to unavailability of GPS can compute its location with assistance from three nearby cars, while the locations of all the participating cars including the lost car remain private. Technological enhancement of modern vehicles, especially in navigation and communication, necessitates parallel enhancement in security and privacy. Previous approaches to maintaining user location privacy suffered from one or more of the following drawbacks: trade-off between accuracy and privacy, one-sided privacy, and the need of a trusted third party that presents a single point to attack. The localization method presented here is one of the very first location-based services that eliminates all these drawbacks. Two protocols for computing the location is presented here based on two Secure Function Evaluation (SFE) techniques that allow multiple parties to jointly evaluate a function on inputs that are encrypted to maintain privacy. The first one is based on the two-party protocol named Yao’s Garbled Circuit (GC). The second one is based on the Beaver-Micali-Rogaway (BMR) protocol that allows inputs from more than two parties. The two secure localization protocols exhibit trade-offs between performance and resilience against collusion. Along with devising the protocols, we design and optimize netlists for the functions required for location computation by leveraging conventional logic synthesis tools with custom libraries optimized for SFE. Proof-of-concept implementation of the protocol shows that the complete operation can be performed within only 355ms. The fast computing time enables localization of even moving cars.

Look-ahead mapping of Boolean functions in memristive crossbar array

Memristors have drawn the attention of researchers due to their unique non-volatile and logic design capabilities. Combining these two, a concept called in-memory computing has emerged, wherein the same memory unit is used for both storage and computation, which helps in overcoming the CPU-memory bottleneck in conventional processor architectures. In this paper, we propose a look-ahead strategy for Boolean functions using Memristor Aided LoGIC (MAGIC) design style in the memristive crossbar, which supports in-memory computing. First, the Boolean function is converted into a netlist of NOT and NOR gates using a logic synthesis tool. The proposed crossbar mapping tool then maps the gate netlist to the crossbar, and also generates the micro-operations needed to execute the gate operations. Experimental evaluation on ISCAS′85 benchmarks reports average improvements of 37.02%, 36.55%, 64.99% and 35.55% respectively in terms of memristor count, latency, crossbar size, and energy over a recently published work. Results were also reported for IWLS-2005 benchmarks.

Logic Optimization, Complex Cell Design, and Retiming of Single Flux Quantum Circuits

Single flux quantum (SFQ) technology has emerged as a promising beyond-CMOS technology with Josephson junctions (JJs) as active devices in a superconducting circuit. In this paper, we (i) describe the algorithms and the methodology we used to synthesize a synchronous SFQ circuit using a CMOS logic synthesis tool by adding new features to the tool and by modifying the existing features; (ii) introduce the concept of two kinds of complex cells: (a) stand-alone cells and (b) interconnected cells along with the advantage gained by these complex cells through the results of synthesized SFQ netlists. Design of stand-alone complex cells presented here includes and and or gates with more-than-two inputs, high-fanout splitters, and “A+BC” cell. Circuits of decoders, multiplexers, and carrylook-ahead adders are synthesized with complex cells, and the advantage in terms of JJ count and latency is presented. We have also investigated the possibility of SFQ cells supporting multiple fanout drive capability by modifying the input/output interfaces of SFQ standard cells. In this direction, an algorithm to modify the input interface of a cell so that it can be driven along with similar cells by a single splitter output is presented along with the results for a simple clock-distribution line with multiple-fanout capability.

Automated Quantum Circuit Synthesis and Cost Estimation for the Binary Welded Tree Oracle

Quantum computing is a new computational paradigm that promises an exponential speed-up over classical algorithms. To develop efficient quantum algorithms for problems of a non-deterministic nature, random walk is one of the most successful concepts employed. In this article, we target both continuous-time and discrete-time random walk in both the classical and quantum regimes. Binary Welded Tree (BWT), or glued tree, is one of the most well-known quantum walk algorithms in the continuous-time domain. Prior work implements quantum walk on the BWT with static welding. In this context, static welding is randomized but case-specific. We propose a solution to automatically generate the circuit for the Oracle for welding. We implement the circuit using the Quantum Assembly Language, which is a language for describing quantum circuits. We then optimize the generated circuit using the Fault-Tolerant Quantum Logic Synthesis tool for any BWT instance. Automatic welding enables us to provide a generalized solution for quantum walk on the BWT.

Synthesis Flow for Cell-Based Adiabatic Quantum-Flux-Parametron Structural Circuit Generation With HDL Back-End Verification

Adiabatic quantum-flux-parametron (AQFP) logic is a very energy-efficient platform to perform computing with superconductivity. In AQFP logic, dynamic energy dissipation can be drastically reduced due to the adiabatic switching operations using ac excitation currents. During the past few years, the AQFP logic family has been investigated and implemented into various operational circuits. Experimental results prove the robustness of building large-scale integrated AQFP circuits. In this paper, an AQFP very large scale integration (VLSI) design flow is introduced and detailed with a 16-b decoder as an example circuit. By including logic synthesis and automatic routing tools, this AQFP VLSI design flow is capable of converting a high-level description of a system into a physical layout. Analysis suggests that a reduction of more than 40% in circuit area and a much higher design efficiency can be obtained, compared to a previous design done manually.

An evaluation and acceptance of COTS software for FPGA-based controllers in NPPS

FPGA (Field-Programmable Gate Array) has received much attention from nuclear industry as an alternative platform of PLC (Programmable Logic Controller)-based digital I&C (Instrumentation & Control). Software aspect of FPGA development encompasses several commercial tools such as logic synthesis and P&R (Place & Route), which should be first dedicated in accordance with domestic standards based on EPRI NP-5652. Even if a state-of-the-art supplementary EPRI TR-1025243 makes an effort, the dedication of indirect COTS (Commercial Off-The-Shelf) SW such as FPGA logic synthesis tools has still caused a dispute. This paper proposes an acceptance process and evaluation criteria, specific to COTS SW, not commercial-grade direct items. It specifically incorporates indirect COTS SW and also provides categorized evaluation criteria for acceptance. It provides an explicit linkage between acceptance methods (Verification and Validation techniques) and evaluation criteria, too. We tried to perform the evaluation and acceptance process upon a commercial FPGA logic synthesis tool being used to develop a new FPGA-based digital I&C in Korea, and could confirm its applicability.

Exploring the use of approximate TMR to mask transient faults in logic with low area overhead

The use of Triple Modular Redundancy (TMR) with majority voters can guarantee 100% single fault masking coverage for a given circuit against transient faults. However, this methodology presents a minimum area overhead of 200% compared to the original circuit. In order to reduce considerably the area overhead without compromising significantly the fault coverage, TMR can use approximated logic circuits to generate redundant modules that are optimized for area, compared to the original module. In this work, we propose the use of only approximate logic modules to compose the TMR in order to reduce the area overhead close to minimal values. We use a Boolean factorization based method to compute approximate functions and to select the best composition of approximate logic. The circuits are mapped using the ABC logic synthesis tool and an academic cell library. All the tests are performed using a fault injection tool designed specifically to cope with logic gate and transistor description level. For a combinational circuit (5 inputs, 10 literals) the results have shown that it is possible to maintain the maximum protected p–n junction ratio of 98.88% with only 165% area overhead when using ATMR; and a maximum of 94.66% protected p–n junction ratio with only an 88% area when using full-ATMR. Results for a 4-bit ripple-carry adder showed a protected p–n juncion ratio of almost 97% with 168% area overhead and 93.5% with only 136% area overhead.

A Circuit Synthesis Flow for Controllable-Polarity Transistors

Double-gate (DG) controllable-polarity field-effect transistors (FETs) are devices whose n - or p - polarity is online configurable by adjusting the second gate voltage. Such emerging transistors have been fabricated in silicon nanowires, carbon nanotubes, and graphene technologies. Thanks to their enhanced functionality, DG controllable-polarity FETs implement arithmetic functions, such as XOR and MAJ, with limited physical resources enabling compact and high-performance datapaths. In order to design digital circuits with this technology, automated design techniques are of paramount importance. In this paper, we describe a design automation framework for DG controllable-polarity transistors. First, we present a novel dedicated logic representation form capable to exploit the polarity control during logic synthesis. Then, we tackle challenges at the physical level, presenting a regular layout technique that alleviates the interconnection issue deriving from the second gate routing. We use logic and physical synthesis tools to form a complete design automation flow. Experimental results show that the proposed flow is able to reduce the area and delay of digital circuits, based on 22-nm DG controllable-polarity Silicon nanowire (SiNW) FETs, by 22% and 42%, respectively, as compared to a commercial synthesis tool. With respect to a 22-nm FinFET technology, the proposed flow produces circuits, based on 22-nm DG controllable-polarity SiNWFETs, with 2.9 $\times$ smaller area-delay product.

FTQLS: Fault-Tolerant Quantum Logic Synthesis

Quantum computation can solve certain problems much faster than classical computation. However, quantum computations are more susceptible to errors than conventional digital computations. Thus, a fault-tolerant (FT) quantum circuit design is required for a practical implementation. Quantum circuits consist of a cascade of quantum gates. These gates are themselves realized using primitive quantum operations that are supported by the quantum physical machine description (PMD). As different quantum systems are associated with different Hamiltonians, they have different PMDs. In addition, the quantum cost for implementing a quantum operation may differ from one PMD to another. Thus, a quantum logic circuit needs to be realized with and optimized for the set of primitive quantum operations supported by the given PMD. In this paper, an FT quantum logic synthesis (FTQLS) methodology and tool is described for six different PMDs. A methodology, such as this, which can be targeted at multiple PMDs, has not been attempted before, to the best of our knowledge. The input to FTQLS is an unoptimized quantum circuit realized using a set of commonly used gates and its output is an optimized FT quantum circuit that only comprises of primitive quantum operations supported by the given PMD. FTQLS does technology mapping for different PMDs and then converts non-FT circuits to FT circuits. For technology mapping, it utilizes an optimized quantum gate library targeted at various PMDs that decomposes gates into primitive operations. Efficient conversion to FT circuits is done by integrating two quantum compilers and an FT cache table into FTQLS. For improving the synthesis results, an FT set of gates that is directly supported by each PMD is proposed. Quantum circuit optimization is done by utilizing quantum identity rules. The performance of FTQLS is evaluated using two cost metrics: number of primitive operations (#ops) and execution cycles on the critical path (#cycles). Experiment results show that the decrease in #ops varies between 58.1% and 87.0% and in #cycles between 42.8% and 76.4%, on an average, depending on the PMD.