Logic Depth Research Articles

Algorithms for Multiplierless Multiple Constant Multiplication in Online Arithmetic

Online arithmetic operators offer advantages of reduction in resource utilization and interconnection complexity besides providing pipelining at digit level. Multiplierless constant coefficient multiplication using the shift-and-add technique is widely used in digital signal processing applications. This paper proposes a novel bit serial adaptation of the parallel shift-and-add algorithm to online arithmetic. The proposed multipliers use right shifts instead of the traditional left shifts resulting in causal online implementations. Graph-based and hybrid algorithms are developed for the estimation of the distance of a constant from a set of constants in terms of the number of additions and for the synthesis of online multiple constant multipliers under area and online delay constraints. The computational complexity of the algorithms is determined. Results of implementation on randomly generated constant sets and FIR filter instances show substantial improvements in the number of operations required using the distance heuristic. Further, it is shown that the proposed techniques and algorithms result in significant savings in resource utilization, logic depth, and clock frequency compared to parallel and digit-serial algorithms.

Psychology, conceptual confusion, and disquieting situationism: Response to Lamiell (2018)

In response to Lamiell’s (2018) commentary arising from my claim that both character and personality belong to “the discourse of individual differences” (Banicki, 2017, p. 56) some further clarifications are provided. At first, an interdisciplinary project lying behind my original article is sketched and the phrase “ individual differences” elucidated as having a non-technical meaning far broader than that connected with individual differences as a specific psychological research paradigm. Then, in turn, Lamiell’s criticism of the notion that the latter can serve as a sole ground for personality psychology is briefly summarised. An attempt is made to simultaneously emphasise the conceptual and logical depth of this criticism and to put into question some of its far-reaching consequences concerning the applicability (or lack thereof) of population-level data at the level of the individual. Finally, a concise remark is made about a specifically philosophical (rather than technically psychological or even psychometrical) approach to the situationism debate.

Undecidability and Irreducibility Conditions for Open-Ended Evolution and Emergence.

Is undecidability a requirement for open-ended evolution (OEE)? Using methods derived from algorithmic complexity theory, we propose robust computational definitions of open-ended evolution and the adaptability of computable dynamical systems. Within this framework, we show that decidability imposes absolute limits on the stable growth of complexity in computable dynamical systems. Conversely, systems that exhibit (strong) open-ended evolution must be undecidable, establishing undecidability as a requirement for such systems. Complexity is assessed in terms of three measures: sophistication, coarse sophistication, and busy beaver logical depth. These three complexity measures assign low complexity values to random (incompressible) objects. As time grows, the stated complexity measures allow for the existence of complex states during the evolution of a computable dynamical system. We show, however, that finding these states involves undecidable computations. We conjecture that for similar complexity measures that assign low complexity values, decidability imposes comparable limits on the stable growth of complexity, and that such behavior is necessary for nontrivial evolutionary systems. We show that the undecidability of adapted states imposes novel and unpredictable behavior on the individuals or populations being modeled. Such behavior is irreducible. Finally, we offer an example of a system, first proposed by Chaitin, that exhibits strong OEE.

Design-Oriented Energy Models for Wide Voltage Scaling Down to the Minimum Energy Point

This paper introduces a transregional energy model to estimate the energy consumption of digital designs for voltages widely ranging from nominal down to deep sub-threshold. The model also predicts the optimal voltage at which the minimum energy point (MEP) occurs, and the resulting minimum energy achievable under aggressive voltage scaling. The model provides the energy profile versus voltage based on a few technology-dependent parameters that are extracted through simple circuit simulations, and other few design-dependent parameters extracted from synthesis or Place&Route reports at nominal voltage only. The model captures the effect of input-dependent (e.g., switching activity), technology-dependent (e.g., corner, transistor flavor), and micro-architectural parameters (e.g., logic depth). The model exhibits a typical error below 10%, and is well suited for design exploration under wide voltage scaling, as it avoids detailed and time-consuming multi-corner and multi-voltage iterations. Also, the model provides a quick estimate of the achievable MEP for a given design. Accordingly, the proposed model is a useful tool that supports early selection of the most energy-efficient design options to meet a targeted energy profile at low voltages.

On the rate of decrease in logical depth

The logical depth with significance b of a string x is the shortest running time of a program for x that can be compressed by at most b bits. Another definition is based on algorithmic probability. We give a simple new proof for the known relation between the two definitions. We also prove the following: Given a string we can consider the maximal decrease in logical depth when the significance parameter increases by 1. There exists a sequence of strings of lengths n=1,2,…, such that this maximal decrease as a function of n rises faster than any computable function but not as fast as the Busy Beaver function. This holds also for the computation times of the shortest programs of these strings.

Lowness and logical depth

Bennett's concept of logic depth [3] seeks to capture the idea that a language has a lot of useful information. Thus we would expect that neither sufficiently random nor sufficiently computationally trivial sequences are deep. A question of Moser and Stephan [11] explores the boundary of this assertion, asking if there is a low computably enumerable (Bennett) deep language. We answer this question affirmatively by constructing a superlow computably enumerable Bennett deep language.

Optimum power supply for minimum energy in nano-CMOS circuits

Operating complementary metal oxide semiconductor (CMOS) circuits in subthreshold mode of operation is proved to be energy efficient for many applications ranging from biomedical implantable devices to wireless sensors which require ultra-low power consumption. In particular, operating CMOS circuits in subthreshold mode minimizes the energy per operation which has been widely considered as the metric for measuring the power efficiency of the circuit. In this paper, the value of the supply voltage that minimizes the energy per operation in CMOS circuits is determined analytically considering the activity factor, the logic depth and the technology parameters. In addition, another analytical closed-form model is developed to predict the least value of the supply voltage for CMOS circuit to function properly. The developed models target the nano-regime CMOS technology. The simplicity of these models provides a good insight into the factors that affect the subthreshold operation. Despite their simplicity, the produced models show a very good agreement with the simulation results considering 16-nm PTM HP process parameters and different CMOS circuits.

Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas

In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified limitations. The power and the energy of the technologies are evaluated and compared assuming given operating frequency targets. The results clearly show how the power/energy advantages of TFET devices are heavily dependent on required operating frequency, switching activity, and logic depth, suggesting that architectural aspects should be taken into account in benchmarking experiments. Two of the TFET technologies analyzed prove to be very promising for different operating frequency ranges and, therefore, for different application areas.

Performance Evaluation of Sequential Adder using Neural Networks

Objectives: Power consumption in digital systems is a crucial issue with the greater emphasis on nano-scaled technologies. Power consumption is greatly curbed by reducing the voltage levels. However, this compromises the circuit delay. Also, by decreasing the voltage level, circuit delay rises exponentially and hence there is an increase in static energy consumption. Methods/Statistical Analysis: In this paper, adders are the architectures chosen for optimization due to the fact that in most of the modern digital systems, the maximum operating speed depends on how fast adders can process the data. This, in turn, is responsible for setting the minimum clock cycle time in processors. The primary focus of this paper is to reduce the delay of Serial Full Adder (SFA), a sequential adder. The delay, power, and area of six different 16-bit adders are examined and compared with respect to their structure and logic depth. This paper presents optimized architectures for 32-bit and 64-bit SFA which operates with less delay and occupies less area by using massively parallel structures. Introducing the concept of neural networks helps us to formulate a power estimation method for adder architectures in SOC Using supervised learning method in Feed Forward Back Propagation Network, the estimated dynamic, leakage and total power is obtained for SFA for any desired input voltage. Findings: The experimental results shows that proposed SFA provides better results with power and delay as metric. The convergence of the proposed estimation method based on neural networks is faster due to its learning and training. Application/Improvements: This method can be extended to estimate the power of any adder architecture and using any other neural network.

Identifying the Worst Reliability Input Vectors and the Associated Critical Logic Gates

Scaling the CMOS devices deep into the nanorange reduces their reliability margins significantly. Consequently, accurately calculating the reliability of digital nanocircuits is becoming a necessity for investigating design alternatives to optimize the trade-offs between area-power-delay and reliability. However, accurate reliability calculation of large and highly connected circuits is complex and very time consuming. This paper proposes a progressive consensus-based algorithm for identifying the worst reliability input vectors and the associated critical logic gates. Improving the reliability of the critical gates helps circuit designers to effectively improve the circuit overall reliability while having a minimal impact on the traditional power-area-deal design parameters. The accuracy and efficiency of the algorithm can be tuned to fit a variety of applications. The algorithm scales well with circuit size, and is independent of the interconnect complexity and the logic depth. Extensive computational results show that the accuracy and the efficiency of the proposed algorithm are better than the most recent results reported in the literature.

Cost-efficient Acceleration of Hardware Trojan Detection Through Fan-Out Cone Analysis and Weighted Random Pattern Technique

Fabless semiconductor industry and government agencies have raised serious concerns about tampering with inserting hardware Trojans (HTs) in an integrated circuit supply chain in recent years. In this paper, a low hardware overhead acceleration method of the detection of HTs based on the insertion of 2-to-1 MUXs as test points is proposed. In the proposed method, the fact that one logical gate has a significant impact on the transition probability of the logical gates in its logical fan-out cone is utilized to optimize the number of the inserted MUXs. The nets which have smaller transition probability than the user-specified threshold and minimal logical depth from the primary inputs are selected as the candidate nets. As for each candidate net, only its input net with smallest signal probability is required to be inserted the MUXs-based test points. The procedure repeats until the minimal transition probability of the entire circuit is not smaller than the threshold value. In order to further optimize the number of required insertions and reduce the overhead, the weighted random pattern technique is also applied. Experiment results on ISCAS’89 benchmark circuits show that our proposed method can achieve remarkable improvement of transition probability with on average 9.50% power, 2.37% delay, and 10.26% area penalty.

Design of Prefix Adder Amalgamation Reversible Logic Gates using 16 Bit Kogge Stone Adder

Objective: VLSI integer adders are critical elements in general purposed DSP and DSPA processors. These used in design of ALU, floating point arithmetic data paths and address generation units. Parallel prefix adders rely on simple cell design. Modern FPGAs utilize fast carry chain for optimization ripple carry adder. Methods/Analysis: Design of the delay models and cost analysis by VLSI embedded system is done in this paper. Prefix adder with reversible logic gates utilizing 16 bit kogge stone adder have been design using PERES logic. Findings: Methodology is based on the fact that a parallel prefix adder can be represented as a graph consists of carry operator nodes. The adder structure has minimum logic depth and binary tree structure with minimum fan-out. From the simulate results this is formed that computational path net delay for 16 X16 bit prefix adder using reversible logic is 20.828 ns with Kogge Stone Adder is reading to 17.247ns. Novelty/Improvement: The multiple based on 16 bit Kogge Stone Adder is formed to be less efficient than the case of reversible adder in term of delay and power analysis.

Sophistication vs Logical Depth

Sophistication and logical depth are two measures that express how complicated the structure in a string is. Sophistication is defined as the minimal complexity of a computable function that defines a two-part description for the string that is shortest within some precision; the second can be defined as the minimal computation time of a program that is shortest within some precision. We show that the Busy Beaver function of the sophistication of a string exceeds its logical depth with logarithmically bigger precision, and that logical depth exceeds the Busy Beaver function of sophistication with logarithmically bigger precision. We also show that sophistication is unstable in its precision: constant variations can change its value by a linear term in the length of the string.

Ultralow-Energy Variation-Aware Design: Adder Architecture Study

Power consumption of digital systems is an important issue in nanoscale technologies and growth of process variation makes the problem more challenging. In this brief, we have analyzed the latency, energy consumption, and effects of process variation on different structures with respect to the design structure and logic depth to propose architectures with higher throughput, lower energy consumption, and smaller performance loss caused by process variation in application-specific integrated circuit design. We have exploited adders as different implementations of a processing unit, and propose architectural guidelines for finer technologies in subthreshold which are applicable to any other architecture. The results show that smaller computing building blocks have better energy efficiency and less performance degradation because of variation effects. In contrast, their computation throughput will be mid or less unless proper solutions, such as pipelined or parallel structures, are used. Therefore, our proposed solution to improve the throughput loss while reducing sensitivity to process variations is using simpler elements in deep pipelined designs or massively parallel structures.

Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs

Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, the evaluation and the comparison of the performance of distinct fan-in logic gates, using a set of widely accepted power–speed metrics, are addressed for five projected tunnel transistor (TFET) technologies and four mosfet and FinFET transistors. The impact of logic depth, switching activity, and minimum supply voltage has been also included in our analysis. Provided results suggest that benefits in terms of a certain metric, in which a higher weight is placed on power or delay, are strongly determined by the selected device. Particularly, the suitability of two of the explored TFET technologies to improve CMOS performance for different metrics is pointed out. A circuit level benchmark is evaluated to validate our analysis.

DPFFs:C2MOSDirect Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling

We propose two master-slave flip-flops (FFs) that utilize the clocked CMOS (C2MOS) technique with an internal direct connection along the main signal propagation path between the master and slave latches and adopt an adaptive body bias technique to improve circuit robustness.C2MOSstructure improves the setup margin and robustness while providing full compatibility with the standard cell characterization flow. Further, the direct path shortens the logic depth and thus speeds up signal propagation, which can be optimized for less power and smaller area. Measurements from test circuits fabricated in 130 nm technology show that the proposed FF operates down to 60 mV, consuming 24.7 pW while improving the propagation delay, dynamic power, and leakage by 22%, 9%, and 13%, respectively, compared with conventional FFs at the iso-output-load condition. The proposed FFs are integrated into an8×8FIR filter which successfully operates all the way down to 85 mV.

BERTRAND RUSSELL'S TRIUMPH AND FAILURE

Bertrand Russell was, along with G.E. Moore, deserving of accolade as a founder of analytic philosophy, and of its close companion, the linguistic turn. Here I explain how his ‘Theory of Descriptions’ relocates philosophy's concern with appearance and reality as a concern with grammatical surface and logical depth. I then on remark the irony of Russell's unhappiness with views to the effect that an ethical judgment is not, despite linguistic appearances, really something that can be true or false. A further irony lies in Russell's error of assigning metaphysical grandeur to logical truths, an error he could have avoided by more fully appreciating how logically misleading linguistic appearances can be.

Gate replacement with PMOS stacking for leakage reduction in VLSI circuits

SummaryScaling down the circuits of complementary metal oxide semiconductor increases the leakage current. Input vector control is an extremely popular method for controlling leakage without using any technological modification. However, it is less effective for larger logic depth circuits.Our study proposes a Worst Leakage State (WLS) free‐node algorithm based on gate replacement technique, in which, when the logic gate of a given circuit goes into WLS, it is replaced by a suitable variant of the gate which in turn reduces the leakage current in an idle mode of the circuit at the same input vector. These variants minimize leakage under WLS conditions. For replacement purpose, four variants (V1–V4) of a two‐input NAND gate are proposed. This technique is applied on different circuits and some benchmark circuits such as ISCAS'85 (C17) and ITC'99 (B01, B02 and B06) (total of 10 circuits), according to the proposed algorithm with variants V1–V4. The average total power is reduced to 15.04%, 15.04%, 35.7% and 31.5%, and the leakage current is reduced to 42.96%, 42.96%, 84.25% and 84.52%, respectively, for variants V1–V4. The average delay is decreased by 16.03% in V1 and V2 variants and increased by 7.74% and 13.16% for variants V3 and V4, respectively, as compared with the results of conventional circuits at 45‐nm Berkeley Predictive Technology Model technology. Copyright © 2015 John Wiley & Sons, Ltd.

Accurate and Efficient Estimation of Logic Circuits Reliability Bounds

As the sizes of CMOS devices rapidly scale deep into the nanometer range, the manufacture of nanocircuits will become extremely complex and will inevitably introduce more defects, including more transient faults that appear during operation. For this reason, accurately calculating the reliability of future designs will be extremely critical for nanocircuit designers as they investigate design alternatives to optimize the tradeoffs between area-power-delay and reliability. However, accurate calculation of the reliability of large and highly connected circuits is complex and very time consuming. This paper presents a complete solution for estimating logic circuit reliability bounds with high accuracy in reasonable time, even for very large and complex circuits. The solution combines a novel criticality scoring algorithm to rank the reliability of individual input vectors with a heuristic search to find the input vector having the lowest reliability. The solution scales well with circuit size, and is independent of the interconnect complexity or the logic depth. Extensive computational results show that the speed of our method is orders of magnitude faster than exact solutions provided by Bayesian network exact inferences, while maintaining identical or sufficiently close accuracy.

Design Flow and Characterization Methodology for Dual Mode Logic

Recently, the dual mode logic (DML) family was introduced as a superior energy-delay alternative to CMOS. DML gates utilize two different modes of operation, dynamic and static, to selectively achieve either high-performance or low-energy operation. Custom designs of DML circuits have been shown to be very efficient. However, implementing DML circuits using the standard design flow and Electronic Design Automation (EDA) tools is very challenging, since DML gates operate in two different modes, each with its own characteristics and operating mechanisms. This paper shows, for the first time, that DML logic can be compatible with the standard design flow and optimized by various tools, such as synthesis and physical design. A DML cell library characterization methodology is also proposed to support the design flow. The methodology and flow were verified on a wide variety of benchmark designs with different gate counts and logic depths, and show that DML design is efficient under the standard design flow restrictions.