Logic-circuit Plane Research Articles

Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction

With the continuous shrinking of technology node, conventional CMOS logic circuits suffer from high power issues due to both increasing leakage current and long traffic delay. Hybrid non-volatile (NV) logic-in-memory architecture, where emerging NV memories are distributed over a logic-circuit plane, has been widely investigated to overcome these limitations. Magnetic tunnel junction (MTJ) is considered as one of the most promising NV candidates thanks to its non-volatility, fast access speed, infinite endurance and easy 3-D integration with CMOS technology. Recently, several 1-bit NV full-adder (FA) structures using MTJ have been proposed to build low-power high-density arithmetic/logic unit for processors. However, one of their major disadvantages is partial non-volatility since they only use MTJs as one of their operands. For the purpose of extending 1-bit NV-FA to multi-bit structure and realizing full non-volatility, synchronous 8-bit NV-FA architecture is presented in this paper, where all the input signals are stored in MTJs instead of CMOS registers. Three possible structures are proposed with respect to different locations of NV data. By using an industrial CMOS 28 nm design kit and a MTJ compact model, we validated their functionalities and compared their performances in terms of power consumption and area, etc.

The Performance of Magnetic Tunnel Junction Integrated on the Back-End Metal Line of Complimentary Metal–Oxide–Semiconductor Circuits

In this paper, we have described the complementary metal–oxide–semiconductor (CMOS)/magnetic tunnel junction (MTJ) integrated process technology; MTJs were fabricated on via metal with surface roughness of 0.3 nm with 0.14 µm CMOS process and 60 ×180 nm2 MTJ process. It is shown that by this process technology, the fabricated MTJ on CMOS logic circuit plane achieves a large change in a resistance of 3.63 kΩ (anti-parallel) with the TMR ratio of 138% at room temperature, which is large enough for a sensing scheme of standard CMOS logic. Furthermore, we have successfully demonstrated the DC and AC operation of this MTJ with write transistors. As the results, our MTJ achieves high enough write/read performance with transistors for realizing MTJ-based logic circuits.

TMR-Based Logic-in-Memory Circuit for Low-Power VLSI

A tunneling magnetoresistive(TMR)-based logic-in-memory circuit, where storage functions are distributed over a logic-circuit plane, is proposed for a low-power VLSI system. Since the TMR device is regarded as a variable resistor with a non-volatile storage capability, any logic functions with external inputs and stored inputs can be performed by using the TMR-based resistor/transistor network. The combination of dynamic current-mode circuitry and a TMR-based logic network makes it possible to perform any switching operations without steady current, which results in power saving. A design example of an SAD unit for MPEG encoding is discussed, and its advantages are demonstrated.

Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI

A novel nonvolatile logic style, called complementary ferroelectric-capacitor (CFC) logic, is proposed for low-power logic-in-memory VLSI, in which storage elements are distributed over the logic-circuit plane. Standby currents in distributed storage elements can be cut off by using ferroelectric-based nonvolatile storage elements, and the standby power dissipation can be greatly reduced. Since the nonvolatile storage and the switching functions are merged into ferroelectric capacitors by the capacitive coupling effect, reduction of active device counts can be achieved. The use of complementary stored data in coupled ferroelectric capacitors makes it possible to perform a switching operation with small degradation of the nonvolatile charge at a low supply voltage. The restore operation can be performed by only applying the small bias across the ferroelectric capacitor, which reduces the dynamic power dissipation. Applying the proposed circuitry in a fully parallel 32-bit content-addressable memory results in about 2/3 dynamic power reduction and 1/7700 static power reduction with chip size of 1/3, compared to a CMOS implementation using 0.6-/spl mu/m ferroelectric/CMOS.