Logic-based Distributed Routing Research Articles

Lattice-Based Turn Model for Adaptive Routing

This paper presents a model for designing partially adaptive logic-based distributed routing algorithms. Unlike the previous methods, the Lattice-based Turn Model associates turn prohibitions with the points of different full-rank integer lattices. Due to the generality of the proposed model, existing approaches can be considered a subset of the solution space identified by this work. Morover, we propose three theorems that are instrumental to the design of lattice-based routing algorithms. In particular, the second theorem gives a necessary and sufficient condition to prove that a lattice-based routing algorithm is deadlock-free as long as the lattice basis meets certain requirements. Based on the proposed model, a novel routing algorithm, called lattice-based routing algorithm (LBRA), is presented. Simulation results exhibit encouraging performance improvements over state-of-the-art approaches when considering real and synthetic benchmarks. For instance, average 71 and 18 percent latency reductions are observed under transpose1 traffic compared to, respectively, Odd-Even and Repetitive Turn Model routing algorithms. Furthermore, LBRA achieves up to 38 and 17 percent performance improvement under real traffic as compared to Odd-Even and Repetitive Turn Model routing algorithms.

σnLBDR: generic congestion handling routing implementation for two‐dimensional mesh network‐on‐chip

The number of cores on a chip is increasing from a few cores to thousands. However, the communication mechanisms for these systems do not scale at the same pace, leading to certain challenges. One of them is on-chip congestion. There are many table-based approaches for congestion handling and avoidance, but these are not acceptable as they impose high area and power overheads. In this study, the authors propose two congestion handling strategies aiming to capture the congestion in few bits to avoid congested routes. The first approach called σ n LBDR (logic based distributed routing) captures congestion present at nodes n-hop away from the current node, reducing area, power and overall packet latency. However, all nodes in the network do not experience same congestion level. For this, their second approach, weighted σ n LBDR, uses a different set of bits for each node and results in the further improvement in area and power. This study shows a comparison of both approaches with each other and also with other similar approaches. From their experimental results, they show that σ n LBDR and weighted σ n LBDR improve latency by 20 and 30%, respectively, and have less area and power overhead as compared with baseline table-based approach.

Hybrid fault tolerant routing algorithm in NoC

Network-on-Chip has been a growing design paradigm with the rise in Multi-Processor System on Chip (MPSoCs) primarily due to its scalability. While regular meshes (2 or 3-dimensional) are the usual proposal for such a paradigm, a real chip may not follow it. Heterogeneous cores, hardware failures or manufacturing defects can possibly cause irregular topologies in a Network-on-Chip. Selection of a routing algorithm is an important challenge in NoC design as it affects power consumption, communication latency and overall system performance. Routing can be supported in such faulty environment by use of routing tables. But this is not a scalable solution as table size grows with network size. Logic Based Distributed Routing (LBDR) is proposed as a new routing implementation technique which offers compact routing implementation and fault tolerance without use of routing table. In this paper we propose a Hybrid Fault Tolerant Routing Algorithm (HFTRA), which aims to provide fault tolerance support in presence of on-chip link failures. Proposed routing is implemented with LBDR scheme. Analysis of the method has shown the effectiveness of proposed scheme as compared to routing tables when implemented using LBDR.

A Brief Comment on “A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs” [ACM Transactions on Embedded Computing Systems 12 (2013) Article 106

In the Ghiribaldi et al. [2013] paper, a complete self-testing and self configuring NoC infrastructure for cost-effective MPSoCs was presented in order to make NoC architecture tolerant to faults. To overcome the complexity involved during the complete reconfiguration of routing instances in the face of most of the usual failure patterns, Ghiribaldi et al. [2013] proposed a fast self-reconfiguration algorithm. The algorithm is based on segment-based routing implemented using Logic-Based Distributed Routing (LBDR) and claimed to have handled the most common NoC faults. The purpose of this comment is to demonstrate the inconsistency of the fast self-configuration method presented in Ghiribaldi et al. [2013]. To handle inconsistency, we present the correct set of LBDR bits and also argue that complete reconfiguration of the routing instance is mandatory to handle some fault combinations. New coverage results of the fast self-reconfiguration algorithm of Ghiribaldi et al. [2013] are also presented.

A novel folded-torus based network architecture for power-aware multicore systems

Multicore computers are expected to be used to process a higher volume of data in the future. Current mesh-like multicore architecture is inadequate to increase memory-level-parallelism because of its poor core-to-core interconnection topology. In some architecture, each node has communication and computation components – switching component of such a node consumes power while the node is only computing and vice versa. In this paper, we propose a folded-torus based topology to improve performance and energy saving. In this architecture, nodes are separated between network switches and computing cores. Using folded-torus concept, we develop a scheme to connect the components (switches and cores) of a multicore architecture. Experimental results show that the proposed architecture outperforms Raw Architecture Workstation (RAW), Triplet Based Architecture (TriBA), and Logic-Based Distributed Routing (LBDR) architecture by reducing the switches more than 53%, the power consumption by up to 71%, and the average delay by up to 58%.

Acyclic LBDRe: fault-tolerant routing algorithm for network on chip

In this paper, as technology scales higher, reliability of network on chip (NoC) becomes key issue. It decreases the transistor reliability by connecting the increasing number of on-chip resources. Consequently, this paper presents an efficient fault tolerant routing algorithm for the NoC architecture. We propose acyclic LBDRe which is based on extended logic-based distributed routing (LBDRe) array. Minimal set of turns are prohibited to avoid deadlock. The algorithm guarantees that not more than 1/3 of all turns in the NoC architecture become prohibited. The proposed routing algorithm outperforms substantially the existing fault tolerant routing algorithms. Simulation results show that the proposed method can noticeably reduce the overall average latency and total network power with minimum hardware cost for the fault tolerant routing algorithm for NoC.

Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems

The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of using routing tables. uLBDR requires a small set of configuration bits, thus being more practical than large routing tables implemented in memories. Several implementations of uLBDR are presented highlighting the tradeoff between routing cost and coverage. The alternatives span from the previously proposed LBDR approach (with 30% of coverage) to the uLBDR mechanism achieving full coverage. This comes with a small performance cost, thus exhibiting the tradeoff between fault tolerance and performance. Power consumption, area, and delay estimates are also provided highlighting the efficiency of the mechanism. To do this, different router models (one for CMPs and one for MPSoCs) have been designed as a proof concept.

A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs

Manufacturing defects in the deep sub-micron VLSI process and aging resulted problems of devices during lifecycle are inevitable, and fault-tolerant routing algorithms are important to provide the required communication for NoCs in spite of failures. The proposed algorithm, referred to as scalable and reconfigurable fault-tolerant distributed routing (RFDR), partitions the system into nine regions using the concept of divide-and-conquer. It is a distributed algorithm, and each router guarantees fault-tolerance within one's own region and the system can be still sustained with multiple fault areas. The proposed RFDR has excellent scalability with hardware cost keeping constant independent of system size. Also it is completely reconfigurable when new nodes fail. Simulations under various synthetic traffic patterns show its better performance compared to Extended-XY routing algorithm. Moreover, there is almost no hardware overhead compared to Logic-Based Distributed Routing (LBDR), but the fault-tolerance capacity is enhanced in the proposed algorithm. Hardware cost is reduced 37% compared to Reconfigurable Distributed Scalable Predictable Interconnect Network (R-DSPIN) which only supports single fault region.

Efficient implementation of distributed routing algorithms for NoCs

Chip multiprocessors (CMPs) are gaining momentum in the high-performance computing domain. Networks-on-chip (NoCs) are key components of CMP architectures, in that they have to deal with the communication scalability challenge while meeting tight power, area and latency constraints. 2D mesh topologies are usually preferred by designers of general purpose NoCs. However, manufacturing faults may break their regularity. Moreover, resource management frameworks may require the segmentation of the network into irregular regions. Under these conditions, efficient routing becomes a challenge. Although the use of routing tables at switches is flexible, it does not scale in terms of latency and area due to its memory requirements. Logic-based distributed routing (LBDR) is proposed as a new routing method that removes the need for routing tables at all. LBDR enables the implementation of many routing algorithms on most of the practical topologies we may find in the near future in a multi-core system. From an initial topology and routing algorithm, a set of three bits per switch/output port is computed. Evaluation results show that, by using a small logic, LBDR mimics the performance of routing algorithms when implemented with routing tables, both in regular and irregular topologies. LBDR implementation in a real NoC switch is also explored, proving its smooth integration in the architecture and its negligible hardware and performance overhead.

Logic-Based Distributed Routing for NoCs

The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. Although 2D meshes are usually proposed for NoCs, heterogeneous cores, manufacturing defects, hard failures, and chip virtualization may lead to irregular topologies. In this context, efficient routing becomes a challenge. Although switches can be easily configured to support most routing algorithms and topologies by using routing tables, this solution does not scale in terms of latency and area. We propose a new circuit that removes the need for using routing tables. The new mechanism, referred to as logic-based distributed routing (LBDR), enables the implementation in NoCs of many routing algorithms for most of the practical topologies we might find in the near future in a multicore chip. From an initial topology and routing algorithm, a set of three bits per switch output port is computed. By using a small logic block, LHDR mimics (demonstrated by evaluation) the behavior of routing algorithms implemented with routing tables. This result is achieved both in regular and irregular topologies. Therefore, LBDR removes the need for using routing tables for distributed routing, thus enabling flexible, fast and power-efficient routing in NoCs.