LOCOS Technology Research Articles

FEATURES OF FORMATION OF BIPOLAR TRANSISTOR FOR IС WITH DIELECTRIC ISOLATION OF ELEMENTS

The processes of a selective epitaxy of silicon layers on the structures Si-SiO2-Si*, formation of dielectric isolation and diffusive areas of complementary bipolar transistor structures are optimized in the work. Complete dielectric isolation of elements IC in episilicon is reached at the expense technology of the structures Si- SiO2-Si* association with the LOCOS technology. Oxidation of the border between layers epimono-Si and epi-Si* is formatted of complete dielectric isolation of elements IC. In this case the border is located at an angle 55° to the surface. In this case the gradient of mechanical tension is directed either to regional area of volume epimono-Si or to layer volume epi-Si * and appearance of mechanical tension, sufficient for emergence of defects in a layer epimono-Si doesn’t happen. Processes of emitter-region diffusion are optimized, which increased the factor of injection of p-n-p-transistors and improved similarity of characteristics of complementary transistors. Epitaxy layers being 3,0–4,0 mcm thick, breakdown tension Uce ≥ 20 V and β ≥ 60 .

Trade-off and process consideration for scalable poly-Si buffered LOCOS technology

The trade-off and process consideration for the scalable usage of poly-Si buffer LOCOS (PBL) technology has been studied. By using a proper stack layer of pad-oxide/poly-Si/nitride, an available and reliable PBL process for scalable device isolation can be achieved. A dual mechanism for pit formation is proposed. As the thermal stress is too large to be sustained by the pad poly-Si, stress-induced voids are found in the poly-Si layer after field oxidation. The residual stress would considerably damage the pad oxide, eventually leading to pit formation at the mostly stressed active area while removing the pad poly-Si. On the other hand, when the stress is not sufficiently high, the pad poly-Si is just subject to stress-enhanced oxy-nitridation. A proper etching control can be employed to retain the integrity of Si substrates. As results, thicker nitride induces larger stress and thus much more easily causes pit formation. Moreover, thicker pad poly-Si can sustain larger stress, but degrade the drain-induced barrier lowering for the field isolation device. Hence, the choice of the PBL stack layer is of great importance to reduce the bird's beak encroachment and alleviate the pit formation as well as retain the gate oxide integrity and the isolation performance.

Radiation hard LOCOS field oxide

It is known that radiation hard field oxides (FOX) can be produced by combination of a thin thermal oxide and a thick P- or As-doped deposited oxide. The doping atoms serve as recombination centers and electron traps for radiation induced charges. This results in a distinctly lower oxide charge at the Si/SiO/sub 2/ interface compared to conventional thermal oxides and, therefore, higher radiation hardness. The radiation resistance of thermally grown FOX for LOCOS isolation cannot be improved much by changes in oxidation parameters. The newly developed radiation hard FOX is produced by local oxidation of P-doped poly-Si. This method preserves the advantages of the LOCOS technology. To distinguish this process from the regular LOCOS process we termed it LOPOX (Local Polysilicon Oxidation). Even with low doping concentrations radiation hardness is improved considerably compared to conventional thermal oxides.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The influence of isolation technique on MOS transistor characteristics, measurements and simulations

Significant electrical characteristics of MOS transistors are influenced by the isolation technique which has been used to fabricate these devices. Under this aspect two isolation techniques are compared: the conventional LOCOS technology and the selective epitaxy isolation technique. Shape and physical properties of the boundary between active transistor area and field isolation are responsible for the influence of the isolation technique on device characteristics. The two isolation techniques being discussed form quite different shapes of this boundary. While the conventional LOCOS technology gives a gradual transition of the oxide thickness from gate oxide to field oxide, new isolation techniques like BOX, trench or selective epitaxy are able to produce a sharp vertical transition between the channel region of the MOS transistor and a fully recessed field oxide. A two dimensional numerical device simulator (GALENE II) is used to study these device structures. Thus internal transistor quantities like electrostatic potential distribution and carrier densities can be observed that cannot be extracted from the terminal characteristics. These simulations enable an interpretation of measured IV characteristics.

Oxidation behaviour of LPCVD silicon oxynitride films

In view of their application as oxidation masks in a modified LOCOS technology the oxidation behaviour of LPCVD silicon oxynitrides was investigated. In dry oxygen hardly any oxidation occurs. The oxidation rate increases with partial water pressure in the ambient. However, in any case the oxidation of oxynitride is at least one order of magnitude smaller than that of silicon. Layers with a composition near O/N = 0.4 were found to have the greatest oxidation resistance. The performance can be further improved by annealing the films prior to oxidation. A model is proposed in which the out-diffusion of N-containing reaction products limits the rate of oxidation. Hydrogen, originating from both the ambient and the as-deposited layer, plays a peculiar role in this process.

MOS isolation technology

Local oxidation with self-aligned field threshold implant has become pervasive as the technique for device isolation in Si-gate technology. As NMOS is replaced by CMOS, this LOCOS technology has been adapted, though with difficulty. Primarily because of poor space utilization, alternatives to LOCOS are now being pursued in a number of laboratories. In this paper the goals and limitations of isolation technology are reviewed, and several alternatives examined. Based on this examination, we suggest that in the near future, evolutionary advances in LOCOS will be adequate. In the longer term, the greatest promise is offered by a technique involving etching and refilling trenches in the substrate.

Selective low-pressure silicon epitaxy for MOS and bipolar transistor application

The selective low-pressure epitaxy is presented in this paper. In contrast to LOCOS technology, this process starts with structuring a thick field oxide by anisotropic RIE etching. Then monocrystalline silicon is grown selectively in the windows formed. Si-gate MOS transistors have been produced using this technology. In the field of bipolar transistors, reactive ion etching and selective low-pressure epitaxy has been used to optimize the Schottky collector transistor to a nearly one-dimensional structure. These transistors have been built on a submicrometer epitaxial layer.