LOCOS Isolation Research Articles

Three-dimensional simulation of total ionizing dose effect on SiGe heterojunction bipolor transistor

The damage mechanism of the total ionizing dose (TID) effect of SiGe heterojunction bipolor transistar (SiGe HBT) is explored by using three-dimensional simulation of semiconductor device (TCAD).In the simulation, the trapped charge defects are introduced into different locations of oxidationin SiGe HBT to simulate the TID effect. Then the degradation characteristics of the forward Gummel characteristic and the reverse Gummel characteristic of the device are analyzed, and the TID damage law of SiGe HBT is obtained. Finally, the simulation results are compared with the <sup>60</sup>Co γ irradiation test results, showing that the trapped charges introduced by TID irradiation in SiGe HBT device mainly affect the Si/SiO<sub>2</sub> interface near the p-n junction, resulting in the change in the depletion region of the p-n junction and the increase of carrier recombination. Eventually, the base current increases and the gain decreases. The trapped charges generated in the EB spacer oxide layer mainly affect the forward Gummel characteristics, and the trapped charges in the LOCOS isolation oxide layer are the main factor causing the reverse Gummel characteristics to degrade. The experimental results on <sup>60</sup>Co γ irradiation under different biases are consistent with those from the total dose effect damage law of SiGe HBT obtained by numerical simulation analysis.

A Concise Numerical TID Radiation Model for <I>n</I>-MOSFET with Nano-Scaled LOCOS Isolation Under Zero Gate Bias

A Concise Numerical TID Radiation Model for <I>n</I>-MOSFET with Nano-Scaled LOCOS Isolation Under Zero Gate Bias

A Novel Method to Extract Carrier Mobility and Threshold Voltage in High-Voltage DDD MOSFETs

In this work, we apply the Hauser technique and combine a newer inversion layer charge model to extract the effective channel carrier mobility (μeff) and threshold voltage (Vth) of several high-voltage DDD MOSFETs with different dimensions in channel length and width. This paper proposes and demonstrates that our new method is a novel and efficient to extract the carrier mobility and threshold voltage in the DDD MOSFET, meanwhile, the extracted data is well consistent with UT model. And, only the extracted values by our new method and BCV method can clearly reflect the narrow-width effect which results from the so called LOCOS isolation technique. Therefore, it is clearly to see that our extraction technique can exactly reflect the device characteristics in high-voltage DDD MOSFETs.

SONOS 구조를 갖는 멀티 비트 소자의 프로그래밍 특성

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by 0.35 <TEX>$\mu\textrm{m}$</TEX> complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the multi-bit operation per cell, charges must be locally frapped in the nitride layer above the channel near the source-drain junction. Programming method is selected by Channel Hot Electron (CUE) injection which is available for localized trap in nitride film. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve are investigated. The multi-bit operation which stores two-bit per cell is investigated. Also, Hot Hole(HH) injection for fast erasing is used. The fabricated SONOS devices have ultra-thinner gate dielectrics and then have lower programming voltage, simpler process and better scalability compared to any other multi-bit storage Flash memory. Our programming characteristics are shown to be the most promising for the multi-bit flash memory.

Silicon nitride deposited by ECR–CVD at room temperature for LOCOS isolation technology

For LOCOS application, silicon nitride (SiNx) insulators have been deposited by ECR–CVD at room temperature and with N2 flows of 2.5, 5, 10 and 20sccm on pad-SiO2/Si or on Si substrates. The obtained SiNx/Si structures were used to analyze the SiNx characteristics. FTIR analyses reveal the presence of SiN and NH bonds. The refractive indexes between 1.88 and 2.48 and the thickness between 120 and 139nm were determined by ellipsometry. With these thickness values, the deposition rates of 9.6–10.1nm/min and the BHF etch rates of 2–86nm/min were determined. On the SiNx/pad-SiO2/Si structures, the LOCOS process was performed. Optical and SEM microscopy analyses were used to investigate the SiNx resistance to thermal oxidation, made at 1000°C, and the bird’s beak in the obtained LOCOS structures, respectively. These analyses reveal that SiNx insulator performed with N2 flows higher than 2.5sccm presented high quality to LOCOS isolation technology.

Narrow-channel effects and their impact on the static and floating-body characteristics of STI- and LOCOS-isolated SOI MOSFETs

Narrow-width effects are investigated in LOCOS and STI-isolated silicon-on-insulator (SOI) MOSFETs. With width as a parameter, variations in threshold voltage, mobility, subthreshold swing and drain-induced barrier lowering are analyzed in relationship with the other transistor dimensions (i.e. channel length, and film thickness). For both isolation techniques, a strong dependence of the threshold voltage with the channel width as well as the SOI silicon film thickness are observed while narrow and short-channel effects are not found to be correlated. Following this, it is shown through saturation subthreshold swing, latch-up and breakdown voltage measurements, that the floating-body effects (FBEs) are reduced in narrow-channel devices. Specific experiments (current transients, source–body junction current…) and simulations were conducted to reveal the mechanisms responsible for the observed weakening of the FBEs. It is concluded that three main mechanisms coexist: (i) the local thinning of the film under the LOCOS isolation, (ii) a lower carrier lifetime near the channel edges and (iii) an increase of the source/body junction leakage near the edges which speeds up the removal of the carriers from the body.

A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs

Silicon-on-insulator (SOI) devices have the great advantage of high operating speed in low supply voltages. This paper presents megabit-class high-speed and low-power embedded SRAM techniques for high data-throughput CMOS/SIMOX ASICs. In order to reduce the power dissipation of high-operating-frequency SRAMs, the multi-V/sub DD/ scheme using a low-voltage power supply only for restricted functional blocks is proposed along with the voltage-swing-matching circuit for "low-voltage" blocks. A squashed double-density layout of six-transistor-type memory cell realizes a small size of 8.64 /spl mu/m/sup 2/ under a 0.3-/spl mu/m CMOS/SMOX logic process including LOCOS isolation and plain local interconnections (e.g., tungsten-deposited diffusion layer and pseudocontacts). A new resistor-coupled current-sense amplifier makes it possible to detect the small readout signal from the memory cell with a short sensing time. To shorten the writing time, each bitline has an individual writing driver (per-bitline architecture). The recovery time of bitlines lowered to write data is also shortened with an accelerator combined with the pulse-reset wordline. A 64 K-words/spl times/16-bits SRAM test chip, fabricated with the 0.3-/spl mu/m pseudomulti-V/sub th/ CMOS/SIMOX process (a short gate length of 0.2 /spl mu/m is available for the fully depleted MOSFETs), has demonstrated the 300-MHz operation under a typical condition with 2- and 1-V power supplies. The power dissipation in standby is less than 0.1 mW and that at 200-MHz operation with a modified checkerboard test pattern is 35.6 mW for single fan-out loads.

Reduced reverse narrow channel effect in thin SOI nMOSFETs

The effects of narrow channel width on the threshold voltage of deep submicron silicon-on-insulator (SOI) nMOSFETs with LOCOS isolation have been investigated. The reverse narrow channel effect (RNCE) in SOI devices is found to be dependent on the thickness of the active silicon film. A thinner silicon film is found to depict less threshold voltage fall-off. These results can be explained by a reduced oxide/silicon interface area in the transistor width direction, thus the boron segregation due to silicon interstitials with high recombination rate is reduced.

Electrically detected magnetic resonance of near-interface defects in Si pn-junction structures with LOCOS isolation

Electrically detected magnetic resonance (EDMR) measurements on planar Si pn-junctions with LOCOS isolation show different types of point defects. We observe P b-centers at the SiO 2/Si interface and detect for the first time via EDMR the so-called “74G doublet” — hydrogen-complexed oxygen vacancies in SiO 2 (LOCOS isolation). The location of the probed oxide defects has to be close enough to the SiO 2/Si interface so that a communication with the junction current can take place.

Reduction of the parasitic charge generation during silicon nitride deposition in a LOCOS isolation without field implant

MOS integrated circuits use the Local oxidation of silicon to isolate laterally adjacent devices (LOCOS isolation). The insulation structure is typically formed by a semiconductor region doped by ion implantation (field implant) and covered by a thick thermal oxide (field oxide). Other insulators (plasma enhanced chemical vapor deposited (PECVD) silicon oxides and LPCVD silicon nitride) and metal interconnection are subsequently deposited on the field oxide. The ion implant together with the thick insulator ensure a high threshold voltage value of the parasitic MOS transistor formed by source and drain of the adjacent active devices and by the insulator/interconnection gate.However, economical purpose leads to the extension of the application field of lower cost technology, addressing the problem of LOCOS isolation without any field implant. As already shown in a previous work [Fay JL, Beluch J, Allirand L, Brosset D, Despax B, Bafleur M, Sarrabayrose G. Jpn J Appl Phys 38(9A):5012–7] for inter-layer dielectric applications, our PECVD oxides suffer from excessive concentration of fixed positive charges brought about by the silicon nitride deposition, and causing the N-channel field threshold voltage to decrease.Characterization reveals that these charges are generated by diffusion of species coming from the gas phase during the silicon nitride process. These generated charges can be reduced either by increasing the O2/tetra-ethyl orthosilicate ratio or by doping the oxide with boron and phosphorus. To avoid diffusion and generation of charges, we minimized the thermal budget using a PECVD silicon nitride. With this process, we have achieved a high threshold voltage and an acceptably low leakage current of the NMOS parasitic transistor.

Hot-carrier degradation mechanism in narrow- and wide-channel n-MOSFETs with recessed LOCOS isolation structure

Narrow-channel n-MOSFETs with recessed LOCOS (R-LOCOS) isolation structure exhibit less hot carrier-induced degradation than wide-channel n-MOSFETs, but the degradation mechanism of both devices is the same. This new finding Is explained by the fact that in deep submicron MOSFETs with ultra-thin gate oxide, the dominant factor deciding the degradation behavior in narrow- and wide-channel devices is the vertical electric field effect rather than the mechanical stress effect.

A leakage current mechanism caused by the interaction of residual oxidation stress and high-energy ion implantation impact in advanced CMOS technology

In this paper, we report abnormal junction leakage current characteristics in sub-quarter micron CMOS formed by OSELO-II isolation method and high-energy ion implantation for well formation. The phenomena have not been found in other isolation schemes such as single Si/sub 3/N/sub 4/ spacer OSELO (SSS-OSELO), modified conventional LOCOS (MLOCOS) and shallow trench isolation (STI). From the defect analysis and process simulation based on the actual recipe, the abnormal leakage is found to be generated from the lattice defects at the edge of field oxide and caused by the combination of oxidation stress, and high-energy ion implantation. A process condition in the high-energy ion implantation and isolation process is proposed to reduce the leakage current.

Process capability of local oxidation of siliconisolationtechnology for sub-half micrometre custom IC applications

The process capability of conventional LOCOS isolation for sub-half micrometre custom IC applications is investigated in terms of field oxide thinning and bird's beak encroachment. A 0.4 µm isolation space appears to be the practical limit when the appropriate film thickness combination is used.

Challenges in hardening technologies using shallow-trench isolation

Challenges related to radiation hardening CMOS technologies with shallow-trench isolation are explored. It is shown that developing a radiation-hardened CMOS technology with shallow trench isolation is more complex than using a traditional hardened field oxide as the trench insulator. We illustrate the use of device simulations in concert with measurements on test structures to provide detailed physical insight into methods for improving total-dose radiation response. Mechanisms that can limit the total-dose radiation hardness of shallow trench isolation such as high electric fields and ion implantation damage are explored. We demonstrate the successful conversion of a non-radiation hardened technology with LOCOS isolation (Sandia's CMOS6) into a greater than 1 Mrad(SiO/sub 2/) radiation-hardened shallow-trench isolated technology (Sandia's CMOS6r).

609 An experimental analysis on a model about driver's errors caused by use of cellular phone

A reverse short-channel effect in LOCOS parasitic MOSFETs is investigated by simulations and experiments. Increase in threshold voltage of the MOSFETs is clearly observed as the LOCOS width decreases to 0.5 μm or less, especially for high substrate doping. Analysis using a nonplanar device simulator shows that this enhancement of the threshold voltage arises from the variation in direction of the electric field at the LOCOS isolation edge due to the two-dimensional structural effect of narrow LOCOS isolation. The reverse short-channel effect is explained by the concept of charge sharing, and the dependence of the reverse short-channel effect on substrate doping and junction depth is examined. As substrate doping increases, a shallow junction depth is found to become an influential parameter for this effect.

Total dose hardness of three commercial CMOS microelectronics foundries

We have measured the effects of total ionizing dose (TID) on CMOS FETs, ring oscillators and field-oxide transistor test structures fabricated at three different commercial foundries with four different processes. The foundries spanned a range of integration levels and included Hewlett-Packard (HP) 0.5 /spl mu/m and 0.8 /spl mu/m processes, an Orbit 1.2 /spl mu/m process, and an AMI 1.6 /spl mu/m process. We found that the highest tolerance to TID was for the HP 0.5 /spl mu/m process, where the shift in NMOS threshold voltage was less than 40 mV at 300 krad. An examination of the dependence of the threshold voltage shift on gate oxide thickness indicated that oxides of the different commercial processes were of similar quality, and that the improvement in the total dose tolerance of the HP 0.5 /spl mu/m technology is associated with the scaling of the gate oxide. Measurements on field-oxide transistors from the HP 0.5 /spl mu/m process were shown not to invert for signal voltages at 300 krad, maintaining the integrity of the LOCOS isolation. The impact of these results is, discussed in terms of the potential insertion of commercial microelectronics into space systems.

Edge Effects of Nitride Film Patterning on Dislocation Generation in Local Oxidation of Silicon

AbstractExtensive monitoring of device characteristics in the manufacturing of ULSI with advanced LOCOS isolation revealed the strong dependence of device leakage currents on the process of patterning of silicon nitride films applied as a hard mask for local oxidation of silicon wafers. At the same time, the level of the leakage currents strongly correlated to stress-induced dislocation density in the device structures. Formation of microtrenches on the wafer surface at the nitride film edges was identified to have a major impact on the leakage currents. Surprisingly, structures having nitride film edge profiles with feet were consistently dislocation-free after the local oxidation. This showed that nitride etching process created surface damage that provided effective sites for crystal defect nucleation in silicon at the film edges. Computer simulations demonstrated that the feet at nitride edges substantially suppress stress growth during local oxidation.

Inverse-narrow-width effect of deep sub-micrometer MOSFETs with LOCOS isolation

The effect of scaling down the channel width on the threshold voltage of deep submicron MOSFETs with LOCOS isolation has been investigated. Previous results, obtained from 1 μm technology and above, show an increase in threshold voltage as the width is reduced. However, in deep submicron technology, oxide thickness is scaled-down and channel doping is increased to avoid punchthrough and maintain a sufficiently high threshold voltage. This results in a threshold voltage reduction as channel width is scaled-down—the so called Inverse-Narrow-Width-Effect (INWE). The trend is explained through dopant redistribution and is verified by both experiment and process simulation. Lastly, a new narrow width threshold voltage model is proposed to account for the dopant redistribution effect.

Is there LOCOS after LOCOS?

Decreasing the field oxide thickness, increasing the temperature or oxidation pressure in a LOCOS type isolation improves field oxide thinning. Under the above regimes, the bird's beak growth results from a reaction-limited mechanism during the linear part of the oxidation process. The latter property is of major importance for the future shrink of LOCOS isolation towards sub-0.1 μm CMOS designs. Market pressure, because of the strong demand for low-voltage and low-power ULSI devices, is defining the framework. Matching the trend in depth-of-focus reduction in lithography tools and limiting process complexity will have to be weighed constantly. The reduction of isolation dimension losses to zero is not as urgent as it used to be. Shallow trench isolation has not come to maturity because of the technically difficult and economically practicable trade-off to be found between planarization and device leakage. Refilling and planarization process standards have not yet been established despite the major progress made in chemical mechanical polishing. The contradiction betwen the planarization issue and the need for an abrupt step at the isolation/active-area edge in order to avoid subthreshold leakage of the MOS active sidewalls still has to be solved. After a brief historical review, we point out and reconsider the main advantages and drawbacks of LOCOS type and shallow trench isolation processes. Within that framework, the impact of isolation design rules on device integration density and isolation performance is reviewed and commented on.

Elimination of Stress‐Induced Defects in Polybuffered LOCOS Isolation Scheme for Sub‐0.25 μm Designs

Decreasing field oxide thickness or (and) increasing field oxidation temperature up to 1100°C, in a polybuffered local oxidation of silicon (PBL) isolation scheme, has a positive impact on field oxide thinning in small spacings, stress‐induced voiding in small active areas, as well as on 5 nm thin gate oxide QBD. A low field oxide thickness and a high temperature field oxidation enable the use of 0.7 μm pitch PBL for sub‐0.25 μm complementary metal oxide semiconductor designs. The transition of the bird's beak growth from a direct oxidation to a diffusion limited mechanism is consistent with the evolution of stress in the middle of active area as a function of field oxide thickness or field oxidation temperature.