Local Oxidation Of Silicon Research Articles

High-Q and high finesse silicon microring resonator

We demonstrate the design, fabrication, and experimental characterization of a single transverse mode adiabatic microring resonator (MRR) implemented using the silicon-on- insulator (SOI) platform using local oxidation of silicon (LOCOS) approach. Following its fabrication, the device was characterized experimentally and an ultrahigh intrinsic Q-factor of ∼2 million with a free spectral range (FSR) of 2 nm was achieved, giving rise to a finesse of ∼1100, the highest demonstrated so far in SOI platform at the telecom band. We have further studied our device to analyze the source of losses that occur in the MRR and to understand the limits of the achievable Q-factor. The surface roughness was quantified using AFM scans and the root mean square roughness was found to be ∼ 0.32±0.03 nm. The nonlinear losses were further examined by coupling different optical power levels into the MRR. Indeed, we could observe that the nonlinear losses become more pronounced at power levels in the range of hundreds of microwatts. The demonstrated approach for constructing high-Q and high finesse MRRs can play a major role in the implementation of devices such as modulators, sensors, filters, frequency combs and devices that are used for quantum applications, e.g., photon pair generation.

Analysis of Hump Effect Induced by Positive Bias Temperature Instability in the Local Oxidation of Silicon n-MOSFETs

In this study, the degradation of the subthreshold swing (S.S.) and the hump effect are observed in the local oxidation of silicon (LOCOS) metal-oxide-semiconductor field-effect transistors (MOSFETs) under short-and long-term positive bias temperature instability tests, respectively. S.S. collapse is considered to be caused by anode hot-hole injection, and the hump effect occurs because the geometric structure from LOCOS isolation forms parasitic transistors on both sides of the channel, which can be verified by a Silvaco Technology computer-aided design (TCAD) simulation. In addition, the body effect measurement method is proposed to elucidate the mechanism of the hump effect for further confirmation of hump formation.

Modeling and Characterization of the Narrow-Width Effect of 4H-SiC MOSFETs With Local Oxidation of SiC Isolation

In this article, the narrow-width effect (NWE) of 4H-SiC MOSFETs with local oxidation of SiC (LOCOSiC) isolation is reported. A channel width-dependent current hump was observed in the subthreshold region for n-type 4H-SiC MOSFETs with LOCOSiC, and a channel width-dependent threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{th}$ </tex-math></inline-formula> ) shift was observed for p-type 4H-SiC MOSFETs with LOCOSiC. This unusual NWE arises from the increase in the gate oxide thickness from the channel center toward the isolation edge and is different from the conventional NWE found in local oxidation of silicon (LOCOS) technology, which arises from the charge stored in the parasitic field oxide (FOX) capacitor and lateral dopant encroachment. A H2O diffusion and oxidation model is proposed in this article to explain the growth of a long bird’s beak in 4H-SiC MOSFETs with LOCOSiC. Technology computer-aided design (TCAD) simulations were executed to explore the H2O diffusion behavior of these MOSFETs, and an analytical formula was derived to predict the oxide layer thickness and length of bird’s beak along the diffusion path in the H2O diffusion and oxidation model. The problems caused by the long bird’s beak and unusual NWE can be overcome by increasing the overetching time of the pad oxide removal and marginally decreasing the thickness of the FOX layer. Therefore, the NWE of the LOCOSiC isolation is expected to be weaker than that of the LOCOS isolation because field implantation is unnecessary, and thus, dopant encroachment does not occur in the LOCOSiC technology.

Detailed total ionizing dose effects on LDMOS transistors

The degradation of lateral double-diffused MOSFETs (LDMOS) due to total ionizing dose (TID) effects is examined in this paper using physics-based 2D TCAD simulations. The devices under test (DUTs) are built with a single reduced surface field (single-RESURF) structure and local oxidation of silicon (LOCOS) field oxide. The device structure was chosen for its topological simplicity in comparison to other modern LDMOS transistors to explore the impact of gamma radiation on small-AC and RF behavior. The results demonstrate fundamental differences between n-type (nLDMOS) and the p-type (pLDMOS) parameter shifts. Due to the distinct damage location in the pLDMOS, which is mainly the drift region, TID augments the values of the various parasitic capacitances. However, in the nLDMOS, TID reduced those values, especially the gate capacitance overshoot, as the degradation happens in the channel region and the bird's beak mostly. Consequently, the RF response and stability of the devices will differ. In addition, we present new research opportunities for TID effects on LDMOS transistors in particular, but also for radiation studies in general.

Evaluation of Hot Carrier Impact on Lateral-DMOS with LOCOS feature

Hot carrier stress is evaluated on a laterally diffused MOSFET (LDMOS) by TCAD simulation. The device under test is obtained from process simulation under a 1µm CMOS flow available at CDTA. The n-type transistor uses the LOCOS (local oxidation of silicon) and single RESURF (reduced surface field) features. Using the trap degradation model, degradation over time and different biases, the shift of threshold voltage VTH, ON-state resistance RON, saturation current IDsat, and device lifetime are extracted. The shifts were found to be manageable, they have a single process mechanism and are due to hot electrons in our case. But, flicker noise assessment under the same stress shows noticeable instabilities.

Thermodynamic insights into Henry's constant in hyperthermal oxidation of silicon for fabricating optical waveguides.

Hyperthermal oxidation of silicon is envisaged to be an alternative to silicon-on-insulator (SOI) waveguide fabrication for photonic integrated circuit (PIC) devices, and thus the local oxidation of silicon (LOCOS) technique has attracted attention. In this article, starting with the thermodynamic insights into the Deal-Grove model for defining the thermal oxidation, we model the Henry's law constant in the silicon oxidation process with the ensemble contributions of thermodynamic and chemical energies, and extract an empirical model with the published statistical data. Then, the simulations show the dramatic temperature/time dependences of Henry's constant, and the different effects of the thermodynamic and chemical energies. Systematic simulations of the temperature/time dependences of both the growth rate and thickness of oxide are carried out where the temperature dependence of the oxidant diffusivity is also considered. Consequently, the simulation results from the two models astonishingly agree with each other. Typically, at 1100 °C, with a 3 h oxidation time, 2.10 and 1.34 μm SiO2 layers can be grown with the thermodynamic model under two diffusivity models, while with the empirical one, the two extreme cases can grow 2.10 and 1.28 μm SiO2 layers, respectively.

Intraguide mode conversions of silica-on-silicon transfer waveguides and SOI tapered structures for highly efficient chip-fiber butt coupling.

An advanced fiber-waveguide coupling scheme is crucial to the effective developments and applications of silicon-on-insulator (SOI) waveguide photonic integrated chips. In this paper, a regime of the mode conversions within guided channels is investigated to realize a highly efficient fiber-chip coupling with a silica-on-silicon (SOS) transfer waveguide that can be realized with the local oxidation of silicon (LOCOS) technique. With this regime, the optical-field overlap process of two optical guided modes between the fiber and the SOI waveguide through a gap is simplified to the two loss contributions: (i) the ultralow coupling loss of the fiber-SOS transfer waveguide and (ii) the Fresnel loss of the SOS transfer waveguide and an SOI tapered structure. As a result, all the mode conversions in this system are operated within the guided channels, so it is referred to as an intraguide mode conversion. Further, the overall mode conversion efficiency of such a fiber-SOS-SOI system is modeled, in which the three key processes, the fiber-SOS gap mode conversion, the SOS-SOI interface mode conversion, and the SOI taper profile mode conversion, are individually investigated and optimized. The simulation values and the experimental results are agreeable with each other for both fiber-SOS waveguide coupling loss and fiber-SOI waveguide coupling loss. Consequently, a fiber-chip butt-coupling loss of 0.8-1.0 dB/facet is demonstrated. Finally, the conditions for realizing the effective LOCOS structure and process are discussed.

Study of the Local Oxidation of Silicon Waveguide for Realizing the Intra-Guided Mode Conversions

The impressive achievements in research and developments of silicon-on-insulator (SOI) based silicon photonic integrated (PIC) devices have been made, but the coupling loss between the fibre and SOI waveguide is still a fatal problem. As well known, the butt coupling between a fibre and a low index-contrast silica-on-silicon (SOS) waveguide only causes a much lower optical loss, however, such a process between a fibre and a high index-contrast SOI waveguide creates a much higher optical loss. In this work, a 2-step intra-guide mode conversion of fibre-SOS-SOI structure is modelled and studied, in which a mitigating structure of SOS waveguide is created via a local oxidation of silicon (LOCOS) technique. The LOCOS method is an in-situ chemical process during the waveguides are fabricated without causing any extra fabrication, but it can control the physical parameters of the SOS waveguide through a chemical process. In such a 2-step intra-guide mode conversion, the total optical efficiency of the fibre-SOS-SOI structure is modelled, and the optical efficiencies of both the fibre-SOS mode conversion and the SOS-SOI mode conversion are systematically studied, and the broad dependences of guided mode profile on the chemical parameters of the LOCOS process are discussed. As a result, a total optical loss of <0.5dB for a butt coupling process between fibre and single-mode SOI-waveguide is achieved. So far, no similar practical butt-coupling method has been reported yet.

Comparison of Si3N4-SiO2 and SiO2 Insulation Layer for Zero-Bias CMUT Operation Using Dielectric Charging Effects.

In this letter, we report the characteristics of zero-bias capacitive micromachined ultrasonic transducers (CMUTs) in various aspects, considering the transmission and reception sensitivity and evaluation of the long-term stability with ac transmission in immersion. The main idea of the zero-bias CMUT implementation is that the charge is injected by the dielectric charging effects in an insulation layer in the pull-in state. The CMUT was fabricated by a local oxidation of silicon (LOCOS) process, and the insulation layer consists of Si3 N4 -SiO2 and SiO2, which have been commonly used in previous studies. A study on the charging effects is reported to quantitatively observe the voltage shift by charge transfer with time dependence at different temperatures and collapsing time dependence. Therefore, we successfully implemented a zero-bias CMUT with a transmission efficiency of 4.62 kPa/V at a center frequency of 7.53 MHz in Si3 N4-SiO2 and a transmission efficiency of 6.78 kPa/V at a center frequency of 7.86 MHz in SiO2 immersion.

Comparison of holes trapping and protons transport induced by low dose rate gamma radiation in oxide on different SiGe processes

Space-related electronics contain different types of oxide isolations which are the crucial factor resulting in device degradation and failure. Previous studies show that the local oxidation of silicon (LOCOS) isolation Silicon‑germanium heterojunction bipolar transistor (SiGe HBT) experience more significantly low dose rate sensitivity than that of shallow trench (STI) isolation SiGe HBTs and behave a “true” dose rate effect. In our work, the electron-hole pairs (EHPs) generation, holes trapped and protons transport inside oxide are simulated in LOCOS and STI isolation SiGe HBTs to explanation the different response t enhanced low dose rate sensitivity (ELDRS). The simulation results show that LOCOS oxide has a larger generation of EHPs than that of STI oxide leading to more surviving holes and protons release within oxide.

Silicon p-n-Diode Based Electro-Optic Modulators

A method for forming p-n-diode based silicon electro-optic modulators using local oxidation is tested. It is shown that the local oxidation of silicon allows forming a rib waveguide as a smoothed trapezoid, in contrast to the classical technique of creating a rib waveguide by plasma-chemical etching. The main advantages of the approach used are described: controllability and reproducibility of critical design parameters of the modulators (width and height of the waveguide rib), low surface roughness, and the possibility of using approaches to forming a modulating p-n-diode of combined type in a rib waveguide, which are standard for planar technologies.

An Injection Enhanced LIGBT on Thin SOI Layer Compatible With CMOS Process

In this paper, we present a lateral injection enhanced insulated gate bipolar transistor (LIEGT) and investigate its mechanism. The LIEGT features a recessed trench at the cathode side of the drift region formed by LOCal oxidation of silicon (LOCOS) process. The recessed trench suppresses holes being extracted and enhances the electron injection, thus contributing to a very low loss in the ON-state. The ON-state voltage ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ) of the LIEGT is reduced by 24% at the current density of 200 A/cm2 and the saturation current is 40% higher than that of the conventional lateral insulated gate bipolar transistor (LIGBT). The LIEGT exhibits an improved tradeoff between ${V}_{ \mathrm{\scriptscriptstyle ON}}$ and turnoff loss ( ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ ). For the same ${V}_{ \mathrm{\scriptscriptstyle ON}}$ , the ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ is decreased by 38% compared with that of the conventional LIGBT.

Characteristics and reliability of VDMOS under capacitive loads

The failure mechanism of vertical double-diffusion metal-oxide-semiconductor (VDMOS) turning on under capacitive loads is analyzed. Due to the structural features of the device, it is easy to burnout at the source pad (SPAD) area when turning on under capacitive loads. On the basis of simulation, thermal characteristics of VDMOS devices under capacitive loads are analyzed. The results show that junction temperatures (Tj) are obviously affected by capacitive load values (CL) and thermal resistances (Rth) of VDMOS devices. When Rth = 0.1 °C/W or Rth = 0.15 °C/W, curves between Tj and CL present an approximately linear relationship, while when Rth = 0.2 °C/W, the rate of Tj rising with CL shows an increasing trend. At last, the influences of device structure and process on capacitive load limits are verified by experiments. The results show that the design of local oxidation of silicon (LOCOS) structure has little effect on capacitive load limits of devices, while the capacitive load limit of the fourth generation (R4) process devices is obviously higher than that of the fifth generation (R5) process devices.

Sensitivity Optimization of Wafer Bonded Gravimetric CMUT Sensors

Optimization of the mass sensitivity of wafer bonded resonant gravimetric capacitive micromachined ultrasonic transducers (CMUTs) is presented. Gas phase sensors based on resonant gravimetric CMUTs have previously been demonstrated. An important figure of merit of these sensors is the sensitivity which, for typical CMUT geometries, is increased by decreasing the radius of the CMUT cell. This paper investigates how to minimize the radius of CMUT cells fabricated using the wafer bonding process. The design and process parameters affecting the radius of the CMUT and hereby the sensitivity are studied through numerical simulations and atomic force microscopy measurements. An excellent fit was obtained between the simulations and measured profiles with a low relative error of ≤ 5%, thus validating the simulation model. Two types of CMUTs are designed and fabricated using the design and process rules determined herein, with experimentally determined mass sensitivities of 0.46 Hz/ag and 0.44 Hz/ag, respectively. The two CMUT devices have cavities made using the local oxidation of silicon (LOCOS) and reactive ion etching (RIE) process. For the LOCOS process, it was found that the smallest radius can be obtained by choosing a Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> oxidation mask and lowering the pad SiO2 thickness, vacuum gap height, and Si bump height. For the RIE process, the vertical dimensions do not influence the horizontal dimensions and consequently, equivalent rules do not exist.

Radiation-tolerance analysis of I-gate n-MOSFET according to isolation oxide module in the CMOS bulk process

The n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET) produced in the widely used CMOS bulk process takes radiation damage by the total ionizing dose (TID) effects in radiation environments, so the radiation-tolerant properties of semiconductor integrated-circuits (ICs) used in high-radiation environments is a critical issue. The formation method of the isolation oxide module (IOM), which induces the radiation-induced leakage currents, differs depending on the chip density of the CMOS bulk process. In this paper, we designed and fabricated I-gate n-MOSFETs for bulk process and analyzed the radiation-tolerant characteristics according to IOM. The I-gate n-MOSFET chips are fabricated using the shallow trench isolation (STI) 0.18um and local oxidation of silicon (LOCOS) 0.35um processes of the CMOS bulk process. Tests and evaluation of the TID effects on the chips are carried out by irradiating a total cumulative dose up to 2 Mrad(Si). As the results, in the standard n-MOSFET, the leakage currents of the LOCOS and STI processes are 27.7uA and 16.4uA, and in I-gate n-MOSEFT, are 1.1uA and 0.7uA. The leakage currents of standard n-MOSFET increased by about 25 times before and after irradiation, but the electric characteristics of I-gate n-MOSFET is maintained regardless of the process. Therefore, the process versatility of the I-gate n-MOSFET with the radiation-tolerant performance has been verified.

Combined colorimetric and gravimetric CMUT sensor for detection of benzyl methyl ketone

The detection of benzyl methyl ketone (BMK) is of interest as it is a common precursor for the synthesis of (meth)amphetamine. Resonant gravimetric sensors can be used to detect the mass and hereby the concentration of a gas while colorimetric arrays typically have exceptional selectivities to a target analyte. We present a sensor system consisting of a capacitive micromachined ultrasonic transducer (CMUT) and a colorimetric array for detection of BMK. The CMUT is used as a resonant gravimetric gas sensor where the resonance frequency shift due to mass loading of the plate. A single local oxidation of silicon (LOCOS) step was used to define the cavities which were sealed with a Si3N4 plate with a thickness of 100 nm, resulting in a resonance frequency of 38.8 MHz and a mass sensitivity of 28.3zgHz×μm2 or 8.5 × 103 cm2/g This sensitivity is, to our knowledge, the best reported as compared with the state of the art of CMUTs. The CMUTs were functionalized with the same dyes used to fabricate the colorimetric arrays. While both the CMUT and the colorimetric array showed selectivity between BMK and acetone and water, the highest selectivity was achieved with the colorimetric array. Here the analyte BMK resulted in the only signal (color change), while acetone and water did not give any signal. Furthermore, the mass of the BMK was found as a function of time. Thus, the combination of a colorimetric array and a CMUT resulted in a sensor system with a selectivity between BMK, acetone and water and in addition a quantitative value for the mass.

(Invited) Proximity Gettering Design of Hydrocarbon Molecular Ion Implanted Silicon Wafers Using Direct Bonding Technique for Advanced CMOS Image Sensors: A Review

Complementary metal oxide semiconductor (CMOS) image sensors have become widely used ubiquitous devices such as smart phone and personal computer type tablets. Consumer markets strongly demands more high sensitivity imaging and more high speed image data processing for achieving advanced CMOS image sensor fabrication. However, there are some serious improvement technical issues in CMOS image sensor fabrication process. Extremely important technical issue is metallic impurity contaminated device active region during device fabrication process such as high temperature rapid thermal annealing, dry etching and plasma heat treatment. Metallic impurities formed deep energy level defects in the silicon band-gap. Thus, these deep energy level defects strongly affects electrical device characteristic such as pn-junction leakage current, recombination lifetime and gate oxide breakdown voltage. Another technical issue is oxygen impurity out-diffused to the device active region from a Czochralski (CZ) grown silicon substrate during device heat process. Oxygen impurity formed oxygen related deep energy level defects in the device active region of photo-diode space charge region and transfer transistor gate channel region. These oxygen related defects strongly influenced on electrical device performance such as image lag. Therefore, in recent years, CMOS image sensor manufacturers have strongly demanded silicon wafers with the highest metal and oxygen impurities gettering capability during CMOS device processes. In response, we have developed a novel gettering wafer production concept using a hydrocarbon molecular ion implantation technique for advanced CMOS image sensors [1][2][3]. This technique can implant a silicon wafer surface simultaneously with carbon and hydrogen elements that form the projection range using a hydrocarbon compound molecular gas source. In our previous study, it was found that a hydrocarbon molecular ion implanted silicon wafer had three unique characteristics for high performance of advanced CMOS image sensors. First, a hydrocarbon molecular ion projection range has high gettering capability of metallic impurities [1][2][4]. Second, this projection range also has a diffusion barrier effect for oxygen impurities out-diffusing to the device active region from a CZ grown silicon wafer substrate [5]. Third, it is expected that diffusing hydrogen to the device active region from the hydrogen of hydrocarbon molecular ions gettered in the projection range during the device fabrication process will have a passivation effect on unreconstructed surface dangling bonds and Si/SiO2 interface state densities such as local oxidation of silicon or shallow trench isolation [6][7]. Moreover, we achieved more improvement for gettering capability of hydrocarbon molecular ion implanted silicon wafer which formed epitaxial layer without epitaxial growth process using room temperature direct bonding technique. In this presentation, we demonstrate that a hydrocarbon molecular ion implanted silicon wafers using room temperature direct bonding technique has high gettering capability characteristics for transition metal and light element impurities such as oxygen, and hydrogen during the CMOS image sensor fabrication process.

Ultra-fast and sensitive silicon nanobelt field-effect transistor for high-throughput screening of alpha-fetoprotein

In this paper, we described a novel fabrication technique for Silicon nanobelt field-effect transistors (SiNB FETs) based on the Local Oxidation of Silicon (LOCOS) process widely utilized in the manufacturing of microelectronics components and explore it to screened alpha-fetoprotein (AFP). LOCOS process is used as it enables thorough compatibility with complementary metal oxide semiconductor (CMOS) technology. Thus, the need for expensive lithography tools to define the nanoscale pattern is avoided. The SiNB FETs emerges as a powerful biosensor for ultrasensitive, label-free for biological/chemical detection and direct electrical readout. The analytical sensing results of the fabricated SiNB FETs employed as a biomolecular sensor for the early, real-time, and label-free screening of AFP can be understood in term of the change in charge density at the silicon nanobelt surface after functionalization. It is observed that, by tuning the gate voltage, the electrical linearity response of the system towards AFP extends its concentration range from 3ng/mL to 100ng/mL, allowing the screening of hepatocellular carcinoma (HCC). These results indicate that the detection of AFP under our direct, label-free, and ultrasensitive biosensor in a microfluidic channel could be one of the promising state-of-the-art techniques applicable as an AFP detector in real samples.

In Situ Planarization of Huygens Metasurfaces by Nanoscale Local Oxidation of Silicon

Metasurfaces are becoming a flourishing field of research, with diverse applications, such as planar optical components and structural colors. While metallic metasurfaces are typically few tens of nanometers in their thickness, their dielectric counterparts typically span few hundreds of nanometers in thickness variations. This makes the stacking of multilayers a bit challenging. To mitigate this challenge, we have developed a new approach for the realization of dielectric metasurfaces. Our approach is based on the nanoscale local oxidation of silicon (LOCOS), allowing to achieve planar metasurface structures. We have utilized this approach for the design, fabrication and characterization of amorphous silicon based all-dielectric Huygens metasurfaces. These metasurfaces show clear electric and magnetic resonances, which can be structurally tuned. The obtained results are in good agreement with numerical simulations taking into account the unique shape of the nanoantennas. Relying on a robust approach for ...

Characterization of LOCOS Field Oxide on 4H-SiC Formed by Ar Preamorphization Ion Implantation

In this letter, the electrical properties of local oxidation of silicon (LOCOS) field oxide formed on 4H-SiC are reported. Moreover, unlike the conventional Si LOCOS process, a simpler method based on Ar preamorphization implantation is proposed. In addition to direct characterization of the field oxide, device properties achieved using LOCOS isolation are compared with those achieved using the conventional chemical vapor deposition oxide isolation to clarify the impact of isolation technology. The results of this letter would be insightful for silicon-carbide-based very-large-scale integration technology.