Local Oscillator Harmonics Research Articles

An N-Path Filter Design Methodology With Harmonic Rejection, Power Reduction, Foldback Elimination, and Spectrum Shaping

In this paper, an adaptive design methodology for synthesizing a harmonic free N-path filter with reduced frequency folding is presented. System level analysis of proposed architecture shows that by adding a few extra paths with proper weights to a conventional N-path filter, several characteristics such as harmonic rejection, power reduction, foldback elimination and spectrum shaping can be achieved. The designed filter is reconfigurable to be a band-pass filter (BPF) or a band-reject filter (notch), based on the requirements. By using the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> harmonic of Local Oscillator (LO) signal, instead of the fundamental harmonic, the required input clock frequency in N-phase clock generator is reduced by a factor of n. As a proof of concept, a 0.1-5 GHz RF filter with 75 dB and 82 dB harmonic rejection at 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> and 5 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> order harmonics respectively is analyzed and simulated using MATLAB and Cadence Spectre-RF. Post-layout simulations are performed using CMOS 180 nm technology with 1.8 V supply voltage. The total power consumption of the chip is less than 8.5 mW while occupying a silicon area of 0.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Furthermore, Noise Figure (NF) of the circuit is shown to be between 3.5 and 4.7 dB and its out-of-band IIP3 is +6 dBm.

A Six-Phase Two-Stage Blocker-Tolerant Harmonic-Rejection Receiver

Modern wideband receivers need to operate linearly in the presence of strong out-of-band blockers. In this article, we introduce a blocker-tolerant harmonic rejection (HR) receiver, which can suppress blockers at the local oscillator harmonics. The suppression is achieved by applying the HR in two stages, such that the first HR already occurs at the first gain-stage output. The proposed receiver achieves this HR with a simple six-phase local-oscillator (LO) clocking. The proposed design also uses simple gain coefficients of ±1 while implementing HR in two stages that compensates for the mismatch effects of each stage. In addition, the near-band blocker linearity is improved by implementing a third-order baseband feedback response, which acts in conjunction with the $N$ -path filtering. Implemented in a 28-nm Fully-Depleted Silicon-on-Insulator (FDSOI) process, the receiver demonstrates the 18–37-dB HR from the first stage and 46–53 dB of HR in total. Furthermore, a blocker compression point (BCP) of 2.5 dBm for a third harmonic blocker and a near-band BCP of −6.5 dBm are achieved.

An Analog LO Harmonic Suppression Technique for SDR Receivers

A low-complexity analog technique to suppress the local oscillator (LO) harmonics in software-defined radios is presented. Accurate mathematical analyses show that an effective attenuation of the LO harmonics is achieved by modulating the transconductance of the low-noise transconductance amplifier (LNTA) with a raised-cosine signal. This modulation is performed through the bias network of a cascode device with a negligible increase in the LNTA noise figure. The proposed technique results in a notch at the third harmonic and at least 36 dB of attenuation at the fifth and the seventh harmonics. Experimental results in 130-nm CMOS and postlayout simulation results in 65-nm CMOS verify the proper functionality of the proposed technique and the accuracy of the proposed analyses.

A Mixed-Signal Circuit Technique for Cancellation of Interferers Modulated by LO Phase-Noise in 4G/5G CA Transceivers

In RF transceivers operating in carrier-aggregation, spurs are generated on the transceiver chip which may down-convert any blocker signal located at the spur frequency into the receiver baseband. The blocker signal could either be the transceiver’s own transmit signal when operating in frequency-division duplex, or a WiFi-related signal received by the antenna. This so-called modulated spur interference contains the phase-noise (PN) of the involved local oscillator harmonics which created the spur and leads to a degradation of the wanted RX signal. The presented mixed-signal circuit mimics the spur building law including the PN of the harmonics and is, therefore, able to provide a replica of the spur interference including PN modulated components. This replica is then used as a reference signal for the digital cancellation of the main and image modulated spur interference using a widely-linear (WL) cancellation structure. The proposed circuit technique is implemented in 28 nm LP CMOS technology, and measurement results show that the mixed-signal solution outperforms a digital-only WL cancellation with respect to PN cancellation even with high blocker power levels of −15 dBm at the input of the low-noise amplifier.

A Wideband Receiver Employing PWM-Based Harmonic Rejection Downconversion

A harmonic rejection (HR) receiver that utilizes discrete-level pulsewidth modulation (PWM) to implement a sinusoidal local oscillator (LO) with intrinsic HR is demonstrated. The PWM-LO is employed in a switching mixer. The receiver can be configured to provide additional HR, by employing multi-phase paths, with appropriate baseband gain coefficients. The PWM generator employs parallel delay-locked loops to implement a three-level natural-sampling dual-edge PWM sinusoidal LO signal, with rejection of the third, fifth, and seventh LO harmonics. Gain control using LO-path pulsewidth control is demonstrated. The design is implemented in a 40-nm CMOS process. The receiver gain with HR is 26.4–30.1 dB in multi-phase LO configuration and 28–31.8 dB in single-phase configuration. The double-sideband noise figure at peak gain is 5.8 dB. The design demonstrates worst case HR3 and HR5 ratios of 47 and 49 dB without calibration for $f_{\mathrm{ LO}}=100$ MHz in the multi-phase configuration, with a total power dissipation of 41.1 mW. With calibration, a single-phase peak harmonic rejection ratio (HRR) higher than 73 dB for the third, fifth, and seventh LO harmonics is demonstrated. Gain dependence of the HRR is studied.

A Blocker-Tolerant RF Front End With Harmonic-Rejecting $N$ -Path Filter

An RF front end with a harmonic-rejecting $N$ -path filter is presented. It features tunable narrow-band filtering and high attenuation at the third- and fifth-order local oscillator (LO) harmonics at the LNA output, which improves the blocker tolerance at LO harmonics. The 0.2–1 GHz RF front end is implemented in a 65-nm CMOS process. The blocker 1-dB compression point (B1dB) is −2.4 dBm at a 20-MHz offset, and remains high at the third- and fifth-order LO harmonics. The reverse isolation of the LNA helps keep the LO emission below −90 dBm. A two-stage harmonic rejection approach offers a >51 dB harmonic-rejection ratio at the third- and fifth-order LO harmonics without calibration.

Effect of Out-of-Band Blockers on the Required Linearity, Phase Noise, and Harmonic Rejection of SDR Receivers Without Input SAW Filter

The required linearity of wideband receivers for applications, such as software-defined radio in the absence of input surface-acoustic wave (SAW) filters, is studied. It is shown that the required linearity of wideband SAW-less receivers is surprisingly higher than what has been commonly assumed. For these receivers, although the out-of-band blockers can reduce the compression point of the receiver, they can also potentially generate interferers that appear in the desired frequency band, resulting in higher noise floor and signal corruption. The required out-of-band IIP2 and IIP3 of low-noise amplifier (LNA) and mixer for single and concurrent applications are analytically derived. The required wideband SAW-less receiver phase noise is also studied, and it is shown that blockers located at the frequencies of the local oscillator harmonics can significantly increase the noise floor of the receiver. The effects of input and intermediate filters on the above applications along with the conditions under which they help to alleviate the limitations of LNA and mixer are defined. The validity of the models and subsequent derivations is verified by actual measurements using a wideband SAW-less receiver.

An Interference-Resilient Wideband Mixer-First Receiver With LO Leakage Suppression and I/Q Correlated Orthogonal Calibration

A mixer-first receiver design in 28-nm CMOS is discussed. An embedded 5-bit mixer digital-to-analog converter provides wideband tuneability to enhance device matching and, hence, suppress the multiple local oscillator (LO) harmonics as well as to improve the overall image rejection (IR) performance. Two-stage baseband amplifiers support a 50-MHz baseband bandwidth, which covers the entire channel for long-term evolution non-contiguous carrier aggregation. The proposed design effectively reduce multiple LO harmonics down to below -62 dBm. The system achieves 2.6-dB noise figure, > 15-dBm out-of-band third-order input intercept point, and an IR ratio > 66 dB with 60-mW power, including five on-chip low dropout regulators.

Cognitive Cellular Systems: A New Challenge on the RF Analog Frontend

AbstractCognitive Cellular Systems are seen today as one of the most promising ways of moving forward solving or at least easing the still worsening situation of congested spectrum caused by the growing number of users and the expectation of higher data transfer rates. As the intelligence of a Cognitive Radio system is located in the digital domain – the Cognitive Engine and associated layers – extensive research has been ongoing in that domain since Mitola published his idea in 1999. Since, a big progress has been made in the domain of architectures and algorithms making systems more efficient and highly flexible. The pace of this progress, however, is going to be impeded by hard requirements on the received and transmitted signal quality, introducing ultimate challenges on the performance of the RF analog frontend, such as in-band local oscillator harmonics, ultra low sensitivity and ultra high linearity. The RF frontend is thus likely to become the limiting technical factor in the true realization of a Cognitive Cellular System. Based on short recapitulations of the most crucial issues in RF analog design for Cognitive Systems, this article will point out why those mechanisms become responsible for the limitation of the overall performance particularly in a broadband Cognitive Cellular System. Furthermore, as part of a possible solution to ease the situation, system design of a high intermediate frequency (IF) to UHF frequency converter for cognitive radios is discussed and the performance of such a converter analyzed as a proof of concept. In addition to successfully tackling some of the challenges, such a high-IF converter enables white space operation for existing commercial devices by acting as frequency converter. From detailed measurements, the capabilities in both physical layer and application layer performance of a high-IF frontend developed out of off-the-shelf components is explained and is shown to provide negligible degradation to the commercial device being connected to.

A sine-LO square-law harmonic-rejection mixer—theory, implementation, and application

A square-law harmonic-rejection mixer (SL-HRM) driven by a sine local oscillator (LO) is proposed for wideband and tunable rejection of all LO harmonics. The key performances including the gain, noise figure (NF), input-referred third-order intercept point (IIP3), and harmonic rejection ratio (HRR) with respect to the amplitude and purity of the sine-LO are analyzed. In the circuit level, the SL-HRM incorporates a voltage-boosted technique to surmount the gain and NF penalties of square-law mixing, while guaranteeing the device reliability via introducing a supply startup circuit and a node-voltage protection circuit. The entailed high-purity sine-LO is achieved via a digital-intensive square-to-sine LO generator plus a passive- RC low-pass filter. Fabricated in 65-nm CMOS, the VHF-/UHF-band SL-HRM has a tunable gain of 1-13 dB, associated with an NF of 27-15 dB, under an LO amplitude of 50-200 mV pp. The IIP3 is stable within from +6.5 to +7.6 dBm, as expected. The tunable HRR3 and HRR5 are 13-40 dB and 17-45 dB, respectively. The mixer core consumes 7.5 mW at 2.5 V, while the LO generator draws 3-6 mW at 1.2 V. The total active area is just 0.042 mm2.

A Harmonic-Rejecting CMOS LNA for Broadband Radios

The local oscillator harmonics corrupt the desired signal in broadband RF receivers by downconverting interferers. This paper proposes the notion of harmonic rejection in the front-end low-noise amplifier so as to relax the stringent matching required of harmonic-reject mixers. Described are frequency response shaping techniques by feedforward and unilateral Miller capacitance multiplication for a signal bandwidth of 100 MHz to 10 GHz. A calibration algorithm is also proposed for the tuning of the frequency response. An experimental prototype fabricated in 65-nm digital CMOS technology provides at least 20 dB of rejection while consuming 8.64 mW with a 1.2-V supply.

A 130-nm CMOS 100-Hz–6-GHz Reconfigurable Vector Signal Analyzer and Software-Defined Receiver

A monolithic 100-Hz-6-GHz reconfigurable vector signal analyzer (VSA) and software-defined receiver (SDR), following a two-step up-down conversion heterodyne scheme with robustness to various wideband interference scenarios and local oscillator (LO) harmonic mixing, is presented. The 130-nm CMOS chip does not require external filters or baseband processing to reduce the effect of interferences or LO harmonics. The receiver has tunable gain from -67 to 68 dB in steps of 0.5 dB, and tunable bandwidth from 0.4 to 11 MHz in steps of 0.5 MHz. The receiver sensitivity at the maximum gain is - 82 dBm. A monolithic VSA/SDR enables various commercial and military wireless solutions.

Design of Cognitive Radios

Cognitive radios are expected to perform spectrum sensing and communication in the frequency range of tens of megahertz to about 10 GHz. As such, they pose tough architecture and circuit design problems. This paper deals with issues such as broadband, low-noise amplification, multidecade carrier frequency synthesis, and spectrum sensing. The paper also describes the effect of nonlinearity and local oscillator harmonics, demonstrating that cognitive radios entail more difficult challenges than do software-defined radios. Multi-decade synthesis techniques and RF-assisted sensing methods are also presented.

DESIGN OF A MICROSTRIP BALANCED MIXER FOR SATELLITE COMMUNICATION

The design and measured results of a compact, low cost, low conversion loss microstrip single balanced Schottky diodes mixer is proposed. This mixer is designed for Ka-band satellite transponder simulator to convert the 30GHz radio-frequency (RF) signal down to the 20GHz intermediate-frequency (IF) signal with 9.8GHz local oscillator (LO) frequency. This design takes full advantage of the frequency relationship of the RF, IF and LO, which is 3 : 2 : 1. A microstrip rat-race ring is designed at the LO frequency, which also functions as a 180-degree hybrid coupler at the RF frequency by its intrinsic multi-band characteristic. The amplitude and phase balance at both LO and RF frequency are analyzed, which guarantee the state- of-art performance of this single balanced mixer. The multi-function open/short stubs and a lowpass fllter (LPF) with bonding wires across the rat-race ring are optimized to realize this low conversion loss mixer. The measured results show that the conversion loss is less than 9dB at the IF frequency from 20.0 to 21.6GHz, and the power of the second harmonic of LO is i45dBm with +6:5dBm LO drive power. The 3rd order inter-modulation products (IMD3) could be lower than i50dBc with LO power higher than +7:8dBm at the input RF power of i15dBm.

A CMOS Harmonic Rejection Mixer With Mismatch Calibration Circuitry for Digital TV Tuner Applications

A harmonic rejection mixer with mismatch calibration circuitry in direct-conversion receiver architecture for digital TV tuner applications is designed and fabricated in 0.18-mum CMOS technology. Odd harmonic mixing in the 48-862 MHz digital TV frequency band between the input signal and the local oscillator harmonics is a critical problem for direct-conversion receivers which require a harmonic rejection of over -60 dBc for ATSC terrestrial and cable digital TV standards. Without calibration, harmonic rejection mixers show a rejection ratio of the third and fifth harmonics in the range of -30 to -40 dBc due to phase and/or gain mismatch. The implemented harmonic rejection mixer with the proposed calibration circuitry consistently achieves more than -70 dBc of third harmonic rejection without degrading other performances such as gain, noise figure, linearity, and power consumption.

A Miniaturized Low-Cost 60–1000-MHz PCB Spectrum Analyzer

This paper presents the development of a printedcircuit-board (PCB) spectrum analyzer for analyzing the radio frequency (RF) input power in a spectral range of 60-1000 MHz. The architecture is based on a standard superheterodyne receiver and is implemented on a low-cost, four-layer, FR-4 PCB. The design uses a frequency-hopped superheterodyning technique to prevent strong local-oscillator harmonics from causing spurs in the spectrum output. The system has a minimum detectable signal of -98 dBm and fits on a PCB with a form factor equivalent to a half-size PCI card. The resolution bandwidth is 7 kHz, and the dynamic range varies from 30 dB at 30-kHz offset to >62 dB for over 30-MHz offsets. This RF PCB spectrum analyzer is entirely constructed of commercial off-the-shelf components, enabling the design to be low-cost and low-power (3.66-W dc).

최소 삽입 손실을 갖는 국부 발진기 고조파 제거를 위한 병렬 결합 전송 선로 대역 여파기의 설계 및 제작

일반적인 여파기는 대역폭과 원하지 않는 신호들의 억압이 더 중요한 반면, 국부 발진기 여파기의 경우, 차단 주파수에서의 억압이 중요한 척도가 되며, 이 때 대역폭은 통과 대역 주파수에서 삽입 손실을 최소화하도록 설계한다. 본 논문에서는 이러한 특수성을 고려한 대역 여파기의 설계 절차를 보였다. 또한, 대역 여파기 제작 시 알 수 없는 기생 성분으로 인해 원하지 않는 결과를 야기시켜 제작 후의 조정이 이루어지게 된다. 따라서 이러한 문제점을 고려하여 Momentum에 근거한 제작 이전의 설계적인 조정 절차를 제시하였다. In this paper, we present the design procedure of BPF(Band Pass Filter) for the suppression of LO(Local Oscillator) harmonics. The required suppression at given harmonics is the key issues in such a filter design, while the bandwidth and the suppression of the unwanted signals are more important in the conventional RF filter design. In LO filter design the bandwidth is used for the minimization of the insertion loss for the desired signal. In addition, we propose the novel tuning procedure based on Momentum to consider the unknown parasitic effects, which usually are not included in the circuit design step and results in undesirable and frustrating tuning after fabrication.

Harmonic mixing at mm waveband in a high temperature superconducting grain boundary Josephson junction

Using a high Tc superconducting grain boundary Josephson junction, harmonic mixing experiments in the mm waveband were carried out, aiming at as large a harmonic number and as high a signal frequency as possible. The dependencies of intermediate frequency output on dc bias, harmonic number, frequency of local oscillator (LO), and other parameters were carefully studied. Until now, our best result was the mixing between the signal at 95 GHz and the 105th harmonic of LO at about 900 MHz. Preliminary experiments using a high Tc harmonic mixer and phase-locking loop were tried to stabilize the frequency of a mm wave source.

Embedding impedance approximations in the analysis of SIS mixers

The adequacy of three approximations to J.R. Tucker's (1979) quantum theory of mixers is examined. They are: (i) the usual three-frequency approximation, which assumes a sinusoidal local oscillator (LO) voltage at the junction and a short-circuit at all frequencies above the upper sideband; (ii) a five-frequency approximation, which allows two LO voltage harmonics and five small-signal sidebands; and (iii) a quasi five-frequency approximation in which five small-signal sidebands are allowed, but the LO voltage is assumed sinusoidal. These are compared with a full harmonic-Newton solution of Tucker's equations, including eight LO harmonics and their corresponding sidebands, for realistic SIS (superconductor-insulator-superconductor) mixer circuits. It is shown that the accuracy of the three approximations depends strongly on the value of omega R/sub N/C for the SIS junctions used. For omega R/sub NC/ values in the range 0.5-10, the range of most practical interest, the quasi five-frequency approximation is a considerable improvement over the three-frequency approximation, giving results very close to those of the eight-harmonic solution, and should be suitable for much design work.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>