Wafer Loading Research Articles

An Efficient Binary Integer Programming Model for Residency Time-Constrained Cluster Tools With Chamber Cleaning Requirements

Cluster tools play a significant role in the entire process of wafer fabrication. As the width of circuits in semiconductor chips shrinks down to less than 10nm, strict operational constraints are imposed on the operations of cluster tools in order to ensure the quality of processed wafers. Particularly, wafer residency time constraints and chamber cleaning requirements are commonly seen in etching, chemical vapor deposition, coating processes, etc. They make the scheduling problem of cluster tools more challenging. This work aims to provide a solution for dual-arm cluster tools with wafer residency time constraints and chamber cleaning requirements. To do so, it proposes a novel virtual wafer-based scheduling method. By this method, under a steady state, a PM processes either a real or virtual wafer at a time. When a PM processes a virtual one, its chamber can perform a cleaning operation. In this way, we can meet not only the strict residency time constraints for real wafers, but also innovatively meet chamber cleaning requirements. Based on such a novel scheduling method, an efficient binary integer programming model is established to optimize the throughput of cluster tools. Finally, experiments are performed to show the efficiency and effectiveness of the proposed method. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Note to Practitioners</i> —To ensure wafer quality in semiconductor manufacturing, engineers have to impose wafer residency time constraints and chamber cleaning requirements on the operations of cluster tools. In order to tackle their scheduling problem with these constraints, this work proposes a novel method based on the use of virtual wafers. Under a one-cyclic schedule obtained for time-constrained cluster tools without chamber cleaning requirements, virtual wafers are loaded into the tool such that when a PM processes a virtual wafer, a chamber cleaning operation can be performed in practice. The key to solve this scheduling problem is to find a wafer loading sequence with the highest performance in terms of cycle time. To do so, this work establishes an efficient binary integer programming model to search for such a solution. Since the obtained solution is a periodical wafer loading sequence based on a one-wafer cyclic schedule, it can be easily implemented. Therefore, this work has a high practical value to numerous semiconductor manufacturers.

Scheduling of Single-Arm Cluster Tools with Residency Time Constraints and Chamber Cleaning Operations

To ensure wafer quality, engineers have to impose wafer residency time constraints and chamber cleaning operations on cluster tools; this has been widely used in semiconductor manufacturing. Wafer residency time constraints and chamber cleaning operations make the scheduling problem of cluster tools more challenging. This work aims to solve such a scheduling problem for single-arm cluster tools and presents a novel method based on the use of virtual wafers. Under a one-cyclic schedule obtained for single-arm cluster tools without chamber cleaning requirements, virtual wafers are loaded into the tool such that when a process module (PM) processes virtual wafers, a chamber cleaning operation is performed in practice. The key to solve this scheduling problem is to find a wafer loading sequence with the highest performance in terms of cycle time. With this idea, this work constructs a genetic algorithm to search for such a solution. Since the obtained solution is a periodical wafer loading sequence based on a one-wafer cyclic schedule, it can be easily implemented. Therefore, this work has high practical value to numerous semiconductor manufacturers. Experiments were performed to show the efficiency and effectiveness of the proposed method.

EUV-induced hydrogen plasma: pulsed mode operation and confinement in scanner

In recent years, EUV lithography scanner systems have entered high-volume manufacturing for state-of-the-art integrated circuits, with critical dimensions down to 10 nm. This technology uses 13.5-nm EUV radiation, which is shaped and transmitted through a near-vacuum H2 background gas. This gas is excited into a low-density H2 plasma by the EUV radiation, as generated in pulsed mode operation by the laser-produced plasma in the EUV source. Thus, in the confinement created by the walls and mirrors within the scanner system, a reductive plasma environment is created that must be understood in detail to maximize mirror transmission over the lifetime and to minimize molecular and particle contamination in the scanner. In addition to the irradiated mirrors, reticle, and wafer, the plasma and radical load to the surrounding construction materials also must be considered. We provide an overview of the EUV-induced plasma in the scanner context. Special attention is given to the plasma parameters in a confined geometry, such as that found in the scanner area near the reticle. It is shown that plasma confinement and resulting contributions from secondary electron emission delay the formation of the plasma sheath and thereby reduce the peak ion energies to below the sputtering threshold for mirrors and construction materials. Furthermore, for a confined pulsed plasma with a pulse period shorter than the decay time of the plasma, the plasma consists of a quasi-steady-state cold background plasma and periodic transient peaks in ion energy and ion flux. In terms of modeling, this means that no assumptions can be made on the electron distribution functions and a (Monte-Carlo) particle-in-cell (PIC) model is needed. We present an extension of the PIC model approach to complex three-dimensional geometries and to multiple pulses using a hybrid PIC-diffusion approach. Also, the translation of these specific plasma parameters to off-line setups and the aspects that must be included to make a meaningful translation from off-line laboratory EUV setups to the scanner plasma are discussed.

Influence and Suppression of Harmful Effects Due to By-Product in CVD Reactor for 4H-SiC Epitaxy

Suppression of harmful effect due to by-product on homo-epitaxial growth of 4H-SiC films using a high speed wafer rotation vertical CVD method was demonstrated. Influence of by-product, such as 3C-SiC deposit on a hot-wall and Si deposit on gas nozzles, formed during the epitaxial growth was investigated in two comparative studies. The analysis of triangular defects with 3C-SiC down-falls on the films revealed that the most of the down-falls which were peeled from the hot-wall adhered to the wafers before the epitaxial growth. By increasing the wafer rotation speed to 300 rpm just after wafer loading into the reactor, the down-falls dropped towards the wafer surface were effectively eliminated, and the maintenance period of the reactor could be increased more than 4 times compared to the case of maintaining the wafer rotation speed of 50 rpm until just before epitaxial growth step. Additionally, the relationship between Si deposit formed on the gas nozzles in the gas inlet and fluctuation of thickness and doping concentration of the films suggested that Si deposit formed on the gas nozzles acts as a trap site of Si source gas. By suppression of the Si deposit using optimizing gas flow condition, no significant fluctuation of thickness and doping concentration of the films were observed and the maintenance period of the gas nozzles could be increased more than 3 times compared to the epitaxial growth using the nozzles on which Si deposit was formed.

Wafer Delay Analysis and Workload Balancing of Parallel Chambers for Dual-Armed Cluster Tools With Multiple Wafer Types

We examine a scheduling problem for a dual-armed cluster tool that processes multiple similar wafer types concurrently. It has been recently proved that the well-known swap sequence, which is widely used for single wafer type processing, also minimizes the cycle time for concurrent processing. In this article, we wish to minimize wafer delays in a process chamber, which are critical to wafer quality degradation, while maintaining the minimum cycle time. In particular, we show that concurrent processing of wafers with different processing times complicates the analysis of wafer delays significantly, and the wafer delays can be remarkably reduced by finding a proper cycle plan which is the release sequence of different wafer types. We first characterize wafer delays for a given cycle plan by analyzing the circuits of the timed event graph (TEG) model. From this, we prove that concurrent processing of wafers may cause a significant workload imbalance between parallel chambers of a process step, and hence the wafer delays increase substantially. We present that the wafer delays are minimized by a cycle plan that evenly balances workloads between parallel chambers. We also propose how wafer loading task at each process step has to be postponed to meet wafer delay constraints while maintaining the minimum cycle time. Note to Practitioners —Wafer quality control has become an essential fab operational problem in semiconductor manufacturing industry. In cluster tools, which are dominantly being used for diverse wafer fabrication stages, it has been proven that the wafer delays within process chambers have a crucial impact on the wafer quality. Accordingly, modern fabs have introduced stringent quality control to regulate wafer delays in cluster tools. In this research, we propose a scheduling strategy to minimize the wafer delays when a cluster tool concurrently processes multiple wafer types. We first show that the release sequence of different wafer types significantly impacts the wafer delays under concurrent processing, and we then propose how these wafer delays can be minimized by finding the optimal wafer release sequence.

Mechanism of PVA Brush Loading with Ceria Particles during Post-CMP Cleaning Process

Brush scrubbing is a well-known post CMP cleaning process. Interaction between PVA brush and the particles removed during the process must be considered while designing a cleaning process. In this work, the effect of cleaning solution pH was investigated in terms of particle removal from the wafer and subsequent loading to the PVA brush nodule. Higher cleaning of particles from wafer was observed for pH 2 and 12 cleaning solutions and poor cleaning for pH 7 cleaning solution. In contrast, the brushes were loaded heavily for pH 7 compared to pH 2 and 12. Higher electrostatic attraction between oppositely charged PVA and ceria surfaces provided higher ceria particles loading to PVA brush in acidic and neutral cleaning solutions. This particle loading to PVA brush can further effect cleaning efficiency as well as cross-contamination.

Epitaxial Ge thin film Growth on Si Using a Cost-Effective Process in Simplified CVD Reactor

Germanium on silicon has the potential to enable growth of high quality group IV semiconductors for the field of silicon photonics by being used as virtual buffers. In addition Ge layers can be used in the fabrication of passive components such as waveguides and resonators. A cost-effective technology for the heteroepitaxial growth of Ge on Si will be highly beneficial. In this work, a simplified chemical vapor deposition reactor was assembled in-house to deposit Ge films. Epitaxial Ge film growth on Si (100) substrates was accomplished without requiring ultra-high vacuum conditions or a high temperature substrate pre-deposition bake thereby minimizing the economic and thermal budget of the process. Films were deposited using digermane (Ge2H6) precursor in a single step at a process temperature of 350 °C and chamber pressures of 1–10 Torr. Films were achieved at high chamber background pressures (>10−6 Torr) by implementing a thorough ex situ substrate cleaning process and optimizing times for wafer loading, chamber pumping and initiation of film deposition. Transmission electron microscopy and X-ray diffraction were used to confirm the epitaxial growth and crystalline quality of the obtained films. Optical properties of the films were characterized using Raman spectroscopy, Photoluminescence and Infra-red spectroscopy.

(Invited) Recent Advances in SiC CMP

The need for high-quality single crystal SiC substrates continues to grow as the demand for SiC-based power and RF devices increases. The physical properties of SiC result in better thermal conductivity, higher breakdown voltage, faster switching performance and lower resistivity when compared to similar devices based on silicon. Even with the performance advantages, the adoption rate of SiC is slowed by high cost and inherent difficulty of processing the material. Conventional processing of SiC substrates involves double-sided batch lapping followed by batch diamond polishing then final polishing with a non-diamond slurry to achieve an epi-ready surface. This process flow involves multiple process tools and is fraught with issues including the need for wafer sorting to group wafers by thickness, manual loading and unloading of wafers, low yields, and unacceptable risk of batch loss (an entire batch of wafers may be scrapped if even one wafer cracks or breaks during process). This paper presents an improved process for single-wafer CMP during SiC substrate manufacturing or backside thinning. In contrast to batch polishing, key improvements include individual wafer processing, fully-automated handling, and elimination of the need for wafer sorting and grouping by thickness. Recent development efforts have achieved removal rates for the 4H Si face up to 2.5 µm/hour for the first step CMP. Removal rates for the C-face can be as much as 3-4x higher consistent with other findings in the industry. Fig 1 shows surface finish after the polishing sequence is complete which is consistently at or below 1 Å Ra as measured by AFM. The combination of an optimized grind followed by an optimized CMP process provides a viable path to both improving wafer yield and reducing costs for SiC wafer manufacturing or backside thinning process sequences. Figure 1

Scheduling Dual-Armed Cluster Tools With Chamber Cleaning Operations

Circuit widths and nodes of semiconductor wafers have been continually shrinking down to less than 20 nm. Therefore, modern wafer fabs enforce extremely strict process control to prevent wafer quality failures. A wafer processing chamber is now frequently cleaned to remove residual chemicals and impurities. Yu et al. show that such cleaning operations significantly change the tool operation of single-armed cluster tools, and they suggest an idea of partial wafer loading to improve the tool throughput under cleaning requirements. However, little is known about how a dual-armed tool could be effectively scheduled when chamber cleaning exists. A dual-armed robot allows more flexible tool operational sequences, and hence, the scheduling problem becomes further complicated and challenging. In this paper, we propose a scheduling method by which the dual arms can be properly exploited for better tool productivity. We show that the suggested hybrid sequence significantly reduces the tool cycle time as compared to previously developed scheduling methods. Through this research, we conclude that the productivity gain of the dual arms against single arm is more significant when chambers are cleaned. Note to Practitioners —This paper is motivated by the scheduling issues of cluster tools with chamber cleaning requirements. Though an efficient scheduling method for single-armed cluster tools is presented by Yu et al. , its performance is not sufficiently close to the optimal when a dual-armed robot is considered. More specifically, we cannot expect any productivity improvement from adopting a dual-armed robot, although it allows more flexible tool operations and is known to have higher throughput than a single-armed robot. Thus, we propose a novel scheduling method for dual-armed cluster tools that require chamber cleaning operations. The experimental results show that the suggested method achieves optimal tool throughput in most of the practical tool conditions.

Scheduling Single-Armed Cluster Tools With Chamber Cleaning Operations

Circuit widths and nodes of semiconductor wafers have been continually shrinking down to less than 20 nm. Therefore, modern wafer fabs enforce extremely strict process control to prevent wafer quality failures. A wafer processing chamber is now frequently cleaned to remove residual chemicals and impurities. Yu et al. show that such cleaning operations significantly change the tool operation of single-armed cluster tools, and they suggest an idea of partial wafer loading to improve the tool throughput under cleaning requirements. However, little is known about how a dual-armed tool could be effectively scheduled when chamber cleaning exists. A dual-armed robot allows more flexible tool operational sequences, and hence, the scheduling problem becomes further complicated and challenging. In this paper, we propose a scheduling method by which the dual arms can be properly exploited for better tool productivity. We show that the suggested hybrid sequence significantly reduces the tool cycle time as compared to previously developed scheduling methods. Through this research, we conclude that the productivity gain of the dual arms against single arm is more significant when chambers are cleaned. Note to Practitioners —This paper is motivated by the scheduling issues of cluster tools with chamber cleaning requirements. Though an efficient scheduling method for single-armed cluster tools is presented by Yu et al. , its performance is not sufficiently close to the optimal when a dual-armed robot is considered. More specifically, we cannot expect any productivity improvement from adopting a dual-armed robot, although it allows more flexible tool operations and is known to have higher throughput than a single-armed robot. Thus, we propose a novel scheduling method for dual-armed cluster tools that require chamber cleaning operations. The experimental results show that the suggested method achieves optimal tool throughput in most of the practical tool conditions.

A Low-Cost, Automated Wafer Loading System With Submicron Alignment Accuracy for Nanomanufacturing and Nanometrology Applications

This paper introduces a low-cost, automated wafer alignment system capable of submicron wafer positioning repeatability. Accurate wafer alignment is critical in a number of nanomanufacturing and nanometrology applications where it is necessary to be able to overlay patterns between fabrication steps or measure the same spot on a wafer over and over again throughout the manufacturing process. The system presented in this paper was designed to support high-throughput nanoscale metrology where the goal is to be able to rapidly and consistently measure the same features on all the wafers in a wafer carrier without the need for slow and expensive vision-based alignment systems to find and measure the desired features. The wafer alignment system demonstrated in this paper consists of a three-pin passive wafer alignment stage, a voice coil actuated nesting force applicator, a three degrees-of-freedom (DOFs) wafer handling robot, and a wafer cassette. In this system, the wafer handling robot takes a wafer from the wafer cassette and loads it on to the wafer alignment stage. The voice coil actuator is then used to load the wafer against the three pins in the wafer alignment system and align the wafer to an atomic force microscope (AFM)-based metrology system. This simple system is able to achieve a throughput of 60 wafers/h with a positional alignment repeatability of 283 nm in the x-direction, 530 nm in the y-direction, and 398 nm in the z-direction for a total capital cost of less than $1800.

(Invited) Optimal Target Functions for Epitaxy in New Channel Applications Such As Horizontal Gate-All-Around (h-GAA) Device Architectures Using Nano-Sheets or Nanowires

Continuation of Moore’s law, an observation of the economics and technological progress in semiconductor manufacturing, is becoming increasingly challenging due to many factors, since it is getting harder to advance the 3 technological P’s and the economic P: Performance/Watt, Precision, Perfection and Price/Transistor [JY Chen, Proc. of SPIE Vol. 8522 (2012) 852202]. Epitaxy allows precise control of the critical dimension(s) in new channel applications (h-GAA device architectures and epitaxially defined FinFETs), directly impacting Device Performance and Yield (DPY) and Cost of Ownership (CoO). "Target functions" include: (1) Uniformity and repeatability (perfection & precision) of thickness and composition, (2) abruptness of SL stack (precision & perfection), (3) crystalline perfection (absence of gas phase nucleation potentially causing defects), (4) Cost of Ownership (CoO) including precursor conversion (determining precursor consumption and waste) and throughput (TP) {wph=60min/(toverhead + tprocess)}, and (5) only applicable to self-aligned selective epitaxial growth (SEG) processes on structured topographies: (a) selectivity, (b) macro- and micro loading, (c) doping level & distribution (d) different shapes: faceting vs. conformality (perfection). Tight control of the critical dimension (epitaxial thickness) its distribution WiW (uniformity, perfection) and WtW (repeatability, precision) are essential for high volume manufacturing [WS Yoo, RTP’06, pp. 159-175]. Analyzing growth rate dependence on temperature (T) with an Arrhenius plot, two distinct growth regimes can be identified: (a) In the ‘low-T’, reaction rate (kinetic) limited regime growth rate is limited by the density of ‘free’ surface sites (1-σH/Cl) available for precursor absorption, thus by the rate of H2/HCl desorption from the surface. Precursor is offered in abundance, conversion rate is low, growth is slow and film uniformities are strongly correlated with thermal uniformity, making T-control (WiW & WtW) the single most important item. {Massive and slow hot wall systems operating in thermal equilibrium provide such T conditions, but challenges include (i) deposit build-up on hot quartz tubes, (ii) sub-optimal pre-clean strategy and difficult Q-time control may result in defective films and degraded particle performance.} (b) In the ‘high-T’, mass flow limited regime growth is fast and only limited by precursor supply and is quite in-sensitive to T variations/excursions (WiW & WtW). High precursor conversion accompanied with depletion of reactants, as they flow over hot surfaces, mandates wafer rotation and a ‘favorable’ flow pattern in order to achieve good WiW uniformities. Precision & Perfection (impacting DP&Y): The interface abruptness of the as grown SiGe/Si super-lattice (SL) is mainly controlled by Ge surface segregation, rather than bulk inter-diffusion. Surface segregation, a thermally activated exchange reaction between surface and sub-surface atoms, is governed by (a) phonons (lattice vibrations => growth temperature), (b) ‘burying rate’ (time constant => growth rate) and (c) H/Cl surface coverage (acting as surfactants). Process flows minimizing channel material loss (thinning and tapering) require: (a) SL stacks with sharp ‘as-grown’ alloy transitions and sufficient material contrast [Δ Ge], (b) well controlled thermal budget (T*t) and (c) a wet or dry etch chemistry (process) with high etch rate selectivity for sacrificial layer removal. Conversely, (i) imperfect alloy transitions, (ii) excessive thermal budget causing inter-diffusion (or even strain relaxation in metastable strained SiGe layers) and (iii) poor etch rate selectivity will cause deleterious channel thickness variations ultimately leading to increased device variability. Requirements for crystalline perfection of channel materials are far more stringent compared to S/D SEG. The tolerance for crystalline defects is virtually zero, requiring strict suppression of any gas phase nucleation or excessive reactor wall coating. Cost of Ownership (CoO): Precursor conversion (and related precursor consumption = cost) speaks for itself. Reducing precursor flow and reducing deposition on hot parts, other than the wafer itself, yields cleaner processing (and likely fewer particles) and might allow reducing intensity and/or frequency of chamber cleaning time. Throughput (TP) is impacted by both, overhead and processing time, thus isothermal processing (or within a small T range for low-T chamber clean, wafer load, pre-epi surface treatment, epitaxial growth and unload) minimizes timefor T ramps and T stabilization. Thermal budget is reduced, thanks to low-T pre-epi surface preparation and reduced processing time (faster growth). Strategies to meet all essential value criteria have been developed and experimentally demonstrated for a single wafer tool. Epitaxial process conditions have been studied over a quite wide range of process conditions. Repeatability (precision) of SiGe & Si thickness, [Ge] and its WiW distributions (perfection) as well as crystalline perfection have been demonstrated using Spectroscopic Ellipsometry and Light Scatterometry (SP3, <32nm defect size). Composition & thickness are controlled by HR-XRD. STEM is used to assess abruptness (perfection) of SiGe/Si SL interfaces and layer thicknesses (precision).

두께 균일도 향상을 위한 LPCVD 챔버 내 웨이퍼 온도 분포 분석

The wafer temperature and its uniformity inside the LPCVD chamber were analyzed. The temperature uniformity at the end of the wafer load depends on the heat-insulating cap. The finite difference method was used to investigate the radiation and conduction heat transfer mechanisms, and the temperature field and heat diffusion in the LPCVD chamber was visualized. It was found that the temperature uniformity of the wafers could be controlled by the size and distance of the heat-insulating cap.

Scheduling Cluster Tools for Concurrent Processing of Two Wafer Types

We examine a scheduling problem of cluster tools that concurrently process two wafer types in a cyclic operational sequence. Whereas the process steps for different wafer types are assigned to different processing modules (PMs), the wafer loading and unloading tasks at the PMs are performed by a single robot. For a given cycle plan, which is a mix of different wafers for each cycle, we wish to determine the robot task sequence so as to minimize the tool cycle time. When a single wafer type is processed, the backward and swap sequences are optimal for single-armed and dual-armed tools, respectively. They are being prevalently used because of their simplicity and robustness. To maintain such advantages in concurrent processing, we introduce and define the concurrent backward and swap sequences (CBSs and CSSs, respectively). We then develop conditions on process times, robot task times, and the number of wafers produced in a cycle for which such CBSs and CSSs are still optimal for concurrent processing. We also show that, for some special cases, the two wafer types can achieve their maximum throughput rates as if each wafer type exclusively uses the tool regardless of other wafer types in progress. When the developed conditions do not hold, an effective mixed integer programming (MIP) model based on the CBSs and CSSs is used for robot task sequencing. Finally, we experimentally verify its efficiency and effectiveness by comparing to the existing scheduling methods for optimal scheduling of cluster tools.

Impact of Recipe Restrictions on Photolithography Toolsets in an ASIC Fabrication Environment

In this paper, a detailed discrete event simulation model is used to better understand the effects of recipe constraints resulting from process restrictions and tool capabilities on overall average cycle time performance of a photolithography area and on average cycle times of individual mask layers. The study is motivated by the industry, in which engineers have to frequently make decisions on tool qualifications and recipe coverage. An experimental procedure is developed and implemented to show the impact of different levels of tool paths on photolithography toolsets. The simulation results show that increasing the number of tool paths decreases the overall average photolithography cycle time for particular wafer loading levels. Also, as start volumes increase, toolset utilizations increase and the impact of single-path tools on average cycle times increases. Immature processes and low-use processes tend to have more single paths and thus suffer higher average cycle times accordingly. Furthermore, it is reported that average cycle time decreases significantly under multiple process environments due to the lower impact of single paths.

Water Vapor Delivery to Vacuum Process for Photovoltaic Applications

Oxide films are an important aspect of modern solar cells, providing passivation layers that increase cell efficiency. Uniformity of these layers is essential and affected by the distribution of gas species within the furnace. As the wafer load has gone up and wafer-to-wafer spacing has gone down, uniformity has become a concern. To address this, manufacturers are turning to sub-atmospheric furnaces. This in turn requires delivery of liquid source chemicals into sub-atmospheric pressure.This study describes tests performed on a Steamer to determine the ability of that device to deliver a set steam flow rate in a controlled manner. Multiple tests under atmospheric and vacuum pressure conditions show that the Steamer can reliably deliver steam to a sub-atmospheric process.

SiGe Epitaxy on a 300 mm Batch Furnace

This work reports the feasibility of silicon and silicon germanium epitaxy using an ASM A412(TMa) LPCVD all quartz, hot wall, vertical batch furnace reactor using 100 wafer product loads. The very same furnace can be used for 25 wafer and 200 wafer load size, without any hardware changes, dependant on production needs. Following this approach a significant cost reduction for epitaxy in 300 mm high volume manufacturing is possible and enables new applications. The native oxide of the substrate was removed by wet chemical cleaning with time coupling of less than 1 h and subsequent in-situ low pressure hydrogen anneal prior to Si or SiGe deposition. The epitaxial layers were grown using silane and germane. The Si and SiGe layers have been characterized with ToFSIMS, XRD, Raman, AFM and TEM confirming excellent crystalline quality, layer thickness and within wafer SiGe stoichiometry uniformity.

HF contamination of 200 mm Al wafers: A parallel angle resolved XPS study

In this work, 650 nm thick Al layers were deposited on 200 mm wafers and intentionally contaminated by exposure to controlled HF airborne concentrations in different humidity conditions. The layers were deposited with an industrial tool, in real clean room conditions. The real dose of HF contaminant was controlled on Al surfaces by LPE-IC (Liquid Phase Extraction in ultra-pure water and analysis by Ionic Chromatography). Several contaminant dose and humidity conditions were investigated and the layers were characterized over time by PAR-XPS parallel angle resolved XPS. Thanks to the full wafer loading capacity of our XPS spectrometer, the XPS measurements were synchronised very quickly after the deposition step. This allowed us to access to the first stage of the oxide/contaminated layer growth that occurs during the storage. Al–F interactions mechanisms were addressed in terms of bounding environment and oxidation/contamination competition. The parallel angle resolved capability of our spectrometer has been used to acquire a great number of angles simultaneously and then to access to accurate and significant depth resolved informations [9]. Relative depth plots profiles were then obtained from angle resolved data, giving detailed informations about the depth repartition of the chemical components, as well as their possible relative interactions. Fluorine repartition with depth has been especially studied. The aging in time of the contaminated layer has been investigated too, from the layer deposition/contamination point onto several days. Fluorine atomic percentage has been monitored at several points as well as the evolution in time of the depth profile of the fluorine components of the contaminated layer.

Leveraging new SEMI standard to reduce waste and improve flow for semicoductor manufacturing

A successful cutting-edge semiconductor manufacturer applies Lean principles with the goal set on perfecting its operation flow. In 2007 SEMI adopted a new standard E94-1107 that breaks the dependency between carrier and lot for processing wafers and formally introduces material redirection, which creates several opportunities for waste reductions and improved WIP handling. As depicted from simulations, the new standard is impacting several KPIs including throughput, cycle time, yield, and Just-In-Time customer response. This paper discusses different lean optimizations leveraging the new standard. Some tools require loading of many wafers simultaneously to achieve a high throughput. Although with reducing lot sizes, takt time can be improved, the sequential nature of these tools become limited by the number of load ports and thus have a negative impact on the equipment effectiveness. Before the new standard implementation, no carrier could be removed from load ports during processing to allow other carriers to load or unload wafers leaving the ports blocked. With this change, we can now remove the carrier from the Load Port after unloading wafers into the tool to allow filling the tool with the optimum number of wafers. Over the years, numerous lean manufacturing studies have been performed in terms of determining the correct lot size (number of wafers in a lot) to meet the Just-In-Time targets. Simulation runs demonstrate that smaller lots have up to 33% and 50% improved cycle time for batch tools and single wafer tools, respectively. Based on fluctuations in demand, there may not only be a need to speed up, but also to slow down production quickly. All these have direct correlation with scheduling of right sized lots (dynamic lot sizing), carefully planned delivery of carriers for processing and improved pull production techniques.

Throughput Considerations for In-Situ Doped Embedded Silicon Carbon Stressor Selectively Grown into Recessed Source Drain Areas of NMOS Devices

In this paper we calculate throughput based on recipe overhead (chamber etch, wafer load, wafer bake, cool down, unload) and deposition time for "true" SEG or the core cycle time (deposition, purge, etch, purge times) for a CDE process. In the latter case an average, effective growth rate (GR) can be extracted by dividing the deposited thickness per cycle by the cycle time. In high volume manufacturing (HVM) high SEG GR are necessary for high throughput and low Cost of Ownership (CoO). High GR also enable high substitutional carbon levels [C]sub in dilute Si:C alloys. In this work all experiments were exclusively performed using Silcore® (ASM trademarked version of Si3H8). Due to the high GR at low process temperature, high [C]sub and low films resistivities can be obtained independent of the two different Cl containing etch chemistries that were used in this study. The main challenge of using Cl2 compared to the ASM proprietary etch chemistry is the 25-30 times lower etch rate selectivity (~7 vs. ~190) of a-SiCP over epi-SiCP. As a result of the low etch rate selectivity using a Cl2 etch chemistry, a significant portion of the epitaxial SiC:P is also etched with the a-SiCP. This results in a low effective growth rate which has a deleterious impact to throughput.