Load Current Tracking Research Articles

Ultra-low power low-dropout linear regulator with a load current tracking bias current generator for loT devices

This paper presents an ultra-low power low-dropout (LDO) linear regulator with a load current tracking bias current generator (BCG). The proposed LDO employs the load current tracking BCG to achieve stable and ultra-low power operation. The measurement results demonstrated that the proposed LDO produced a 1.2 V output and achieved 78 nA quiescent current, 145 mV mA−1 load regulation, and 2.2 mV V−1 line regulation.

Efficient Non-Isolated DC-DC Converter Using Variable Switching Frequency Control

A load adaptive high efficiency dc-dc converter with optimized switching control is proposed in this paper. The converter is controlled through the switching frequency auto-tuning over a full range of load changes. The load current tracking using a single current sensor is implemented with real-time computation of the desired switching frequency. It presents the latest algorithm to adopt the loading condition while keeping the output voltage constant. The algorithm is employed with a low-cost microcontroller having the capability to maintain dynamic performance through DPWM operation. In different operational conditions and with varying parameters, the converter continually retains the higher switching frequency. This proposed AFO (Adaptive frequency Optimization) controller performance is presented through simulation using MATLAB/SIMULINK and results are verified on a 100W DC-DC converter.

Elimination of zero sequence circulating currents in paralleled three‐level T‐type inverters with a model predictive control strategy

The configuration of modular paralleled three-level T-type inverters (3LT2Is) has been widely utilised to extend the system power rating. However, zero sequence circulating currents (ZSCCs) are generated when sharing the common DC-link and the AC side without isolated transformers. This study presents a novel model predictive control (MPC) based strategy to eliminate the ZSCC in parallel operating 3LT2Is. Both the differences of common-mode voltages (CMVs) and neutral point potentials (NPPs) between paralleled 3LT2Is are investigated to be the potential exciting sources of the ZSCC based on the developed model of the ZSCC. According to this conclusion, an MPC-based zero CMV method which adds an additional term to the cost function is used to reduce the differences of CMVs between paralleled 3LT2Is. Besides, a closed-loop ZSCC feedback control method is further introduced to compensate the ZSCC by modifying the cost function. With the proposed MPC-based ZSCC elimination strategy, the ZSCC between the paralleled 3LT2Is can be effectively eliminated in both steady and dynamic states. Besides, good performances can be achieved for both load current tracking and NPP balance control. Simulation and experimental results validate the effectiveness of the proposed ZSCC elimination strategy.

A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range

One of the most critical attributes of low dropout regulators (LDOs) in increasingly complex systems on chip (SoCs) is high-power supply rejection ratio (PSRR), not only over a wide frequency range but also over a large load current range. This paper presents an LDO, realized in 65-nm CMOS, featuring >60-dB PSRR over a 10-MHz frequency range and a 100-mA large load current range. The high PSRR is achieved by an adaptive feed forward ripple cancellation (FFRC) technique embodying an adaptive load current tracking scheme. By means of embodying an NMOS-based power stage, the LDO also achieves very low dropout voltage of 80 mV and features very small overshoot and undershoot of 2 and 4 mV, respectively.

Experimental evaluation of model predictive current control for a modified three‐level four‐leg indirect matrix converter

This study presents an experimental validation and robustness evaluation of predictive current control and reactive power minimisation strategy for a three-level three-phase four-wire indirect matrix converter. The proposed topology features a unification of conventional four-leg indirect matrix converter with an additional four switches circuit resembling a back-to-back buck circuit to synthesise multi-level variable dual dc-link voltage. A systematic rectifier switching strategy is elaborated to ensure positive fictitious dc-link voltage at any instant. The proposed control and topology have been tested under various transient and steady-state conditions for comprehensive robustness evaluation. The experimental results reveal an outstanding independent load current reference tracking with low ripple current and the reactive power minimisation has been achieved by tuning the weighting factor. The load current tracking and reactive power minimisation have been achieved by properly tuning the weighting factor. The load current harmonics distortion is recorded <5% during normal operating conditions.