Load Capacitance Research Articles

Vibration characteristics of piezoelectric pipe conveying fluid subjected to fluid-structure-electrical interaction

This paper mainly investigates the vibration characteristics of piezoelectric pipe conveying fluid subjected to fluid-structure-electrical interaction. Based on the Hamilton’s principle, the dynamic equations of the cantilever piezoelectric pipe subjected to the weight and fluid-structure-electrical interaction are established and solved by using the Galerkin method. Ultimately, complex frequency and critical flow velocity are obtained. The main discussion focused on the influence of electromechanical coupling, resistive load, and dimensionless capacitance on the critical flow velocity under different lengths of piezoelectric materials. It also examined the dynamic trajectories of the real and imaginary parts of the complex frequency under various mass ratios and resistive loads. Furthermore, it explored the impact of parameters representing voltage on the stability of the system. The results indicate various stability evolutions under different lengths of piezoelectric materials, flow velocities, and parameters representing voltage. The stability of the system pipe is influenced by factors such as the length of the piezoelectric material and resistive load.

Optimization Analysis of Low-Noise Amplifier

This paper mainly analyzes the important component of a wireless receiver – low-noise amplifiers (LNA). Low-noise amplifiers can reduce the effect of noise on the received signal and amplify signals. For the better development of wireless communication technology, remote control, and other related fields, it is necessary to optimize the design of low-noise amplifiers, so that low-noise operational amplifiers can finally obtain high gain, low noise figure, and other advantages. This paper analyzes the optimization design of LNA in the field of Global Navigation Satellite Systems (GNSS). This paper analyzes a low-noise amplifier design with the operation of concurrent dual-band for GNSS receivers with a single channel. The optimized design of a low-noise amplifier in this field uses a low-cost 0.18µm CMOS tube and adds load capacitances and a feedforward path to reduce the noise figure (NF) of the system. Noise figures in 1.2 GHz and 1.57 GHz bands are reduced by about 0.9 dB. In addition, the high gain, high linearity, and other excellent properties are shown in 1.2 GHz and 1.57GHz. In the application of 5G/6G network technology, the optimized design of Gallium Arsenide (GaAs) PHEMT technology with a gate length of 0.3µmm and inductively degraded common source topology phase structure is adopted. From this optimization, the noise figure is optimized to 1.3-1.4, and the gain of the system is 20-22 dB. At the same time, good linearity is also shown. Then, the prospects of semiconductor materials such as Gallium Nitride (GaN) and Indium Phosphide (InP), which have the advantages of high electron mobility and low-cost design, in optimizing low noise operational amplifiers. To a certain extent, the in-depth study of the optimal design of LNA can improve the technical level of wireless communication, aerospace, and other fields.

An integrated approach for multi-objective differential algorithm based event constrained optimal power flow for power system resiliency enhancement

ABSTRACT Due to climatic changes, the probability of occurrence and the intensity of extreme weather events increase day by day which leads to power outages. The probability of failure events is calculated using Monte Carlo simulation technique which is used to identify the most frequent failure events. The least eigenvalues of the inverse reduced Jacobian matrix decide the sensitive buses for load shedding using V-Q sensitivity analysis. This work presents the multi-objective differential evolution (MODE) algorithm for solving resilient constrained optimal power flow (RCOPF) in a deregulated power system. The control variables namely the real power of generators in a base case and under event, generator bus voltage magnitude, the real and reactive power demand of the selected load buses, tap settings and capacitor bank ratings. This algorithm is validated in IEEE 30 bus test system and the Indian 62 bus utility test system to show the effectiveness in four different cases including tie lines and distributed generation.

High‐speed, two‐stage operational transconductance amplifier without Miller capacitor, suitable for large capacitive load

AbstractA two‐stage Class A‐AB operational transconductance amplifier with low power consumption, high slew rate, and high bandwidth is introduced for handling large capacitive loads. Unlike the conventional two‐stage operational transconductance amplifiers that use a Miller capacitor, compensation is provided by the load capacitor (CL) at the output node. The proposed two‐stage amplifier maintains a 45° phase margin (PM) over any load capacitance. This is achieved through a MOSFET‐based RC network at the output node. Dual nMOS/pMOS differential stages drive output directly, improving both SR+ and SR−. Post‐layout simulation results with a capacitive load of 100 pF (CL) demonstrate that the proposed operational transconductance amplifier has a DC gain of 60.1 dB, an excellent average slew rate of 20.3 V/µs, a gain‐bandwidth product of 10.6 MHz, an average 1% settling time of 122.2 ns and a PM of 76.6°, while consuming only 103.5 µW. Reducing the CL to 10 pF reduces the PM to 47.6°, while increasing the gain‐bandwidth and average slew rate to 82.9 MHz and 142.6 V/µs respectively.

Advanced MXene/Graphene Oxide/Lignosulfonate Inks for 3D Printing Thick Electrodes with Vertically Aligned Pores to Dually Boost Mass Loading and Areal Capacitance

AbstractDirect ink writing 3D printing, using ink extrusion, promises to transform conventional 2D thin electrodes into 3D thick architectures for high‐performance supercapacitors. However, formulating 3D printing inks and designing 3D architectures for electrodes remain challenges. In this work, a novel MXene/graphene oxide/lignosulfonate (MGL) ink with excellent rheological properties is developed for 3D printing MGL thick electrodes with vertically aligned architectures. The MGL ink exhibited excellent shear‐thinning properties for smooth 3D printing and shape retention after printing. The 3D‐printed MGL thick electrode, with a thickness of up to 4 mm, achieved a breakthrough mass loading of 72.1 mg cm−2, resulting in an extremely high areal capacitance of 8.6 F cm−2 that is 9.6 times greater than the value observed for the bulk MGL electrode (0.9 F cm−2). Additionally, supercapacitors using the 3D MGL electrode achieved an energy density of 505.3 µWh cm−2, significantly surpassing the value for bulk MGL electrode (52.8 µWh cm−2). This enhancement is attributed to the efficient design of the electrodes, where vertically aligned pores in the 3D MGL electrode enhanced ion transfer and reaction kinetics. This study demonstrates an innovative approach for formulating inks and provides guidance for designing 3D thick electrodes with rapid ion transport and excellent electrochemical performance.

Design of a tunable center frequency and small size cavity bandpass filter by separating capacitor-loaded resonators

This paper presents a tunable center frequency and small size cavity bandpass filter design method. In this method, a capacitor-loaded open terminal coaxial resonator is employed to reduce the size of cavity filters. The resonator is designed and fabricated separately into two parts to achieve the flexible operating frequency purpose. The first part is called the base of the resonator which is simply a pillar and directly fabricated integrally with the cavity housing. The second part called the hat of the resonator is the main part causing the load capacitance in cavity filters. By using different heights of the base part or/and different shapes and sizes of the hat, the operating frequency of cavity filters can be changed flexibly. This method not only reduces the difficulty and cost of cavity filter processing but also makes cavity filters reconfigurable. To demonstrate the effectiveness of the method, a cavity filter sample with a center frequency of 3.45 GHz and a bandwidth of 80 MHz was designed, fabricated, and measured. The measured results show that the insertion loss was smaller than 1.33 dB in the whole bandwidth, one zero-point at 3.350 GHz reaching -68 dB, the rejection at 3.550 GHz was -41 dB, unloaded Q was 5,898, and the dimension of the filter was 128 mm×86 mm×23 mm.

A three-stage single-miller CMOS OTA with no lower load capacitor limit

This work proposes a Single Miller Capacitor (SMC) compensated three-stage Operational Transconductance Amplifier (OTA) for a wide range of load capacitors with a zero minimum load capacitor. The proposed three-stage OTA does not require a minimum load capacitor for OTA to be stable. The proposed work uses two different feed-forward transconductors to enhance the small-signal and large-signal performances of the OTA. This OTA achieves more than 70° phase margin and more than 10dB gain margin with a load capacitor range of 0 to 500pF and consumes less quiescent current. The proposed OTA uses a smaller SMC of 2pF to drive a wide range of load capacitors. Furthermore, it saves the active area of the chip. The proposed OTA is simulated in a cadence virtuoso tool using UMC 90nm CMOS technology with BSIM4 MOSFETs.

Comparison of Si CMOS and SiC CMOS Operational Amplifiers

In this study, we numerically compare the characteristics of Si and SiC CMOS operational amplifiers (OpAmp) using LTspice. According to prior researches, we set the device parameters for Si and SiC MOSFETs. The OpAmp consists of three stages: the input stage, the gain stage, and the output stage. We established three criteria for the OpAmp's operation: (1) a unity gain frequency of 1MHz, (2) an open-loop gain of at least 75dB, and (3) a phase margin of more than 60° when a load capacitance is 300pF. To achieve a unity gain frequency of 1MHz, we adjusted the values of the resistor and capacitor used for phase compensation. The supply voltage was set to be ±5V for the Si OpAmp and ±15V for the SiC one. Our numerical analysis of the frequency response shows that the Si OpAmp met all three criteria. In contrast, the SiC OpAmp, when faced with a load capacitor of 300pF, had a phase margin of 43.4°, falling below the 60° mark. For the SiC OpAmp, the frequency response declined rapidly when the supply voltage dropped to 10V or below.

On the propagation delay of CMOS inverters

This research study delves into the propagation delay analysis in Complementary Metal-Oxide-Semiconductor (CMOS) inverters, aiming to uncover the factors contributing to it and exploring strategies to mitigate its impact. CMOS inverters, as pivotal constituents within digital integrated circuits, play a foundational role, making a thorough understanding of their propagation delay characteristics indispensable for the design of high-performance circuit. The research encompasses a comprehensive examination of propagation delay in CMOS inverters, addressing three key factors affecting it: load capacitance, transconductance parameters, and power supply voltage. Additionally, the study explores techniques for reducing propagation delay, including leveraging alternative materials and adopting specific layout designs. This study can provide insights into the sources of propagation delay in CMOS inverters and provide a comprehensive grasp of methods to alleviate it. By efficiently managing propagation delay, it becomes possible to enhance the overall performance and efficiency of CMOS circuits, thereby facilitating the development of advanced, high-speed digital systems.

A Pseudo-Differential LNA with Noise Improvement Techniques for Concurrent Multi-Band GNSS Applications

A low-noise amplifier (LNA) design with the operation of concurrent dual-band for Global Navigation Satellite System (GNSS) receivers with single channel is presented in this work. This LNA structure has an inductively degenerated cascode architecture and is pseudo-differential, operating at two frequencies simultaneously (1.2 GHz and 1.57 GHz). Two noise reduction/cancellation techniques, using load capacitor and feedforward path, respectively, are proposed resulting in an excellent improvement in the noise figure (NF). The input matching circuit uses both series and parallel resonant components to enable concurrency. The adopted pseudo-differential structure results in input balun elimination. Inductively degenerated cascode topology provides both input impedance and optimum noise impedance matching. The soundness of the proposed approach has been demonstrated in a 0.18-µm CMOS technology by TSMC. Simulation results show that at 1.2 GHz and 1.57 GHz the LNA achieves −13 dB and −11 dB of input matching, 24.6 dB and 24.7 dB of gain, 1.47 dB and 1.43 dB of NF, respectively. The input-referred 1-dB compression point (IP1dB) is around −16 dBm, while the input-referred third-order intercept point (IIP3) achieves −2.2 dBm at 1.2 GHz and −0.6 dBm at 1.57 GHz. The LNA draws about 13 mA from a 1.8-V supply voltage.

An Output-Capacitorless LDO regulator with fast transient response and high PSRR

Abstract A fast transient response and high supply voltage rejection ratio (PSRR) output-capacitor-less low-dropout (OCL-LDO) regulator with a dual power transistor structure is proposed in this paper. The designed flip voltage follower (FVF) structure and the proposed back-gate control loop improve the transient performance of the system. The proposed PSRR enhancement circuit transmits the power supply voltage fluctuation 1:1 to the gate of the power transistor so that the influence of the power supply voltage fluctuation on the output voltage of the LDO is offset by the difference between the gate and source voltages of the power transistor. The simulated results have shown that the proposed OCL-LDO regulator achieves full range stability from 100 μA to 50 mA. The output voltage undershoot is reduced by more than 100 mV when the load current is stepped from 1 to 50 mA in 500 ns without the load capacitor. The PSRR enhancement circuit increases the PSRR of the LDO from 1 KHz to 10 MHz by more than 20 dB.

ВПЛИВ ВЕЛИЧИНИ ЄМНОСТІ ПОСЛІДОВНОГО РЕЗОНАНСНОГО КОНТУРУ НА ПОТУЖНІСТЬ ЕЛЕКТРОТЕХНІЧНИХ СИСТЕМ РЕЗОНАНСНОГО ТИПУ ДЛЯ МОНІТОРИНГУ ІЗОЛЯЦІЇ ВИСОКОВОЛЬТНОГО ОБЛАДНАННЯ

It were analyzed the processes of charging the capacitive electro-technical storage (CES), which can be the electrical insulation of modern high -voltage equipment (in particular power cables) during the current monitoring of its techni-cal condition by the value of leakage currents when applying high voltage to insulation. The transformerless electro-technical system (ETS) of a resonance type, in which resonant inductive-capacitive circuit (ICС) with a high Q -factor carried out a multiple increase in AC voltage, was used to generate such voltage. Analytical expressions were obtained for the steady-state voltage on such CES and transient currents in the ETS circuit its charging. Simulation modeling of transient processes in the circuits of such ETS during CES charging was performed using the LTSpice software pack-age. It is shown that the dependences of the output voltage and current of the ETS on time, obtained by analytical ex-pressions, practically coincide with the results of simulation simulations. The influence of the ratio of the load capaci-tance and the resonant circuit capacitance on the relative load charging time and, accordingly, on the ETS power was studied. It was found that in order to increase the power of high -voltage transformerless ETS of the specified reso-nance type, it is necessary to increase the ratio of the CES capacity to the ICС capacity of the resonant circuit of the ETS. This approach can be used when using ETS with resonant ICCs to create powerful electric discharge installations (EDIs) for the implementation of technologies for obtaining electro-spark micro- and nanopowders with unique opera-tional properties. When creating powerful EDIs, it is suggested to use the value of the above-mentioned ratio at least 10. References 31, figures 5.

Accurate Evaluation of Electro-Thermal Performance in Silicon Nanosheet Field-Effect Transistors with Schemes for Controlling Parasitic Bottom Transistors.

The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (trpbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat's impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-etched S/D recess depth (TSD) exceeds 2 nm in the TIS scheme, the RC delay becomes larger than that of the BOX scheme due to increased gate capacitance (Cgg) as the TSD increases. A higher TIS height prevents the Cgg increase and exhibits the best electro-thermal performance at single-device operation. Circuit-level evaluations are conducted with ring oscillators using 3D mixed-mode simulation. Although TIS and BOX schemes have similar oscillation frequencies, the TIS scheme has a slightly lower device temperature. This thermal superiority of the TIS scheme becomes more pronounced as the load capacitance (CL) increases. As CL increases from 1 to 10 fF, the temperature difference between TIS and BOX schemes widens from 1.5 to 4.8 K. Therefore, the TIS scheme is most suitable for controlling trpbt and improving electro-thermal performance in sub-3 nm node NSFETs.

A novel gain boost and slew rate enhanced CMOTA

Abstract The design of a novel current mirror operational transconductance amplifier is proposed to address the issues of low gain and limited swing rate under conditions of low voltage and power consumption. In order to improve the gain and swing rate of the amplifier, the increase and lift technology and swing rate increase technology are introduced to the traditional op-amp Simulation and verification based on 0.18 μm BCD process and candence. The results show that under 10 pF load capacitance, the gain is increased by 42 dB and the swing rate is increased by 130 times compared with the conventional transconductance op amp.

A high current efficiency rail-to-rail operational amplifier

ABSTRACT This paper proposes a new single stage high current efficiency rail to rail amplifier (HCE-RTR). Due to the combination of a new constant transconductance control circuit and local common mode feedback (LCMFB) technique, the proposed rail to rail amplifier not only achieves improvements in unity-gain bandwidth (GBW) and slew rate (SR), but also ensures input stage transconductance constancy within the rail to rail voltage range. Based on the SMIC 180 nm process, the post-layout simulation results show that the proposed amplifier achieves rail-to-rail input/output. The simulated open loop AC response shows the DC gain, GBW, and PM are 66.2 dB, 8.2 MHz, and 60.97 o , respectively. When the driving load capacitance is 70 pF, the transient response simulation results show that the proposed amplifier achieves 0.039 µs average 1% settling time, and about 5.73 V/µs average slew rate. Note that under the condition of 1.8 V power supply, the power consumption is only 122.4 µW, proving the proposed amplifier can achieve high current efficiency while maintaining stability.

Low power content addressable memory designing and implementation using voltage swing self adjustable match line technique

One of the essential components of computer systems is memory. A primary hindrance in this regard is the memory speed. Content Addressable Memory (CAM) speeds up transformations and table lookups in network routers and data processing systems for hardware search engines. Parallel seeks using the CAM (Content Addressable Memory) model are often used to enhance memory performance. This paper uses the voltage swing self-adjustable match line (VSSA-ML) technique to describe low-power content addressable memory design and implementation. This project decreases Match Line (ML) power loss by reducing load capacitance and ML voltage swing. A simple ML voltage detector is proposed instead of the complex, fully different detector that allows ML voltage swings near zero. This paper presents 6 T 8×8 CAM arrays using VSSA-ML Technique using Tanner tools 45-nm technology. On the other hand, this design enhances robustness in processing variations by self-adjusting voltage swings. Implementation analysis states that the described mode 6 T 8×8 CAM design utilized fewer MOSFETs than the 8 T 8×8 CAM array.

Characterization of the BigRock 28 nm fast timing Analog Front End

An initial characterization of the BigRock high-speed, low-power Analog Front End (AFE) is presented. The BigRock AFE previously described in [1] has been refined in a second generation testbed ASIC, Pebbles. The AFE utilizes a current-mode signal path that has been designed for 4D tracking applications with precision time resolution of order 50 ps. The preamplifier concept is based on a prior art current-feedback CMOS topology in [2]. An on-chip test bench comprised of a variable injection circuit and high-resolution TDC measures the AFE timing resolution. An array of integrated load capacitors and IO IPs enhance the characterization capability. These full-custom pads include LVDS and clock receivers, CML output driver, and simple analog buffer pads designed at the process core voltage (0.9 V) on a 90 μm/180 μm pitch. Critical noise and timing metrics for an array of input detector capacitance ranging 0 to 100 fF have been measured.

Additional eddy current losses in transformer working at static VAr compensation station

The article discusses the impact of reactive power load on additional power losses in a high-power transformer operating at a VAr static compensation station. The presence of an almost pure capacitive load on the secondary side together with the thyristor switches is the cause of high-frequency components in the phase currents. The additional effect of electrical resonance between the transformer inductance and the load capacitance is also taken into account. The analysis is achieved using a three-dimensional finite element approach.

Equivalent circuits in nanopore-based electrochemical systems

Single-nanopore membranes constitute physical models for biological ion channels and are also central to electrochemical energy transducers, logical circuits in sensors and actuators, and converters in bioelectrical interfaces. The membrane potential, defined as the electrical potential difference established between two different ionic solutions separated by the membrane, is crucial for the electrical coupling of nanofluidic concentration cells to electronic components such as load capacitors and resistors. Here we analyze, theoretically and experimentally, the validity of basic principles governing electric circuit theory such as the Thévenin equivalent circuit, the additivity of voltages and resistances, and the Millman theorem in nanopore-based concentration cells. To this end, we consider a wide range of practical conditions with respect to salt concentrations, nanopore asymmetry, electrical capacitances, and series and parallel arrangements. Additionally, we investigate the scaling of the single pore results to the multipore case. The results obtained suggest that basic circuit models offer approximate tools to guide the analysis of the nanofluidic concentration cells.

Ring Oscillator Based True Random Number Generator

Abstract: A true random number generator (TRNG), also known as a hardware random number generator (HRNG), does not use a computer algorithm. Instead, it uses an external unpredictable physical variable such as stochastic models to generate random numbers. Here it gathers data from random electronic signals. Then, the data is converted into digital form and any patterns registered are removed to make it random. This data is used to create random numbers. It is mainly used in Cryptographic Security, authentication, secure communications, e-commerce transactions, Digital Signatures etc. In Existing Method, LFSR based TRNGs generate pseudo random numbers. They produce sequences of bits that appear random but are deterministic and repeat after a certain number of cycles known as the period. They are easy to predict and are not suitable for high security applications. This project aim is to overcome such circumstances, we use TERO(Three Edge Ring Oscillator) based TRNG. Three edges are simultaneously injected by each inverting NAND stage with enable signal Run. These edges will have an identical mean period since they propagate through the same stages. The TERO generates an oscillating signal with a frequency determined by the delay of inverters. TDC (Time to Digital Converter) is used to precisely measure the time intervals between the rising edges of TEROs output signal. Then, it converts time intervals into digital values, effectively generating truly random numbers. Power consumption depends on factors like operating frequency and load capacitance. The Software used is Xilinx Vivado/Xilinx ISE Tools. Here the Proposed Method exquisitely balances Low design effort and resource consumption with high throughput and high randomness.