Characterization of the BigRock 28 nm fast timing Analog Front End

Abstract

An initial characterization of the BigRock high-speed, low-power Analog Front End (AFE) is presented. The BigRock AFE previously described in [1] has been refined in a second generation testbed ASIC, Pebbles. The AFE utilizes a current-mode signal path that has been designed for 4D tracking applications with precision time resolution of order 50 ps. The preamplifier concept is based on a prior art current-feedback CMOS topology in [2]. An on-chip test bench comprised of a variable injection circuit and high-resolution TDC measures the AFE timing resolution. An array of integrated load capacitors and IO IPs enhance the characterization capability. These full-custom pads include LVDS and clock receivers, CML output driver, and simple analog buffer pads designed at the process core voltage (0.9 V) on a 90 μm/180 μm pitch. Critical noise and timing metrics for an array of input detector capacitance ranging 0 to 100 fF have been measured.