ABSTRACT The research letter emphasises the hardware chip design of homogeneous clustered optimised link state routing (HMC-OLSR) protocol for Mobile Ad-hoc Networks (MANET). The homogeneously distributed clustering allows for parallel processing and distributes the burden evenly among the clusters to reduce the network complexity and computational time. The chip design is evaluated based on field programmable gate array (FPGA) performance metrics for the proposed HMC-OLSR protocol, which significantly reduced hardware utilisation by 27.45%, 48.8% of slices, 28.71%, 55.82% of flip-flops, 8.35%, 13.60% of look-up tables (LUTs), and 36.4% of input/output blocks (IoBs) compared to existing OLSR and destination-Sequenced distance vector (DSDV) protocols, respectively. The recommended protocol also outperformed OLSR and DSDV routing protocols in FPGA timing constraints such as minimum time before the clock, maximum time after the clock, and minimum propagation period. The novelty of the work is in the incorporation of an FPGA-integrated scalable network design that surpasses maximum throughput, packet delivery ratio (PDR), minimum power consumption, end-to-end delay, and control overhead.
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