Linear Transconductance Amplifier Research Articles

Design and Simulation of variable gain amplifier using cadence Tool

The radio frequency (RF) amplifiers are widely used in a variety of communication systems. However, the conventional analog RF resulted in reduced volage gain, magnitude, and phase responses. So, this work provides an overview of a research paper focused on the design and analysis of a single-stage variable gain amplifier (SSVGA) utilizing cascaded linear transconductance amplifier (Gm cell) and linear transimpedance amplifier (TIA) blocks with feedback via shunt resistors. The SSVGA architecture aims to maintain constant bandwidth while offering controllable voltage gain, making it versatile for applications with varying input signal strengths. The first stage of the SSVGA is realized as a current mode TIA, converting the input voltage signal to an output current efficiently. The second stage features a Gm cell with source degeneration, enhancing bias current efficiency and transconductance at the supply voltage. The proposed SSVGA design offers flexibility and adaptability, making it suitable for diverse communication systems and signal processing applications. The incorporation of feedback control ensures consistent performance across different voltage gain settings, resulting in a robust and efficient solution for varying signal strengths.

A Wideband Differential Linear Low-Noise Transconductance Amplifier With Active-Combiner Feedback in Complementary MGTR Configurations

A wideband differential linear low-noise transconductance amplifier (LNTA) is proposed for SAW-less applications. An active combiner provides a dual-loop feedback for wideband matching with power efficiency. Operating as an auxiliary common source (CS) stage, complementary multi-gated transistor (MGTR) configurations are employed to compensate for the second- and third-order nonlinearity of the main CS stage, improving small-signal linearity. Large-signal linearity is also enhanced due to Class AB configurations. Additionally, the push-pull operation of the main CS stage and the auxiliary CS stage preserves good large-signal input matching performance. Implemented in a 0.18-μm CMOS process, the measured LNTA chip provides a minimum noise figure (NF) of 2.5 dB, and a maximum transconductance value of 76.7 mS from 0.1 to 3.1 GHz. On average, an input 1-dB compression point (IP1 dB) of 2.3 dBm and an input third-order intercept point (IIP3) of 17.8 dBm are obtained, respectively. The blocker NF is 4.0 dB under a 0 dBm blocker injection while the S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> <; -10 dB is maintained even with the blocker input of -3.1 dBm. The LNTA core only draws 13.3 mA from a 1.8 V supply.

Low power and adjustable biomedical sensor interface system

In this paper a new sensor interface using current mode approach is presented for biomedical applications. The proposed sensor interface utilises a low-power current-mode comparator, an 8 bit current mode successive approximation analogue to digital converter (SA-ADC), an adaptable band-pass filter as well as a highly linear transconductance amplifier (Gm). The Gm and current mode SAR ADC are designed in a way to achieve minimum power consumption. The circuit is simulated in 0.18 μm CMOS technology with supply voltage of 1.8 V. At 400 KS/s sampling frequency, the total power consumption and total harmonic distortion of the system are obtained equal to 2.2 μW and 45.2 dB respectively. The simulation results demonstrate the effectiveness and superiority of the proposed circuit in comparison with the conventional circuits.

Systematic Design of Current-Mode Multiple-Loop Feedback Filters Based on a Single CDCTA

ABSTRACTIn this paper, a new current differencing cascaded transconductance amplifier (CDCTA) is presented. The CDCTA circuit consists of a current differencing unit and n cascaded highly linear voltage-controlled transconductance amplifiers, and it possesses wide bandwidth and linear-tunable feature. Based on this CDCTA, a systematic design method generating current-mode (CM) multiple-loop feedback filter is proposed. By altering the parameters of the design matrix, multiple nth-order CM all-pole low pass filters structures can be synthesized without changing internal circuit. The nth-order filters have low complexity and meet the requirement of no active and passive element matching conditions as adopting only a single CDCTA and n grounded capacitors. Furthermore, the frequency of the nth-order filters can be linearly tuned by the bias voltage. A fourth-order Butterworth filter is designed as an example, and its Cadence simulation results have good agreement with the theoretical analysis.

Design and Simulation of Power Efficient Linear MOS Transconductor

Objectives: This paper proposes design of a linear and power efficient transconductance amplifier for Asynchronous Sigma-Delta Modulator (ASDM). Methods/Statistical Analysis: The proposed tranconductor circuit uses two linearization techniques which have been combined for design improvement. A triode transistors configuration with cross coupled transistor pair is used to increase the linearity. Findings: The proposed transconductor is specially designed to act as a filter for ASDM. The topology attains a DC gain (Ao) of 25 dB, a Gain-Bandwidth Product (GBW) of 70 MHz, cut-off frequency of 4 MHz and a power consumption of 72.44 μW when used as an integrator. Application/Improvements: Transconductor is simulated in TSMC 0.18μm technology with an operating voltage 1.8 V. Simulation results shows that the power consumption of circuit is very less, which makes it suitable for low power signal processing applications.

A High IIP2 SAW-Less Superheterodyne Receiver With Multistage Harmonic Rejection

In this paper, we propose and demonstrate the first fully integrated surface acoustic wave (SAW)-less superheterodyne receiver (RX) for 4G cellular applications. The RX operates in discrete-time domain and introduces various innovations to simultaneously improve noise and linearity performance while reducing power consumption: a highly linear wideband noise-canceling low-noise transconductance amplifier (LNTA), a blocker-resilient octal charge-sharing bandpass filter, and a cascaded harmonic rejection circuitry. The RX is implemented in 28-nm CMOS and it does not require any calibration. It features NF of 2.1–2.6 dB, an immeasurably high input second intercept point for closely-spaced or modulated interferers, and input third intercept point of 8–14 dBm, while drawing only 22–40 mW in various operating modes.

A highly linear CMOS transconductance amplifier in 180 nm process technology

The present article describes the design and analysis of an operational transconductance amplifier (voltage to current converter) with wide linear input range. The proposed configuration combines the techniques of signal attenuation and source degeneration in order to reduce the odd order harmonic distortion significantly. The proposed circuit is compared with several circuit topologies based on MOS differential pairs with respect to their achievable linearity, input referred noise and power consumption. The linear transconductor is designed and simulated in 180 nm CMOS process technology with 1.8 V power supply. Simulation results show third order harmonic distortion (HD 3) of ?70 dB for 600 mVpp input signal. For 1% transconductance variation the linear range is about 1.2 Vpp. The input referred noise of the transconductor is $$70\,\hbox{nV}/\sqrt{\text {Hz}}$$ at 10 MHz. The quiescent power consumption is only 450 μW.

A linear transconductance amplifier obtained by realizing a floating resistor

A novel circuit-design technique for bipolar and CMOS linear transconductance amplifiers is presented. The proposed linear transconductance amplifier consists of a differential pair of constant-current-biased transistors with a degeneration resistor and emitter- or source-followed-augmented current mirrors. The fundamental characteristics of the bipolar linear transconductance amplifier at a 1.9 V supply voltage are verified using bipolar transistor arrays and discrete resistors. The obtained linear input-voltage range is 320 mV r.m.s. (=0.905 V/sub p-p/ for less than 1% total harmonic distortion (THD) or 285 mV r.m.s. (=0.806 V/sub p-p/ for less than 0.1% THD when the input frequency is 1 kHz.

Tunable low-distortion BiCMOS transconductance amplifiers

A linear BiCMOS transconductance amplifier based on a MOS transistor operated in the linear region is presented. The circuit uses regulated cascode techniques to restrict the variation of the drain-source voltage of the MOS device and hence enhance the linearity of the V-I conversion. Simulation results confirm that the proposed circuits have superior linearity compared with other transconductance amplifiers operating in the linear region.

The ultra-multi-tanh technique for bipolar linear transconductance amplifiers

A novel circuit design technique for bipolar linear transconductance amplifiers is presented. A triple-tail cell, which consists of three emitter-common transistors biased only by a current source, is exchangeable with symmetrical cross-coupled, emitter-coupled pairs in a multi-tanh cell, such as a multi-tanh doublet, or a multi-tanh quad. Therefore, the multi-tanh technique is further theoretically expanded to the ultra-multi-tanh technique. In this paper, the ultra-multi-tanh technique is proposed and discussed, and furthermore, an ultra-multi-tanh doublet is verified with bipolar transistor-arrays and discrete resistors on a breadboard.

The super-multi-tanh technique for bipolar linear transconductance amplifiers

A novel circuit design technique for bipolar linear transconductance amplifiers is presented. A triple-tail cell, which consists of three emitter-common transistors biased by a single tail current, is exchangeable with an emitter-coupled pair in the multi-tanh cell, such as a multi-tanh doublet, a multi-tanh triplet or a multi-tanh quad. Therefore, the multi-tanh technique is further theoretically expanded to the super-multi-tanh technique. In this paper, the super-multi-tanh technique is proposed and discussed, and furthermore, a super-multi-tanh doublet is verified with bipolar transistor-arrays and discrete resistors on a breadboard.

Independent control of transconductance gain andinput linear range in a MOS linear transconductance amplifier

A linear self-biasing MOS transconductance amplifier is presented. A linear V-I transfer characteristic is obtained by square-rooting the drain current of a MOS transistor in the saturation region. The main advantage of the circuit is that its transconductance gain and input linear range can be adjusted independently. Simulation results are included to confirm the feasibility of the technique.

ANALOGUE SIGNAL PROCESSING: THE “CURRENT” WAY OF THINKING

This paper presents a tutorial review of the current-mode approach to analogue electronic circuit design, in particular some of the author’s own research over the past decade covering the development of a new generation of technology specific current-mode analogue signal processing. In this paper various technologies are represented with key current-mode building blocks ranging from current-conveyors, current-feedback operational amplifiers, linear transconductance amplifiers to applications ranging from current-mode active filters to low-noise current-mode optical preamplifiers. Advantages, future trends and perspectives of the current-mode approach are highlighted throughout the paper. The theoretical basis for many of the examples dates back many years but it is only recently due to advances in process technology that many of these techniques have now become a practical reality.