Linear Array Of Processors Research Articles

Work-preserving emulations of shuffle-exchange networks: An analysis of the complex plane diagram

In this paper we show that for each n, the order- n shuffle-exchange network can be emulated by an n-node linear processor array or an n 2-node mesh in a work-preserving manner. An emulation of a computation on a guest network G is work-preserving on a host network H , if the time-processor products are equal to within a constant factor. To achieve this result we demonstrate a uniform many-to-one embedding of the nodes of a shuffle-exchange network into a linear array. We then give a simple, deterministic routing algorithm on the linear array which schedules the communication of messages necessary to achieve the emulation within the required time bounds. The analysis of the algorithm relies on certain statistical properties of the complex plane diagram of the shuffle-exchange network.

One-dimensional processor arrays for linear algebraic problems

Using isomorphic embedding of the original dependence graphs in another graph before its space-time mapping onto array architectures, two linear processor arrays are designed for the Gauss-Jordan algorithm with partial pivoting and Cholesky decomposition. Each of these arrays comprises only (n+1)/2 processing elements (PEs), where n is the number of columns in the input matrices. The block pipelining period is n(n-1) cycles for the first array and n(n+1)/2 cycles for the second. If the matrices are processed sequentially, systems of linear equations are solved by the Gauss-Jordan algorithm with almost full processor utilisation, whereas for the Cholesky decomposition the utilisation of PEs is approximately two-thirds.

A GENERALIZED MAPPING OF 2-D ARRAY PROCESSOR TO LINEAR ARRAY PROCESSOR AND ITS APPLICATIONS

In a previous paper [14], Yang and Lee showed a mapping method which maps a 2-dimensional single-wavefront array processor to a linear array processor if there is only one wavefront propagating and never backtracks. In this paper, we shall discuss a more general case where the wavefront activates only a limited part of each diagonal. The mapping method which is more general than that given by Yang and Lee is presented here. We then show how this mapping can be applied to synthesize the stereo-matching algorithm on a linear array processor, where the number of processors depends upon the bandwidth of the wavefront.

Reconfigurable buses with shift switching: concepts and applications

We propose to enhance traditional broadcast buses by the addition of a new feature that we call shift switching. We show that on a linear array of processors enhanced with shift switching, the prefix sums of n bits can be computed in [log(n+1)/log w] broadcasts, each over n switches, assuming a global bus of width w. Next our prefix sums algorithm is used in conjunction with broadcasting on short buses to obtain several efficient architectural designs for the following fundamental problems: 1) ranking linked lists, 2) counting the number of 1's in a sequence of n bits, and 3) sorting small sets. We see our main contribution in showing that the new bus feature leads to designs that are both theoretically interesting and practically relevant.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Scheduling for Periodic Concurrent Error Detection in Processor Arrays

Periodic application of time-redundant error checking to processor arrays provides a trade-off between error detection latency and performance degradation. The goal is to achieve high error coverage while satisfying performance requirements. In this paper, we derive the optimal scheduling of checking patterns for linear processor arrays in order to minimize the error detection latency and maximize the error coverage.

The distributed voting strategy for fault diagnosis and reconfiguration of linear processor arrays

Abstract A new strategy for fault diagnosis and reconfiguration of linear processor arrays is proposed. This strategy can be implemented in a distributed manner, suitable for arrays with a large number of processors such as those implemented by VLSI and WSI techniques. The proposed fault diagnosis is based on the distributed voting technique. Additional links are added for fault diagnosis. These links are also used, when there is a processor failure, for communication between the processors. Some reconfiguration schemes are also presented emphasizing the distributed approach.

Updating URV decompositions in parallel

A URV decomposition of a matrix is a factorization of the matrix into the product of a unitary matrix (U), an upper triangular matrix (R), and another unitary matrix (V). In [8] it was shown how to update a URV decomposition in such a way that it reveals the effective rank of the matrix. It was also argued that the updating procedure could be implemented in parallel on a linear array of processors; however, no specific algorithms were given. This paper gives a detailed implementation of the updating procedure.

Efficient Levinson- and Schur-type algorithms for block near-to-Toeplitz systems of equations

Abstract In this paper new efficient Levinson- and Schur-type algorithms are derived for block near-to-Toeplitz systems of equations. In contrast to previously derived algorithms, the block near-to-Toeplitz property is exploited on a scalar level leading to Levinson- and Schur-type algorithms based on scalar instead of matrix operations. As a consequence, the highly parallel Schur-type algorithm can be implemented in a straightforward way on a linear array processor, consisting of scalar operators locally connected.

Pipelined Diagnosis of Wafer-Scale Linear Arrays

We present a comparison-based algorithm for identifying faulty and fault-free elements in a wafer-scale linear array of processors (or other logic elements). Only nearest neighbor communication is assumed to be possible between the processors in the array. Because the algorithm is simple and requires no storage of test vectors or test outcomes, it is ideally suited for implementation on the wafer to provide the capability for built-in production (or post production) testing. We show that, surprisingly, this method achieves high accuracy of diagnosis over a wide range of yields even though the diagnosis may be based on a high proportion of results produced by faulty processors. We also propose an improvement to the above algorithm which uses a processor diagnosed as fault-free by the basic algorithm as the starting point in improving the accuracy with which faulty processors are identified. Quantitative and qualitative reasoning validate the efficiency of these schemes.

AN EFFICIENT NETWORK ANALYSER BASED ON LINEAR ARRAY ARCHITECTURE∗

In this paper we present an array based network analyzer for Broadband Integrated Services Digital Networks. The analyzer is laid as a linear array processor. We describe the implementation of the analyzer's functions on the array processor. Apart the real-time application, the importance of this study becomes more apparent by the fact that, the resulting design can be implemented on configurable gate array and be attached to a microprocessor. Nevertheless, it is also possible to use the analyser array in combination with commercially available hardware to debug the network equipment in the development phase.

Intermediate-level vision tasks on a memory array architecture

With the fast advances in the area of computer vision and robotics there is a growing need for machines that can “understand images” at very high speed. A conventional von Neumann computer is not suitable for this purpose, because it takes a tremendous amount of time to solve most typical image analysis problems. Thus, it is now imperative to study computer vision in a parallel processing framework in order to reduce the processing time. In this paper we demonstrate the applicability of a simple memory array architecture to some intermediate-level computer vision tasks. This architecture, called theAccess Constrained Memory Array Architecture (ACMAA) has a linear array of processors which concurrently access distinct rows or columns of an array of memory modules. Because of its efficient local and global communication capabilities ACMAA is well suited for low-level as well as intermediate-level vision tasks. This paper presents algorithms for connected component labeling, determination of area, perimeter and moments of a labeled region, convex hull of a region, and Hough transform of an image. ACMAA is well suited to an efficient hardware implementation because it has a modular structure, simple interconnect and limited global control.

Neural network feature detector for real-time video signal processing.

The application of artificial neural networks to real-time image processing tasks requires the use of dedicated, high performance hardware. A linear array processor called HANNIBAL has been developed which implements the backpropagation neural learning algorithm on-chip. This paper considers the design of a complete neural system which integrates HANNIBAL into an existing image processing environment. The goals for the design of the system have been set partly by the primary application, namely feature recognition, but mainly by the desire for a flexible, high performance hardware tool for the study and evaluation of range of neural image processing applications.

Optimized cyclic reduction for the solution of linear tridiagonal systems on parallel computers

A parallel version of the cyclic reduction algorithm for the solution of tridiagonal linear systems is presented. The original problem is divided into subproblems which may be solved almost independently. Synchronizations among the processors involved is only needed to solve a reduced tridiagonal system whose dimension depends on the number of processors. Numerical tests have been performed on a linear array of processors. The obtained speedups show that this is the best possible parallel implementation of the cyclic reduction and one of the fastest algorithms for the solution of tridiagonal systems on a parallel computer with medium grain parallelism.

A PARALLEL ALGORITHM TO GENERATE N-ARY REFLECTED GRAY CODES IN A LINEAR ARRAY WITH RECONFIGURABLE BUS SYSTEM

A simple parallel algorithm for generating N-ary reflected Gray codes is presented. The algorithm is derived from the pattern of N-ary reflected Gray codes. The algorithm runs on a linear processor array with a reconfigurable bus system. A reconfigurable bus system is a bus system whose configuration can be dynamically changed. Recently processor arrays with reconfigurable bus systems were used to solve many problems in constant time. There already exists experimental reconfigurable chips.

On balancing sorting on a linear array

A balanced parallel algorithm to sort a sequence of items on a linear array of processors is presented. The length of the sequence may be small to arbitrarily large. For a short sequence, the output of the sorted sequence begins at the step following the last input of the whole sequence. For an arbitrarily long sequence, the time complexity is optimal under realistic hardware conditions. A variation of the algorithm is also introduced. Both algorithms require far less local memory than that required by a different approach of balanced computation. Any number of balanced processors can be connected to deliver more computing power without increasing the memory size of each processor.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Systolic architectures for finite-state vector quantization

The authors present a new systolic architecture for implementing finite state vector quantization in real-time for both speech and image data. This architecture is modular and has a very simple control flow. Only one processor is needed for speech compression. A linear array of processors is used for image compression; the number of processors needed is independent of the size of the image. Image data is processed at a rate of 1 pixel per clock cycle. An implementation at 31.5 MHz can quantize 1024*1024 pixel images at 30 frames/sec in real-time. The authors describe a VLSI implementation of these processors. >

Updating a Rank-Revealing ULV Decomposition

A ULV decomposition of a matrix A of order n is a decomposition of the form $A = ULV^H $, where U and V are orthogonal matrices and L is a lower triangular matrix. When A is approximately of rank k, the decomposition is rank revealing if the last $n - k$ rows of L are small. This paper presents algorithms for updating a rank-revealing ULV decomposition. The algorithms run in $O( n^2 )$ time, and can be implemented on a linear array of processors to run in $O( n )$ time.

Constant geometry fast Fourier transforms on array processors

Matrix algebra is used to design and validate parallel algorithms for large constant-geometry fast Fourier transforms (FFTs) on fixed-size array processors. The N-point radix 2 case for a linear array processor with N/2 cells is identical to the usual procedure corresponding to the matrix factorization of M.C. Pease, (1968). The algorithms are engendered by matrix factorizations, which themselves depend on a basic factorization of the perfect shuffle. The resulting data movement is realized in parallel as relatively small perfect shuffles inside each local memory and along each row and column of the array processor, without requiring that the complete array itself have the shuffle-exchange network. >

Recursive neighbourhood operations on the linear processor array SYMPATI-2

This paper deals with parallelism in image processing. Local neighbourhood operations and recursive neighbourhood operations are presented and illustrated with examples. Then a linear processor array is depicted and the method of parallelizing those operations is shown. Experimental results are provided, and we show that linear structures are relevant for both local and recursive neighbourhood operations.

Parallel architecture for a pel-recursive motion estimation algorithm

A parallel architecture for a pel-recursive motion estimation algorithm is presented. It is a linear array of processors, each consisting of an initialization part, a data-routing part, and an updating part. The initializing part performs a prediction of the motion vector. The routing parts constitute a routing path along which previous-frame data are routed from processors that store to processors that request such data. The router can be data driven or clocked. The latter approach is presented in more detail. The updating part calculates an update to the predicted motion vector. The architecture proposed is derived in a systematic way and is parameterized with respect to certain window sizes. It is thus completely different from the few existing pel-recursive motion estimation architectures. >