Linear CMOS Low Noise Amplifier Research Articles

A UWB CMOS low-noise amplifier with noise reduction and linearity improvement techniques

In this paper, a highly linear CMOS low noise amplifier (LNA) for ultra-wideband applications is presented. The proposed LNA improves both input second- and third-order intercept points (IIP2 and IIP3) by canceling the common-mode part of all intermodulation components from the output current. The proposed LNA structure creates equal common-mode currents with the opposite sign by cascading two differential pairs with a cross-connected output. These currents eliminate each other at the output and improve the linearity. Also, the proposed LNA improves the noise performance by canceling the thermal noise of the input and auxiliary transistors at the output. Detailed analysis is provided to show the effectiveness of the proposed LNA structure. Post-layout circuit level simulation results using a 90nm RF CMOS process with Spectre-RF reveal 9.5dB power gain, -3dB bandwidth (BW−3dB) of 8GHz from 2.4GHz to 10.4GHz, and mean IIP3 and IIP2 of +13.1dBm and +42.8dBm, respectively. The simulated S11 is less than −11dB in whole frequency range while the LNA consumes 14.8mW from a single 1.2V power supply.

A highly linear CMOS low noise amplifier for K-band applications

This paper describes a highly linear low noise amplifier (LNA) for K-band applications in a 0.18 µm RF CMOS technology. The core of the circuit is a two-stage LNA consisting of a common-source and a cascode stage. By adopting an improved post-linearisation technique at the common-source transistor of the second stage, more than 5 dB improvement in IIP3 is achieved with a minor effect on noise figure and input matching. The circuit level analysis and simulation results are presented to demonstrate the effectiveness of the proposed technique.

An Optimum Body Biasing for Gain and Linearity Control in CMOS Low-Noise Amplifiers

In this paper, an optimum body biasing for gain and linearity control in CMOS Low Noise Amplifier (LNA) is discussed. A digitally controlled highly linear CMOS LNA has been designed and implemented in a 0.13 μm CMOS process. An off chip Digital to Analog Converter (DAC) is used to generate the proper body bias voltage corresponding to a maximum of the input referred third order intercept point (IIP3). The LNA is suitable for reconfigurable purposes due to its smooth control of gain and linearity. It is dedicated to wireless sensor network applications in the 2.4 GHz ISM Band. The circuit achieves 12.4 dB nominal gain, 4.2 dB noise figure (NF), and ―1 dBm IIP3 while drawing 3.1 mA at a 1 V supply. When adjusting the body bias to ―0.55 V, the IIP3 peaks at 6 dBm for a 1.7 mA current consumption. The gain and NF are 8.9 dB and 6.2 dB respectively.