Linear Array Architecture Research Articles

Linear array of charge sensitive infrared phototransistors for long wavelength infrared detection

Infrared has been deeply involved in frontier research, modern technologies, and human society, which requires sensitive infrared detection and sensing, in particular, array imaging. A charge-sensitive infrared phototransistor (CSIP) device is made of a GaAs/AlGaAs double quantum well and has been shown to exhibit much larger infrared photoresponsivity than conventional infrared photodetectors, attributable to its built-in amplification mechanism of large transconductance. In this work, we propose and demonstrate a linear array architecture of long wavelength CSIPs with each pixel directly addressable via its reset gate. The performance of a prototype 1×8 linear array of CSIPs is studied at 5 K, and each pixel shows a large photoresponsivity of >50 A/W at the peak wavelength of λ=11 μm, nearly two orders higher than conventional detectors. Using a home-made multi-channel pulse generator, the array is operated at a typical frame rate of ∼5 ms, without the necessity of using cryogenic readout circuits. Besides, the fabrication of the proposed CSIP array requires only state-of-the-art planar technology; our work, therefore, provides a promising solution to realize very sensitive and small-scale array infrared imaging for sensitive long-wavelength infrared applications.

A New Variable Forgetting Factor-Based Bias-Compensated RLS Algorithm for Identification of FIR Systems With Input Noise and Its Hardware Implementation

This paper proposes a new variable forgetting factor QRD-based recursive least squares algorithm with bias compensation (VFF-QRRLS-BC) for system identification under input noise. A new variable forgetting factor scheme is proposed to improve its convergence speed and steady-state mean squares error. A new method for recursive estimation of the additive noise variance is also proposed for reliable bias compensation. The mean and mean-square asymptotic behaviors of the algorithm are analyzed and a self-calibration scheme is further proposed to improve the steady-state mean squares error (MSE) due to finite sample effect. Simulations show that the proposed VFF approach offers improved tracking and steady-state MSE performance over the conventional recursive least squares method and its fixed FF counterpart. A linear array architecture is proposed for the realization of this algorithm and several hardware efficient techniques are introduced to avoid the expensive cubic root and division operations required. The proposed algorithm is validated on Xilinx Zynq®-7000 AP SoC ZC702 Field Programmable Gate Array (FPGA). For a 10-tap finite impulse response (FIR) system, the implementation requires only about 11.5k slice look-up table (LUT)s, 4.5k slice registers and 50 DSP48s and it can work up to about 0.58 MHz sample rate with a 200 MHz system clock. The hardware resources are considerably lower than traditional techniques using divider and cubic root realization. The linear array architecture also serves as an attractive alternative to the systolic array in medium to low rate applications due to its reduced hardware usages.

On the Use of the $Z$ Transform of LTI Systems for the Synthesis of Steered Beams and Nulls in the Radiation Pattern of Leaky-Wave Antenna Arrays

This paper addresses the use of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$Z$</tex-math></inline-formula> transform to synthesize radiation patterns with prescribed nulls from a phased array of electronically reconfigurable leaky-wave antennas (LWAs). This approach provides the relationship between such antennas and linear and time invariant (LTI) systems. Using this signal processing perspective, the proper locations of the poles and zeros of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$Z$</tex-math></inline-formula> transform of the associated LTI system provide a radiation pattern with prescribed specifications (mainly main lobes’ directions and surrounding radiation nulls). Then, these poles and zeros’ positions can be transformed into particular values of the LWA array control coefficients. The effectiveness of the proposed technique is demonstrated with the synthesis of various radiation patterns, with application to reconfigurable smart antennas. A comparison with more conventional uniform linear array architecture is also performed to evaluate the synthesis flexibility and system complexity of the proposed approach.

A New Systolic Array Algorithm and Architecture for the VLSI Implementation of IDST Based on a Pseudo-Band Correlation Structure

In this paper a new linear VLSI array architecture for the VLSI implementation of a prime-length 1-D Inverse Discrete Sine Transform (IDST) is proposed. This new design approach uses a ...

A Family of Modular QRD-Accelerator Architectures and Circuits Cross-Layer Optimized for High Area- and Energy-Efficiency

QR-decomposition accelerators are attractive SoC components for many applications with a wide range of specifications. A new family of highly area- and energy-efficient, modular two-way linear-array QRD architectures based on the Givens algorithm and CORDIC rotations is proposed. The template architecture allows for implementations of real-/complex-valued and integer/floating-point QRDs. An accurate algebraic cost model enables cross-layer optimization over architecture, micro-architecture and circuit level using a rich set of parameters. Quantitative results for exemplary applications are presented for implementations in 40-nm CMOS, proving the significant improvement of efficiency.

A Flexibly Fault-Tolerant FU Array Processor and its Self-Tuning Scheme to Locate Permanently Defective Unit

Nowadays, small feature-sized transistors and wires led by the process miniaturization have shown increasing vulnerability to both transient and permanent faults. Modular redundancy in circuits and failure-unit isolation are thereby employed to guarantee the correct execution and also to well keep the lifespan of electronic devices. In this work, we propose the Explicit Redundancy Linear Array (EReLA) architecture to provide a highly flexible fault tolerance. EReLA follows the baseline reconfigurable architecture, which works best with failure-unit isolation and hot-swap techniques. In addition, specifically for the preparation of hot swaps, we propose a low-cost self-tuning scheme, to fast locate the precise position of the defective processing element or network connection. Powered by these schemes, EReLA is functionally the same as a traditional TMR processor in terms of fault tolerance, while the power data of a 180nm prototype EReLA chip has indicated that it incurs about 1/3 less power consumption than the TMR implementation.

A Flexible, Self-Tuning, Fault-Tolerant Functional Unit Array Processor

Today, small feature-sized transistors and wires led by process miniaturization have shown increasing vulnerability to both transient and permanent faults. Modular redundancy in circuits and failure-unit isolation are thereby employed to guarantee the correct execution and also to lengthen the lifespan of electronic devices. This article proposes the Explicit Redundancy Linear Array (EReLA) architecture to provide highly flexible fault tolerance. EReLA follows the baseline reconfigurable architecture, which works best with failure-unit isolation and hot-swap techniques. In addition, specifically for the preparation of hot swaps, the authors propose a low-cost self-tuning scheme to quickly locate the precise position of the defective processing element or network connection. Powered by these schemes, EReLA can function the same as a traditional TMR processor in terms of fault tolerance with a third less power consumption, as indicated by the power data of a 0.18 μm prototype EReLA chip. The simulation data indicates that EReLA achieves around 4× the lifespan of the traditional TMR processor.

A new VLSI algorithm and architecture for the hardware implementation of type IV discrete cosine transform using a pseudo-band correlation structure

AbstractA new VLSI algorithm and its associated systolic array architecture for a prime length type IV discrete cosine transform is presented. They represent the basis of an efficient design approach for deriving a linear systolic array architecture for type IV DCT. The proposed algorithm uses a regular computational structure called pseudoband correlation structure that is appropriate for a VLSI implementation. The proposed algorithm is then mapped onto a linear systolic array with a small number of I/O channels and low I/O bandwidth. The proposed architecture can be unified with that obtained for type IV DST due to a similar kernel. A highly efficient VLSI chip can be thus obtained with good performance in the architectural topology, computing parallelism, processing speed, hardware complexity and I/O costs similar to those obtained for circular correlation and cyclic convolution computational structures.

MIMO Channel Capacity With Polarization Diversity in Arched Tunnels

This letter studies the possible application of MIMO polarization diversity in road/railway tunnels. By means of an extensive measurement campaign extending from 2.8 to 5 GHz, different linear array architectures were studied, considering different polarizations within each array. Channel capacity was calculated assuming either a constant signal-to-noise ratio (SNR), whatever the array architecture, or a fixed transmitted power. Interpretation of the results is based on the spatial correlation between the incident electric fields on the array elements and also on the variation of the SNR in the case of a fixed transmitted power.

An Integrated Memory Array Processor for Embedded Image Recognition Systems

Embedded processors for video image recognition in most cases not only need to address the conventional cost (die size and power) versus real-time performance issue, but must also maintain high flexibility due to the immense diversity of recognition targets, situations, and applications. This paper describes IMAP, a highly parallel SIMD linear processor and memory array architecture that addresses these trade-off requirements. By using parallel and systolic algorithmic techniques, but based on a simple linear array architecture, IMAP successfully exploits not only the straightforward per-image row data level parallelism (DLP), but also the inherent DLP of other memory access patterns frequently found in various image recognition tasks, while allowing programming to be done using an explicit parallel C language (1DC). We describe and evaluate IMAP-CE, one of the latest IMAP processors, integrating 128 100 MHz 8 bit 4-way VLIW PEs, 128 2 KByte RAMs, and one 16 bit RISC control processor onto a single chip. The PE instruction set is enhanced to support 1DC code. The die size of IMAP-CE is 11 times11 mm2 integrating 32.7 M transistors, while the power consumption is, on average, approximately 2 watts. IMAP-CE is evaluated mainly by comparing its performance while running 1DC code with that of a 2.4 GHz Intel P4 running optimized C code. Based on the use of parallelizing techniques, benchmark results show a speed increase of up to 20 times for image filter kernels and of 4 times for a full image recognition application

Processor array architectures for flexible approximate string matching

In this paper, we present linear processor array architectures for flexible approximate string matching. These architectures are based on parallel realization of dynamic programming and non-deterministic finite automaton algorithms. The algorithms consist of two phases, i.e. preprocessing and searching. Then, starting from the data dependence graphs of the searching phase, parallel algorithms are derived, which can be realized directly onto special purpose processor array architectures for approximate string matching. Further, the preprocessing phase is also accommodated onto the same processor array designs. Finally, the proposed architectures support flexible patterns i.e. patterns with a ''don't care'' symbol, patterns with a complement symbol and patterns with a class symbol.

Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on Reconfigurable Computing Systems

The abundant hardware resources on current reconfigurable computing systems provide new opportunities for high-performance parallel implementations of scientific computations. In this paper, we study designs for floating-point matrix multiplication, a fundamental kernel in a number of scientific applications, on reconfigurable computing systems. We first analyze design trade-offs in implementing this kernel. These trade-offs are caused by the inherent parallelism of matrix multiplication and the resource constraints, including the number of configurable slices, the size of on-chip memory, and the available memory bandwidth. We propose three parameterized algorithms which can be tuned according to the problem size and the available hardware resources. Our algorithms employ linear array architecture with simple control logic. This architecture effectively utilizes the available resources and reduces routing complexity. The processing elements (PEs) used in our algorithms are modular so that it is easy to embed floating-point units into them. Experimental results on a Xilinx Virtex-ll Pro XC2VP100 show that our algorithms achieve good scalability and high sustained GFLOPS performance. We also implement our algorithms on Cray XD1. XD1 is a high-end reconfigurable computing system that employs both general-purpose processors and reconfigurable devices. Our algorithms achieve a sustained performance of 2.06 GFLOPS on a single node of XD1

FPGA implementation of RSA public-key cryptographic coprocessor based on systolic linear array architecture

In order to make the typical Montgomery’s algorithm suitable for implementation on FPGA, a modified version is proposed and then a high-performance systolic linear array architecture is designed for RSA cryptosystem on the basis of the optimized algorithm. The proposed systolic array architecture has distinctive features, i.e. not only the computation speed is significantly fast but also the hardware overhead is drastically decreased. As a major practical result, the paper shows that it is possible to implement public-key cryptosystem at secure bit lengths on a single commercially available FPGA.

An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems

Embedded processors for video image recognition require to address both the cost (die size and power) versus real-time performance issue, and also to achieve high flexibility due to the immense diversity of recognition targets, situations, and applications. This paper describes IMAP, a highly parallel SIMD linear processor and memory array architecture that addresses these trading-off requirements. By using parallel and systolic algorithmic techniques, despite of its simple architecture IMAP achieves to exploit not only the straightforward per image row data level parallelism (DLP), but also the inherent DLP of other memory access patterns frequently found in various image recognition tasks, under the use of an explicit parallel C language (1DC). We describe and evaluate IMAP-CE, a latest IMAP processor, which integrates 128 of 100MHz 8 bit4-way VLIW PEs, 128 of 2KByte RAMs, and one 16 bit RISC control processor, into a single chip. The PE instruction set is enhanced for supporting 1DC codes. IMAP-CE is evaluated mainly by comparing its performance running 1DC codes with that of a 2.4GHz Intel P4 running optimized C codes. Based on the use of parallelizing techniques, benchmark results show a speedup of up to 20 for image filter kernels, and of 4 for a full image recognition application.

Implementation of model predictive control using real-time multiprocessing computing

This work addresses the issue of finding the programming procedure that results to the fastest implementation of the core calculations of the model predictive control (MPC) algorithms that are amenable to parallel processing on a real-time multiprocessing system. Three concurrent programming procedures were considered for the MPC implementation, each one consisting of a number of tasks configured to a linear array, mesh and tree parallel architectures. Both theoretical analysis and measurements, taken from running these procedures on a four-processor computer platform, indicate that the procedure of the linear array architecture presents the best speed-up ratio.

A parallel algorithm for generating chain code of objects in binary images

This paper addresses parallel execution of chain code generation on a linear array architecture. The contours in the proposed algorithm are viewed as a set of edges (or contour segments) that can be traced by a top-down contour tracing method to generate the chain codes for the outer and inner object contours. A parallel algorithm that contains the chain code generating rules and operations needed is also described, and the algorithm is mapped onto a one-dimensional systolic array containing ⌈ 1 2 (N+1)⌉ processing elements (PEs) to devise this architecture. The architecture extracts the contours of objects and quickly generates the corresponding chain codes after the image data in all rows are inputted in a linear fashion. The total processing time for generating the chain codes in an N× N image is O(3 N). By doing so, the real-time requirement is fulfilled and its execution time is independent of the image content. In addition, a partition method is developed to process an image when the parallel architecture has a fixed number of PEs; say two or more. The total execution time for an N× N image by employing a fixed number of PEs is N( N+1)/ M+2( M−1), when M is the fixed number of PEs.

Parallel distance transforms on a linear array architecture

Distance transformation (DT) has been widely used for image matching and shape analysis. In this paper, a parallel algorithm for computing distance transformation is presented. First, it is shown that the algorithm has an execution time of 6 N−4 cycles, for an N× N image using a parallel architecture that requires ⌈ N/2⌉ parallel processors. By doing so, the real time requirement is fulfilled and its execution time is independent of the image contents. In addition, a partition method is developed to process an image when the parallel architecture has a fixed number of processing elements (PEs); say two or more. The total execution time for an N× N image by employing a fixed number of PEs is 2[ N 2/ M+2( M−1)], when M is the fixed number of PEs.

New matrix formulation for two-dimensional DCT∕IDCT computation and its distributed-memory VLSI implementation

A direct method for the computation of 2-D DCT/IDCT on a linear-array architecture is presented. The 2-D DCT/IDCT is first converted into its corresponding 1-D DCT/IDCT problem through proper input/output index reordering. Then, a new coefficient matrix factorisation is derived, leading to a cascade of several basic computation blocks. Unlike other previously proposed high-speed 2-D N×N DCT/IDCT processors that usually require intermediate transpose memory and have computation complexity O(N 3), the proposed hardware-efficient architecture with distributed memory structure has computation complexity O(N 2 log2 N) and requires only log2 N multipliers. The new pipelinable and scalable 2-D DCT/IDCT processor uses storage elements local to the processing elements and thus does not require any address generation hardware or global memory-to-array routing.

Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization

Current and future requirements for adaptive real-time image compression challenge even the capabilities of highly parallel realizations in terms of hardware performance. Previously proposed linear array structures for full-search vector quantization do not offer scalability and adaptivity in this context, because they require separate data/control pins for dynamically updating the codevectors and complicated interlock mechanisms to ensure that the regular data flow is not corrupted as a result of updates. We explore the design space for full-search vector quantizers and propose a novel linear processor array architecture in which global wiring is limited to clock and power supply distribution, thus allowing high-speed processing in spite of only limited communication with the host via the boundary processors. The resulting fully pipelined design is not only area-efficient for VLSI implementation but is also readily scalable and offers extremely high performance.

Design of low-cost and high-throughput linear arrays for DFT computations: algorithms, architectures, and implementations

Recursive algorithms for discrete Fourier transform (DFT) computation are proposed, where the common entries of the decomposed matrices are factored out in order to reduce the number of multipliers during implementation. The derived algorithms are essentially band-matrix-vector multiplications with matrix bandwidth of 3 in the radix-2 case and bandwidth of 7 in the radix-4 case. Low cost architectures are derived using an efficient mapping technique for the corresponding heterogeneous dependence graphs of the decomposed band matrices. Only log/sub 2/ N(3 log/sub 4/ N) adders and log/sub 2/ N-1(log/sub 4/ N-1) multipliers are needed to compute the DFT of size N using the proposed radix-2 (radix-4) linear array architectures, a great saving in hardware cost compared to previous approaches. Due to the simplicity and regularity of the architectures, it is possible to reduce the power consumption of the DFT processors by temporarily disabling the multiplier units at proper time steps. VLSI implementations of an 8-point radix-2 DFT processor and a 64-point radix-4 DFT processor are also given.