Line Tunnel Field-effect Transistors Research Articles

Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction

Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction

Comparison between low-dropout voltage regulators designed with line and nanowire tunnel field effect transistors using experimental data

This paper presents the comparison of Low-Dropout Voltage Regulators (LDOs) designed with Nanowire (NW-TFET) and Line Tunnel FET (Line-TFET), in which the transistors were modeled using Verilog-A and Lookup Tables (LUTs) obtained from experimental data. The LDOs were designed in two gm/ID, load currents and capacitances conditions: 7 V−1, 100 µA, 100 pF and 10.5 V−1, 10 µA, 10 pF. For comparison, a MOSFET LDO was designed with TSCM 0.18 µm PDK. It was observed that both TFET LDOs can be designed without the compensation capacitor to reach stability. The Line-TFET LDO delivers better specifications than the NW-TFET LDO, but with higher current consumption. Comparing with MOSFET LDO, both TFET LDOs present higher efficiency. The Line-TFET LDO showed higher loop gain and lower, but comparable, gain-bandwidth product (GBW) in both biases.

Device-Simulation-Based Machine Learning Technique for the Characteristic of Line Tunnel Field-Effect Transistors

With the rapid growth of the semiconductor manufacturing industry, it has been evident that device simulation has been considered a sluggish process. Therefore, due to downscaling of semiconductor devices, it is significantly expensive to obtain the inevitable device simulation data because it requires complex analysis of various factors. To develop a competent technique to analyze the performance of the line tunnel field-effect transistors (TFETs), the 3-D stochastic device simulation is integrated with a machine learning (ML) algorithm, named random forest regressor (RFR). Despite producing tremendous researches by the RFR model in the field of computer vision, the adoption of these ML algorithms in the field of the semiconductor industry has a lot of margin for progress. The ML-based RFR model is exploited to predict the effect of variability sources of line TFET under different biasing conditions. Results are promising and reducing the computational cost of device simulation by 99%. The prediction of effect of source variation is less than 1% as compared to the device simulation of line TFET. The application of the RFR on the line TFET device exhibits the power and flexibility of this approach because its evaluation with different bias conditions shows outstanding results.

P-SiGe nanosheet line tunnel field-effect transistors with ample exploitation of ferroelectric

This work illustrates the ample exploitation of ferroelectric through metal-ferroelectric options for nanosheet line tunnel field-effect transistor (NLTFET), for the first time. Here, SiGe and ferroelectric (HZO) are successfully employed to demonstrate the high performance p-NLTFET through simulations. Owing to this, the on-state current (I on = 122.3 μA μm−1) is enormously improved through the reduction of gate-oxide thickness even at low gate bias. In addition, the steep subthreshold swing is effectively minimized to 25.96 mV dec−1 by controlling the off-state current, gate-leakage and trap-assisted-tunneling. Overall, a 2-order boost on the I on is achieved, compared with planar ferroelectric TFETs.

Optimization of Tunnel Field-Effect Transistor-Based ESD Protection Network

The tunnel field-effect transistor (TFET) is a potential candidate for replacing the reverse diode and providing a secondary path in a whole-chip electrostatic discharge (ESD) protection network. In this paper, the ESD characteristics of a traditional point TFET, a line TFET and a Ge-source TFET are investigated using technology computer-aided design (TCAD) simulations, and an improved TFET-based whole-chip ESD protection scheme is proposed. It is found that the Ge-source TFET has a lower trigger voltage and higher failure current compared to the traditional point and line TFETs. However, the Ge-source TFET-based secondary path in the whole-chip ESD protection network is more vulnerable compared to the primary path due to the low thermal instability. Simulation results show that choosing the proper germanium mole fraction in the source region can balance the discharge ability and thermal failure risk, consequently enhancing the whole-chip ESD robustness.

A New Z-Shaped Gate Line Tunnel FET with Improved Electrostatic Performance

In this paper, we simulated a new line tunnel field-effect transistor (TFET) with a Z-shaped gate. The proposed Z-TFET generates vertical tunneling due to the presence of the front gate over the entire source region. This generates faster tunneling between the source and the channel region, providing a 3-decade improvement in drain current compared to conventional DG-TFET. The ambipolar current is also improved by 1-decade with a subthreshold swing (SS) of 40 mV/decade (reduces by 18%). Further optimization of the front and back gate is performed to investigate its impact on the analog performance of Z-TFET. The simulated results exhibit improvement in ambipolar current, reduction in OFF current by optimizing the back-gate length. This simulation work is performed in the presence of field-induced quantum confinement using the TCAD device simulator. Additional reliability issue of the structure in the presence of the interface trap charge at the semiconductor-oxide interface is properly investigated. The effect of trap charge density (Nf) and capture cross-section (σ) variation on the transfer characteristics and average SS has been examined. The proposed device can provide a higher ION/IOFF of 1013 and ION/IAMB of 107.

Impact of drain doping engineering on ambipolar and high-frequency performance of ZHP line-TFET

In this paper, we present a new Z-shaped line tunnel field effect transistor (TFET) employing drain doping engineering with a split drain structure (SD-ZHP-TFET). The split drain (SD) approach in the proposed ZHP-TFET helps increasing tunneling width at the channel-drain interface, reducing ambipolarity. Moreover, a horizontal pocket (HP) is implanted in the source region to boost the ON-current of the proposed SD-ZHP-TFET structure. The effect of both these approaches in the line-TFET provides higher ON-current and reduces ambipolarity significantly. Split drain structure in the ZHP-TFET exhibits a three-decade improvement in the ambipolar current without affecting the subthreshold (SS) and leakage current significantly. A calibrated simulation study of split drain thickness (tu) and drain region doping variation on the analog performance are investigated using the technology computer-aided design device simulator. Moreover, the high-frequency figure of merit regarding total gate capacitance (Cgg), unit-gain cut-off frequency (fT) is analysed. It is found that the drain doping improves the cut-off frequency from 1.8 GHz in ZHP-TFET to 2.2 GHz in the proposed SD-ZHP-TFET structure. Thus the proposed device is capable of providing higher ION/IOFF (≈1013) and ION/IAMB (≈1013) ratio with an average SS of 44 mV/decade.

Analog design with Line-TFET device experimental data: from device to circuit level

This work studies the use of line-tunnel field effect transistor (Line TFET) devices in analog applications. It presents the DC and small signal characteristics of these devices and compares them with other TFET topologies and with conventional MOSFET technology. The Line-TFET’s saturation characteristics are also closely studied, through simulations and experimental characterization, revealing that point tunneling leakage from source to drain not only limits the bias voltage and the gate area but also makes the output conductance independent of the gate length. A common source stage is designed to illustrate and further explore this fact, making comparisons with conventional MOSFET technology. In order to obtain an amplifier with very high voltage gain, a two-stage operational transconductance amplifier is designed considering two different starting points: fixed transistor efficiency (gm/Ids) or fixed normalized current (Ids/W) in order to obtain similar conditions of performance for Line-TFET and MOSFET devices. It is revealed that the Line-TFET design always achieves much higher intrinsic voltage gain (of up to 115 dB) and is more suitable for low power, low frequency applications. Thus, a third design is performed with Line-TFET devices by using gate lengths of 100 nm, achieving 71 dB of open loop voltage gain and 18 nW of power dissipation, which may be suitable for applications such as bio-signal acquisition.

Optimal Inter-Gate Separation and Overlapped Source of Multi-Channel Line Tunnel FETs

This work comprises of design and simulation of multi-channel line tunnel field-effect transistors (mCLTFETs) by scaling inter-gate separation (IGS) and overlapped source ( LOV ). The scope of the work is to explore the performance boost and optimization of the studied devices by considering geometrical structures, low-bandgap materials, IGS and LOV of the mCLTFETs. The structure is designed without diminishing the subthreshold swing ( SS ) and the leakage currents through a spacer technology and strained Si0.6Ge0.4. The optimal values of IGS and LOV for the multi-channel concept are estimated subject to several physical constraints of the proposed device. An IGS a 10 nm and a LOV a LG /2 are reported as suitable choice for sub-8-nm technological nodes, where SS = 18 mV/dec and Ion / Ioff = 109 are achieved.

Performance of differential pair circuits designed with line tunnel FET devices at different temperatures

This work studies differential pair circuits designed with Line tunnel field effect transistors (TFETs), comparing their suitability with conventional Point TFETs. Differential voltage gain (Ad), compliance voltage and sensitivity to channel length mismatch are analyzed experimentally for different temperatures. The first part highlights individual characteristics of Line TFETs, focusing on behaviors that affect analog circuits. In comparison to Point TFETs, Line TFETs present higher drive current, better transconductance and worse output conductance. In the second part, differential pairs are studied at room temperature for different dimensions and bias conditions. Line TFETs present the highest Ad, while Point TFET decrease the susceptibility to channel length mismatch. In the last part, the temperature impact is investigated. Based on the activation energy, the impact of band-to-band tunneling and trap-assisted tunneling is discussed for different bias conditions. A general equation is proposed, including the technology and the susceptibility to temperature and dimensions. It was observed that Line TFETs are a good option to design differential pairs with higher Ad and ON-state current than Point TFETs.

Analysis of current mirror circuits designed with line tunnel FET devices at different temperatures

The goal of this work is to study the performance of current mirror circuits designed with line tunnel field effect transistor (TFET) devices and compare the suitability of this technology with alternatives such as point TFETs and FinFETs. Experimental results have been obtained at room and high temperatures and the analyses focused on parameters such as the magnitude of the on-state current and the sensitivity of the current transfer ratio to channel dimensions mismatch and to the temperature. Line TFETs exhibited higher on-state current than point TFETs, in spite of a higher susceptibility to the channel length. When band-to-band tunneling prevails for both input and output transistors, the current transfer ratio with line TFETs presented a nearly linear dependence on the temperature due to bandgap narrowing. This way, a general equation of the current transfer ratio for circuits designed with the three highlighted technologies is proposed. Globally, it was observed that, unless a very low sensitivity to channel length mismatch is required, line TFET devices are a very suitable alternative for current mirror circuits, since this technology provides much higher on-state currents than point TFETs, and at the same time it is much less sensitive to temperature variations than FinFET transistors.

Heteromaterial-gate line tunnel field-effect transistor based on Si/Ge heterojunction**Project supported by the National Natural Science Foundation of China (Grant No. 61306105), the National Science and Technology Major Project of China (Grant No. 2011ZX02708-002), the Tsinghua University Initiative Scientific Research Program and the Tsinghua National Laboratory for Information Science and Technology (TNList) Cross-discipline Foundation of China.

A Si/Ge heterojunction line tunnel field-effect transistor (LTFET) with a symmetric heteromaterial gate is proposed. Compared to single-material-gate LTFETs, the heteromaterial gate LTFET shows an off-state leakage current that is three orders of magnitude lower, and steeper subthreshold characteristics, without degradation in the on-state current. We reveal that these improvements are due to the induced local potential barrier, which arises from the energy-band profile modulation effect. Based on this novel structure, the impacts of the physical parameters of the gap region between the pocket and the drain, including the work-function mismatch between the pocket gate and the gap gate, the type of dopant, and the doping concentration, on the device performance are investigated. Simulation and theoretical calculation results indicate that the gap gate material and n-type doping level in the gap region should be optimized simultaneously to make this region fully depleted for further suppression of the off-state leakage current.

Full-zone spectral envelope function formalism for the optimization of line and point tunnel field-effect transistors

Efficient quantum mechanical simulation of tunnel field-effect transistors (TFETs) is indispensable to allow for an optimal configuration identification. We therefore present a full-zone 15-band quantum mechanical solver based on the envelope function formalism and employing a spectral method to reduce computational complexity and handle spurious solutions. We demonstrate the versatility of the solver by simulating a 40 nm wide In0.53Ga0.47As lineTFET and comparing it to p-n-i-n configurations with various pocket and body thicknesses. We find that the lineTFET performance is not degraded compared to semi-classical simulations. Furthermore, we show that a suitably optimized p-n-i-n TFET can obtain similar performance to the lineTFET.

Fabrication and Analysis of a ${\rm Si}/{\rm Si}_{0.55}{\rm Ge}_{0.45}$ Heterojunction Line Tunnel FET

This paper presents a new integration scheme to fabricate a Si/Si0.55Ge0.45 heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. The 1- μm gate length device shows on current in excess of 20 μA/μm at VGS=VDS=1.2 V. Low-temperature measurements, performed to suppress trap-assisted tunneling (TAT), reveal the point subthreshold swing as low as 22 mV/dec at 78 K. Field-induced quantum confinement effects are found to increase the tunneling onset voltage by ~ 0.35 V. Variation of the tunneling onset voltage measured experimentally is correlated to variation in the pocket thickness and its doping concentration. Small geometry devices were found to be more susceptible to microvariations in the pocket thickness and doping concentration.

Part I: Impact of Field-Induced Quantum Confinement on the Subthreshold Swing Behavior of Line TFETs

Trap-assisted tunneling (TAT) is a major hurdle in achieving a sub-60-mV/decade subthreshold swing (SS) in tunnel field-effect transistors (TFETs). This paper presents an insight into the TAT process in the presence of field-induced quantum confinement (FIQC) in line TFETs. We show that the SS degradation in line TFETs is mainly caused by TAT through traps located in the bulk of the semiconductor nearby the gate dielectric. For an Si n-type TFET, the energy quantization in the conduction band is found to suppress the TAT through the interface-region traps by several orders of magnitude and delay the TAT through bulk traps nearby the gate dielectric with several hundreds of millivolts. The trap levels closer to the conduction band were found to be the most efficient for TAT in this n-TFET. The FIQC onset voltage shift in TAT through bulk taps is found to be smaller than the band-to-band tunneling (BTBT) shift, enhancing the effective SS degradation in TFETs. We therefore show that it is equally important to include the FIQC effect when calculating TAT as when calculating BTBT generation rates.

Part II: Investigation of Subthreshold Swing in Line Tunnel FETs Using Bias Stress Measurements

The role of trap-assisted tunneling (TAT) in the degradation of the subthreshold swing (SS) in n-type line tunnel field-effect transistors (TFETs) is investigated through the experiments and simulations. A two to fourfold increase in the interface state density is achieved by applying a positive or a negative stress between the gate and the source. The negative stress shows no impact on the SS in spite of nearly fourfold increase in the interface state density. A nearly twofold increase in interface state density and improvement in SS are observed under the application of positive stress. The improvement in SS is attributed to H+ species released from the Si/ SiO2 interface during stress, which moves toward the bulk Si, passivating boron and bulk Si traps, thereby improving the SS. Under negative stress bias, the released H+ species drifts toward the gate electrode, and hence no change in SS was observed. These experiments suggest that the SS degradation is mainly caused by TAT through bulk Si traps and insensitive to interface traps. A good control of bulk semiconductor trap density will be required to achieve sub-60-mV/decade SS in line TFETs.

Corrections to “Quantum Mechanical Performance Predictions of p-n-i-n Versus Pocketed Line Tunnel Field-Effect Transistors” [Jul 13 2128-2134

The above-named article [ibid., vol. 60, no. 7, pp. 2128-134, Jul. 2013] contains an error in the legend of Fig. 11. The correct version is provided.

Quantum Mechanical Performance Predictions of p-n-i-n Versus Pocketed Line Tunnel Field-Effect Transistors

The tunnel field-effect transistor (TFET) is a promising candidate to replace the metal-oxide-semiconductor field-effect transistor in advanced technology nodes, because of its potential to obtain sub-60 mV/dec subthreshold swings. However, it is challenging to reach sufficiently high on-currents in TFETs. Therefore, on-current boosters are actively being researched. In this paper, a p-n-i-n TFET, containing a vertical pocket at the source-channel junction, is studied with quantum mechanical simulations and compared with a line tunneling TFET, containing horizontal pockets in the source region. The comparison is carried out both for all-Si and all-Ge, while an extrapolation is made for smaller bandgap materials. The p-n-i-n TFET is found to perform better than a p-i-n configuration, thanks to the increased electric field at the source-pocket junction. Compared to the p-n-i-n TFET, the line TFET has an even higher on-current and lower subthreshold swing, attributed to the closer proximity of the tunnel junction to the gate. For the all-Ge case, the difference between the two configurations is found to decrease when direct transitions are taken into account semi-classically.

A Simulation Study on Process Sensitivity of a Line Tunnel Field-Effect Transistor

A process sensitivity study of a steep subthreshold swing line tunnel field-effect transistor is presented for the first time using 2-D quantum-mechanical device simulations. The impact of various process parameters on the device transfer characteristics is presented with the help of process splits. A study of the thermal budget also shows that an increase in epitaxial growth thermal budget degrades the device performance by increasing the tunneling onset voltage <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TON</sub> and the off-current. Through process simulation and Plackett-Burman design of experiment (PB-DOE), the epitaxial layer thickness of the channel was identified as the most critical parameter in device processing. A thickness variation from 2 to 3 nm in the highly ( 7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> ) doped epitaxial was found to cause ~ 500-mV change in the tunneling onset voltage. It was found that an increase in doping concentration in the epitaxial layer to reduce quantum confinement effects will lead to an increase in the sensitivity of the device to the thickness of the epitaxial layer. A thicker epitaxial layer (5-6 nm) with lower doping concentration is recommended for reduced epitaxial layer variation sensitivity.