Line Transient Response Research Articles

A Low-Power Fast-Transient 90-nm Low-Dropout Regulator With Multiple Small-Gain Stages

A power-efficient 90-nm low-dropout regulator (LDO) with multiple small-gain stages is proposed in this paper. The proposed channel-resistance-insensitive small-gain stages provide loop gain enhancements without introducing low-frequency poles before the unity-gain frequency (UGF). As a result, both the loop gain and bandwidth of the LDO are improved, so that the accuracy and response speed of voltage regulation are significantly enhanced. As no on-chip compensation capacitor is required, the active chip area of the LDO is only 72.5 μm × 37.8 μm. Experimental results show that the LDO is capable of providing an output of 0.9 V with maximum output current of 50 mA from a 1-V supply. The LDO has a quiescent current of 9.3 μA, and has significantly improvement in line and load transient responses as well as performance in power-supply rejection ratio (PSRR).

Output-Capacitor-Free Adaptively Biased Low-Dropout Regulator for System-on-Chips

A high-precision low-voltage adaptively biased (AB) low-dropout regulator (LDR) with extended loop bandwidth is proposed. The multistage output-capacitor-free LDR is stabilized by Miller compensation and Q-reduction techniques to reduce the required minimum load current. Adaptive biasing is achieved by using direct current feedback from a simple current mirror. The dynamics of both the main feedback loop (MFL) and the adaptive biasing loop are thoroughly analyzed. Tradeoffs between the adaptive biasing factor and the MFL stability are discussed. The AB LDR is designed using a standard 0.35- ?m CMOS technology ( Vtn ? 0.52 V and Vtp ? -0.72 V). The output is 1.0 V, which delivers a maximum current of 100 mA. The minimum input voltage is 1.2 V, and the minimum load current required is reduced to 50 ?A . Extensive simulation results verify that the proposed LDR achieves high loop bandwidth, fast line and load transient responses, high power supply rejection, and low output impedance.

Hybrid Buck–Boost Feedforward and Reduced Average Inductor Current Techniques in Fast Line Transient and High-Efficiency Buck–Boost Converter

This paper presents a buck-boost converter with high efficiency and small output ripple to extend the battery life of portable devices. Besides, the hybrid buck-boost feedforward (HBBFF) technique is integrated in this converter to achieve fast line response. The new control topology minimizes the switching and conduction losses at the same time even when four switches are used. Therefore, over a wide input voltage range, the proposed buck-boost converter with minimum switching loss like the buck or boost converter can reduce the conduction loss through the use of the reduced average inductor current (RAIC) technique. Moreover, the HBBFF technique minimizes the voltage variation at the output of error amplifier. Consequently, a fast line transient response can be achieved with small dropout voltage at the output. Especially, the converter can offer good line and load regulations to ensure a regulated output voltage without being affected by the decreasing battery voltage. Experimental results show that the output voltage is regulated over a wide battery lifetime, and the output ripple is minimized during mode transition. The peak efficiency is 97% and the transient dropout voltage can be improved substantially.

A 3-A CMOS low-dropout regulator with adaptive Miller compensation

A 3-A CMOS low-dropout regulator (LDO) is presented by utilizing adaptive Miller compensation (AMC) technique, which provides high stability, as well as fast line and load transient responses. The proposed LDO has been fabricated in a standard 0.5 ?m CMOS technology, and the die area is small as 1330 ?m × 1330 ?m with the area-efficient waffle layout for power transistors. Both load and line regulation are less than ±0.1%. And the output voltage can recover within 80 ?s for full load changes. The power---supply rejection ratio (PSRR) at 20 KHz is ?30 dB. Moreover, it is stable enough with a ceramic capacitor small to 2.2 ?F, and the added series resistance is not needed.

A capacitor-free cmos low-dropout regulator with damping-factor-control frequency compensation

A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-/spl mu/m CMOS technology, and the active chip area is 568 /spl mu/m/spl times/541 /spl mu/m. The total error of the output voltage due to line and load variations is less than /spl plusmn/0.25%, and the temperature coefficient is 38 ppm//spl deg/C. Moreover, the output voltage can recover within 2 /spl mu/s for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 /spl mu/V//spl radic/Hz, respectively.

A ripple control buck regulator with fixed output frequency

This paper presents a ripple control buck regulator for stepping down high-voltage adaptor or battery supplies to low-voltage CPU core supply in notebook computers. Methods and circuits are proposed to achieve fixed switching frequency operation. The control loop adjusts delay of the controller and thus controls the output frequency. This is done by using a phase-frequency detector (PFD) to lock the frequency of switching signal with the input clock. The delay value is determined automatically according to operating conditions. Simulation results showed fast load and line transient responses and fixed frequency operations in steady states. In addition, stability of the regulator is shown under a very low output-to-input voltage ratio condition that is difficult for conventional PWM controllers.

Transient electronics: pulsed circuit technology

Preface. Mathematical Techniques for Pulse and Transient Circuit Analysis. Transmission Line Theory and Transient Response. Pulse--forming Lines. Pulse--forming Networks. Pulse Transformers. Transmission Line Pulse Transformers. Pulse Generators using Capacitive and Inductive Energy Storage. Nonlinear Pulsed Circuits. Appendix: Table of Laplace Transforms. Index.

Modeling the structural dynamic response of overhead transmission lines

Static analysis forms the basis of calculations in structural design of overhead power lines. The environmental loads considered in design can be assumed static (icing) or quasi-static (idealized steady wind). However, dynamic analysis is necessary to predict line transient response to shock loads such as those induced by the sudden failure of components or sudden ice-shedding effects on the conductors. This paper summarizes a macroscopic modeling approach to line dynamic analysis where emphasis is put on capturing the salient features of the propagation of such shock loads in a line section. The approach is illustrated with a case study of a line section having suffered two tower failures due to conductor breakages during an ice storm. The cable dynamics model proposed has been applied successfully to several examples, using the commercial software ADINA.

Characteristics of Coupled Buried Microstrip Lines by Modeling and Simulation

Electrical characteristics of coupled buried microstrip lines were obtained using a recently developed two-dimensional TEM transmission line parameter modeling tool. The capacitance [C] and inductance matrix [L] parameters were used in a lossless TEM mode transmission line transient response calculator to determine the maximum coupled noise. It is found that there is a critical depth of bury h <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</inf> below which the lines appear to be within an infinite dielectric and above which there is coupling to the polarization charge on the dielectric interface. This often results in very complicated Coupled noise behavior as the coupling of the lines is capacitive at One depth of bury and inductive at another depth of bury. Parameter simulation and maximum noise results are given for a wide variety of structures important in integrated circuit electronic packaging structures.

Forward and Backward Response Functions for Transmission Line Transient Analysis

This paper concerns the numerical evaluation of transmission line transient response using travelling-wave methods in which the effects of frequency dependent parameters are taken into account. Transmission line behaviour is considered in terms of forward and backward response functions, special emphasis being placed on the latter, which is introduced because of the time dependent nature of the line characteristic impedance. Relatively simple formulae are derived so that both response functions may be included in a general purpose computer program without difficulty. The validity of the approach is confirmed by comparing results with those obtained from the modified Fourier transform method.