Effect Of Line Edge Roughness Research Articles

Nondestructive analysis of lithographic patterns with natural line edge roughness from Mueller matrix ellipsometric data

Mueller matrix ellipsometry (MME) is applied to characterize lithographic patterns with natural line edge roughness (LER). A computationally efficient approach based on effective medium approximation is proposed to model the effects of LER in MME measurements. We present both the theoretical and experimental results on lithographic patterns with realistic LER which demonstrate that MME in combination with the proposed effective modeling method is capable of quantifying LER amplitudes. Quantitative comparisons between the MME and scanning electron microscopy measured results also reveal the strong potential of this technique for in-line nondestructive line roughness monitoring.

An Effective Modeling Framework for the Analysis of Interconnects Subject to Line-Edge Roughness

This letter proposes a complete and efficient simulation framework to assess the effects of line-edge roughness appearing in on-chip lines. The modeling approach consists of three steps. First, a stochastic macromodel is created for the per-unit-length RLGC parameters of the line. Secondly, random conductor edge profiles are generated using randomized splines. These are combined with the stochastic macromodel to readily provide place-dependent RLGC parameters. Finally, the resulting nonuniform transmission line is analyzed by means of a fast and accurate perturbation technique. To validate the proposed approach, a statistical analysis of the response of a coupled inverted embedded microstrip line is carried out for different roughness parameters.

Impact of Self-Heating on the Statistical Variability in Bulk and SOI FinFETs

In this paper, for the first time, we study the impact of self-heating on the statistical variability of bulk and Silicon-on-insulator FinFETs designed to meet the requirements of the 14/16-nm technology node. The simulations are performed using the Gold Standard Simulations atomistic simulator GARAND using an enhanced electrothermal model that considers the impact of the fin geometry on the thermal conductivity. In the simulations, we have compared the statistical variability obtained from full-scale electrothermal simulations with the variability at uniform room temperature and at the maximum or average temperatures obtained in the electrothermal simulations. The combined effects of line edge roughness and metal gate granularity are considered. The distributions and the correlations between key figures of merit, including the threshold voltage, ON-current, subthreshold slope, and leakage current are presented and analyzed.

Pentagate Approach to Reduce the Line Edge Roughness Effects in Bulk Si Tri-gate Transistors

ABSTRACTAccumulated body [1] approach to mitigate the effects of line edge roughness on bulk silicon finFETs and tri-gate FETs is analyzed through 3D TCAD simulations. A side-gate surrounding the body portion of the FET is used to accumulate the body with majority carriers. This approach is predicted to reduce device-to-device variability due to line edge roughness by stronger accumulation of the body in the wider sections of the channel and confinement of the channel away from the edges.

Stochastic Variability in Silicon Double-Gate Lateral Tunnel Field-Effect Transistors

Device-level variability in silicon double-gate lateral tunnel field-effect transistors (TFETs) due to line-edge roughness (LER) and random dopant fluctuation (RDF) is investigated for designs with a 20-nm gate length and body widths of 5 or 10 nm (“20/5” and “20/10,” respectively). Variability in TFET threshold voltage (VT), on-state drive current (Ion), off-state leakage current (Ioff), and subthreshold swing is examined by means of statistical technology computer-aided design simulations with consideration of body LER up to 1 nm in amplitude as well as RDF for body heights ranging from 10 to 40 nm. The effects of body LER and RDF are found to be similar in magnitude and also comparable to those in similarly designed fin FETs, with the exception of Ion variability which is roughly three times higher for TFETs. Arguments are presented to explain these findings based on the operating principle of TFETs compared to standard metal-oxide-semiconductor-FET-based technology.

Optimization of the Process Modules for a Top-Down Silicon Nanowire Fabrication Using Optical Lithography and Orientation Dependent Etching

A top-down silicon nanowire fabrication using a combination of optical lithography and orientation dependent etching has been developed using Silicon-on Insulator (SOI) as the starting substrate. The design of experiments for the optimization of the process flow especially on the orientation dependent etching using potassium hydroxide (KOH) and Tetra-Methyl Ammonium Hydroxide (TMAH) are presented in this paper. Based on the etching experiments using silicon substrates, KOH with added isopropyl alcohol (IPA) had shown to have a consistent etch rate with acceptable silicon surface roughness as compared with its other counterparts. The concern regarding the effect of line edge roughness (LER) as a result of optical lithography was highlighted and, therefore, the optimization of the patterning procedure was also discussed and presented.

Device- and Circuit-Level Variability Caused by Line Edge Roughness for Sub-32-nm FinFET Technologies

The variability impact of line edge roughness (LER) on sub-32-nm fin-shaped FET (FinFET) technologies is investigated from both device- and circuit-level perspectives using computer-aided design simulations. Resist-defined FinFETs exhibit sizeable device performance variation (up to 10% fluctuation in threshold voltage and 200% in leakage current) when subjected to fin roughness up to 1 nm root-mean-square amplitude. Spacer-defined FinFETs show negligible device performance variation and exhibit quadratic dependence with LER amplitude. For both patterning technologies, the resulting impact on large-scale digital-circuit performance variation is found to be minimal in terms of the overall delay mean and variation. This is attributed to self-averaging of uncorrelated LER effects between individual devices within the circuits, resulting in minimal delay impact for digital-circuit design. The impact of LER on leakage power variation is also found to be minimal for all technologies; however, the mean value increases by up to 40% for 15-nm resist FinFETs. On this basis, the impact of LER on sub-32-nm FinFET device-level variability is only significant for resist devices, whereas the resulting digital-circuit impact is important only in terms of mean leakage power increase.

Efficient statistical capacitance extraction of nanometer interconnects considering the on-chip line edge roughness

In this paper, efficient techniques are presented to extract the statistical interconnect capacitance due to random geometric variations, especially the line-edge roughness (LER). Based on the continuous-surface variation (CSV) model depicting wire thickness and width variations, an efficient approach is presented to calculate the capacitance sensitivity with respect to geometric variable, and further the statistical capacitance variance. The Hermite polynomial collocation (HPC) technique with variable reduction is also presented to generate the linear statistical capacitance model. Numerical experiments are carried out on structures in the 45nm down to the 19nm technologies. The results demonstrate the presented approaches are several orders of magnitude faster than the MC simulation with 5000 samples. The error of the sensitivity-based approach is less than 10% for the 45nm structures, while the HPC-based technique exhibits better accuracy, even for the 19nm structures with strong LER effect.

Field Dependence of Porous Low-$k$ Dielectric Breakdown as Revealed by the Effects of Line Edge Roughness on Failure Distributions

We investigate the electric field (E) dependence of the breakdown of porous low-k dielectrics by measuring the changes in the failure time distribution resulting from the presence of line edge roughness. We show that the Weibull β increases with decreasing field, clearly demonstrating that dielectric breakdown does not exhibit 1/E or E-n characteristics.

Spacer Gate Lithography for Reduced Variability Due to Line Edge Roughness

The effect of gate line edge roughness (LER) on bulk-Si MOSFET performance is studied using 3-D device simulations. The benefit of using a spacer (sidewall transfer) gate lithography process to mitigate the effect of LER is assessed, with consideration of source/drain placement and spacer width variation. The simulation results indicate that spacer gate lithography can dramatically reduce LER-induced variation in transistor performance and that variability can be well suppressed with gate-length scaling even if LER does not scale.

Effective medium approximations for modeling optical reflectance from gratings with rough edges

Line edge roughness (LER) has been identified as a potential source of uncertainty in optical scatterometry measurements. Characterizing the effect of LER on optical scatterometry signals is required to assess the uncertainty of the measurement. However, rigorous approaches to modeling the structures that are needed to simulate LER can be computationally expensive. In this work, we compare the effect of LER on scatterometry signals computed using an effective medium approximation (EMA) to those computed with realizations of rough interfaces. We find that for correlation lengths much less than the wavelength but greater than the rms roughness, an anisotropic EMA provides a satisfactory approximation in the cases studied.

Gate Line Edge Roughness Model for Estimation of FinFET Performance Variability

We present a model for estimating the impact of gate line edge roughness (LER) on the performance of double-gate (DG) FinFET devices. Thirteen-nanometer-gate-length DG FinFETs are investigated using a framework that links device performance to commonly used LER descriptors, namely, correlation length (xi), rms amplitude or standard deviation (sigma) of the line edge from its mean value, and roughness exponent ( alpha). Our approach provides physical insight into how LER impacts FinFET performance. In addition, our modeling approach is more efficient than Monte Carlo TCAD simulations and provides comparable results with appropriately selected input parameters. The FinFET device architecture is found to be robust to gate LER effects. Furthermore, a spacer-defined gate electrode (versus a resist-defined gate electrode) provides for reduced variability in performance, indicating that the gate length mismatch has more impact than lateral offset between the front and the back gates.

Impact of Line-Edge Roughness on Double-Gate Schottky-Barrier Field-Effect Transistors

The impact of line-edge roughness (LER) on double-gate (DG) Schottky-barrier field-effect transistors (SBFETs) in the level of device and circuit was investigated by a statistical simulation. The LER sequence is statistically generated by a Fourier analysis of the power spectrum of the Gaussian autocorrelation function. The results show that SBFETs are more sensitive to the LER effect in the high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> region and less sensitive in the subthreshold region compared with DG FinFETs. The aggressive fluctuation of drive current can be attributed to the variation of tunneling barrier width. Lowering the Schottky-barrier height and increasing the silicon-body thickness can suppress the parameter fluctuations from the LER effect. The simulation also shows that a 6T SRAM cell consisting of SBFETs is more vulnerable to noise disturbance than its counterpart consisting of FinFETs, particularly for the read operation, which is due to a larger mismatch of drivability of SBFETs within the cell.

Three-Dimensional Measurement of Line Edge Roughness in Copper Wires Using Electron Tomography

Electrical interconnects in integrated circuits have shrunk to sizes in the range of 20-100 nm. Accurate measurements of the dimensions of these nanowires are essential for identifying the dominant electron scattering mechanisms affecting wire resistivity as they continue to shrink. We report a systematic study of the effect of line edge roughness on the apparent cross-sectional area of 90 nm Cu wires with a TaN/Ta barrier measured by conventional two-dimensional projection imaging and three-dimensional electron tomography. Discrepancies in area measurements due to the overlap of defects along the wire's length lead to a 5% difference in the resistivities predicted by the two methods. Tomography of thick cross sections is shown to give a more accurate representation of the original structure and allows more efficient sampling of the wire's cross-sectional area. The effect of roughness on measurements from projection images is minimized for cross-section thicknesses less than 50 nm, or approximately half the spatial frequency of the roughness variations along the length of the investigated wires.

Triple-Gate Fin Field Effect Transistors with Fin-Thickness Optimization to Reduce the Impact of Fin Line Edge Roughness

Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin field effect transistors (FinFETs) with optimized fin-thickness (Tsi) to reduce the fin line edge roughness (LER) effect both in the device and circuit level. The results show that ultrathin fin will lead to intolerable parameter fluctuations in 20 nm double-gate (DG) FinFETs and FinFETs static random access memory (SRAM). Increasing Tsi can alleviate fin LER effect, but in the meantime it will exacerbate the short channel effect (SCE). TG structure can strengthen the gate controllability over the channel, thus, can suppress SCE and reduce LER effect as well. Adopting TG structure can relax the constraint of fin-thickness to half the gate length.

Reduction effect of line edge roughness on time-dependent dielectric breakdown lifetime of Cu/low-k interconnects by using CF3I etching

The authors investigated the etching of grooves in low-k in Cu technology. Correlation between the line edge roughness (LER) and the time-dependent dielectric breakdown (TDDB) reliability for 100nm pitch Cu interconnects was investigated. They controlled LER by using various gases to etch multilayer photoresist. CF3I gas was found to reduce LER better than conventional gases such as CF4 and CHF3 because CF3I has higher etching selectivity of photoresist against spin-on glass film. The LER did not affect measures of electrical performance such as wiring resistance, capacitance, and leakage current, but did affect TDDB lifetime because, according to their simulation, the electric field was strongly enhanced at curvatures in the interconnects. The maximum electric field (Emax) was also determined to evaluate the effect of LER on TDDB lifetime. All their results show that CF3I etching is promising for creating reliable Cu interconnects with smaller pitches.

The impact of line edge roughness on the stability of a FinFET SRAM

3D mixed-mode device-circuit simulation is presented to investigate the impact of line edge roughness (LER) on the stability of a FinFET SRAM. In this work, LER sequence is statistically generated by a Fourier analysis of the power spectrum of Gaussian autocorrelation function. The sensitivity of 20 nm FinFET SRAM of Read and Write static noise margins (SNM) to fin LER is evaluated. The results show that FinFET SRAM is more tolerant of disturbance in write operation than in read disturbance. The dependence of Read SNM on fin LER's root mean square (RMS) amplitude, fin thickness and supply voltage is also analyzed. Furthermore, methods to reduce the LER effect on the FinFET SRAM's read stability are introduced. Optimization of the cell ratio by a multiple-fin design, control of the access transistor's gate bias voltage and replacement of a 6T cell with an 8T cell are possible solutions to continue the scaling trend of SRAM in the nanoscale CMOS technology.

Impact of line-edge roughness on resistance and capacitance of scaled interconnects

The impact of line-edge roughness (LER) on resistance R and capacitance C of on-chip interconnects is for the first time evaluated by a simulation methodology based on a realistic modeling of LER. The model can be calibrated with measured LER parameters. A geometrical approximations of LER is generated and superimposed to an interconnect architecture model with no roughness; resistance and capacitance are extracted from the model by a 3D static solver to estimate the impact of LER on them. By applying this methodology to the interconnect scaling scenario of the 2005 ITRS Roadmap, a small but increasing detrimental effect of LER on both R and C is predicted.

Stochastic Matching Properties of FinFETs

For the first time, an experimental assessment of the intradie mismatch properties of a FinFET technology is presented. By applying the analysis to different combinations of gate stack materials, it is shown that the best results are obtained with undoped fins, with matching performances on par or even superior to those of planar MOSFETs. Furthermore, the observation in the narrowest transistors of a noticeable degradation of the mismatch in both the threshold voltage and current factor points to line-edge roughness effects as the presumed key factor influencing intradie mismatch in the smallest fin geometries

Gate line edge roughness amplitude and frequency variation effects on intra die MOS device characteristics

Random fluctuations in fabrication process outcomes such as gate line edge roughness (LER) give rise to corresponding fluctuations in scaled down MOS device characteristics. A thermodynamic-variational model is presented to study the effects of LER on threshold voltage and capacitance of sub-50 nm MOS devices. Conceptually, we treat the geometric definition of the MOS devices on a die as consisting of a collection of gates. In turn, each of these gates has an area, A, and a perimeter, P, defined by nominally straight lines subject to random process outcomes producing roughness. We treat roughness as being deviations from straightness consisting of both transverse amplitude and longitudinal wavelength each having lognormal distribution. We obtain closed-form expressions for variance of threshold voltage ( V th), and device capacitance ( C) at Onset of Strong Inversion (OSI) for a small device. Using our variational model, we characterized the device electrical properties such as σ V th and σ C in terms of the statistical parameters of the roughness amplitude and spatial frequency, i.e., inverse roughness wavelength. We then verified our model with numerical analysis of V th roll-off for small devices and σ V th due to dopant fluctuation. Our model was also benchmarked against TCAD of σ V th as a function of LER. We then extended our analysis to predict variations in σ V th and σ C versus average LER spatial frequency and amplitude, and oxide-thickness. Given the intuitive expectation that LER of very short wavelengths must also have small amplitude, we have investigated the case in which the amplitude mean is inversely related to the frequency mean. We compare with the situation in which amplitude and frequency mean are unrelated. Given also that the gate perimeter may consist of different LER signature for each side, we have extended our analysis to the case when the LER statistical difference between gate sides is moderate, as well as when it is significantly large.