MOSFET Lifetime Research Articles

WCF approach of reliability assessment for solid state power controller with accelerate degradation data

ABSTRACTThe lower confidence limit of system reliability plays an important role in system reliability assessment, and it is also of a concern to researchers and engineers. In this article, Winterbottom-Cornish-Fisher (WCF) method is applied to estimate the lower confidence limit of the reliability for Solid State Power Controller (SSPC). In order to do this, this article first fits the regression paths and extrapolates the pseudo lifetimes based on the degradation data of MOSFET. With the monotone coherent structure of SSPC and the cumulant properties of parameters, the lower confidence limit of SSPC reliability is derived from the pseudo lifetime of MOSFET.

A New BSIM3v3 SPICE Model for Reliability of Hot Carrier Injection Effect in MOSFET

This paper reports a new BSIM3v3 SPICE reliability model for describing the reliability of hot carrier injection (HCI) in MOSFET, which can be widely used in traditional process MOSFET. In this work, thousands of BSIM3v3 model parameters are analyzed, seven parameters primarily affected by HCI are extracted and optimized in original BSIM3v3 source code.The I-V simulation results after parameter extraction fits the measured results very well, so an accurate new model of MOSFETs reliability model is achieved. Using the new BSIM3v3 SPICE reliability model, the idvd curves at the stress time from 10 to 50000s of the nMOSFET with 10µm gate length and 0.5µm gate width can be achieved. So the device characters variation with time can be monitored. Besides, the typical Idsat, Vth, Idlin and Gmax degradation as a function of stress time are also plotted and the lifetime of MOSFETs can be evaluated from these functions.

SU-GG-I-67: Variation of MOSFET Calibration Factor as a Function of Dosimeter Age

Purpose: The purpose of this study was to examine the variation of the calibration factor (mV/cGy) as a function of the dosimeter age in diagnostic and therapeuticMOSFET dosimeters. Method and Materials: Two of each diagnostic and therapeuticMOSFET dosimeters (TN‐1002RD and TN‐502RD, Best Medical Canada) were used in the study. They were irradiated side by side next to a 0.18 cc MDH RadCal 9015 ion chamber. An AGFA X‐RAD 320 Orthovoltage x‐ray irradiator was used with the beam quality of HVL 7.9 mm Al equivalent to a typical CT beam at 120 kVp. The desired beam quality was achieved by adding a filter (2.5mm Al and 0.1 mm Cu) to the tube. The diagnosticMOSFETs with a high sensitivity bias setting were exposed at 120 kVp over the lifetime of MOSFET, i.e., the age of 0 to 20,000 mV and calibration factor obtained as specified by the manufacturer. Similarly, the therapeuticMOSFETs, using a standard sensitivity bias setting, were exposed at 250 kVp (commonly used in small animal dosimetry) over the lifetime of MOSFET.Results: It was observed that the diagnosticMOSFETcalibration factor remained within ±4% from the initial value from 0 mV up to the age of 12,000 mV (corresponding to a dose of ∼450 cGy), and then, the calibration factor decreased on average by 19% from 12,000 mV to 18,000 mV. The therapeuticMOSFETscalibration factor decreased linearly by approximately 3% every 3,000 mV up to the age of 18,000 mV. Conclusion: The diagnosticMOSFET detectors (TN‐1002RD) maintain their initial calibration up to 12,000 mV (approximately 450 cGy), and thereafter, a larger percentage uncertainty was seen; therefore, we recommend a recalibration after the age of 15,000 mV. The therapeuticMOSFET (TN‐502RD) should be recalibrated every 5,000mV over the life of the MOSFET.

Device reliability challenges for modern semiconductor circuit design – a review

Abstract. Product development based on highly integrated semiconductor circuits faces various challenges. To ensure the function of circuits the electrical parameters of every device must be in a specific window. This window is restricted by competing mechanisms like process variations and device degradation (Fig. 1). Degradation mechanisms like Negative Bias Temperature Instability (NBTI) or Hot Carrier Injection (HCI) lead to parameter drifts during operation adding on top of the process variations. The safety margin between real lifetime of MOSFETs and product lifetime requirements decreases at advanced technologies. The assignment of tasks to ensure the product lifetime has to be changed for the future. Up to now technology development has the main responsibility to adjust the technology processes to achieve the required lifetime. In future, reliability can no longer be the task of technology development only. Device degradation becomes a collective challenge for semiconductor technologist, reliability experts and circuit designers. Reliability issues have to be considered in design as well to achieve reliable and competitive products. For this work, designers require support by smart software tools with built-in reliability know how. Design for reliability will be one of the key requirements for modern product designs. An overview will be given of the physical device damage mechanisms, the operation conditions within circuits leading to stress and the impact of the corresponding device parameter degradation on the function of the circuit. Based on this understanding various approaches for Design for Reliability (DfR) will be described. The function of aging simulators will be explained and the flow of circuit-simulation will be described. Furthermore, the difference between full custom and semi custom design and therefore, the different required approaches will be discussed.

A new hot carrier degradation law for MOSFET lifetime prediction

We propose in this paper a new hot carrier degradation law for a reliable MOSFET lifetime prediction. We show that the proposed exponential function can describe all kind of curve concavity (saturating or non-saturating shapes) and can fit very well with the experimental data for the whole duration of the stress. Finally, it gives a more accurate lifetime value as compared to previous modelings because it accounts for the concavity of the saturating degradation law.

Reliability simulation of AC hot carrier degradation for deep sub‐micron MOSFETs

AbstractHigh performance under low supply voltage is required for ULSIs in combination with the higher packing density that results from scaling down to the deep sub‐micron region. For this requirement, the conventional method, using the DC hot carrier lifetime of MOSFETs as measured by DC stress, overestimates the degradation caused by real circuit operation. As a result, the improvement of MOSFET performance is limited by attempting to satisfy the overestimated hot carrier criteria under DC stress. Therefore, it is strongly desired that the reliability simulation estimate accurately hot carrier degradation in real circuit operation. We have found that the degradation rate depends on the stress conditions and can be expressed in terms of the difference between the gate and drain voltages. Hence, in this paper, we propose a new method of modeling and calculation of hot carrier degradation that incorporates this dependence and will demonstrate improved accuracy in predicting degradation and life time for both AC and DC bias conditions. We also propose a new duty ratio extraction method that can be used to predict the lifetime for hot carrier degradation under actual circuit operation.

Lifetime calculations of MOSFETs using depth-dependent non-local impact ionization

In this paper, we present a simple but accurate engineering tool for optimizing the lifetime of MOSFETs against hot carrier degradation. The method consists of simulation of the substrate currents in conjunction with the use of an empirical relation between the transistor lifetime and the MOSFET currents. Accurate calculations of the substrate currents are only possible if depth-dependent impact ionization is used in combination with the energy-balance equation.

Hot carrier evaluation of MOSFETs in ULSI circuits using the photon emission method

Photon emission from MOSFETs by hot carrier effect under AC operation is studied. A method to estimate the lifetime of MOSFETs in LSI chips, which uses the photon emission, is proposed. This method is based on experimental data showing that the lifetime of hot-carrier degradation is described by a universal curve with respect to the photon count at a wavelength of 200 nm. Quantitative estimations of lifetimes of MOSFETs in a real LSI are reported. This method is applied to the lifetime estimation of a CMOS microprocessor. >

Comparison of -MOSFET lifetime estimates based on GIDL enhancement and transconductance degradation as criteria

A comparison of MOSFET lifetimes based on gate-induced drain leakage (GIDL) enhancement and transconductance degradation as criteria is presented. Analysis of damage mechanisms indicates that degradations related to interface state generation limit the MOSFET lifetime at reduced voltage operations. In conventional gate oxide MOSFETs, GIDL enhancement due to band-to-defect tunneling and transconductance degradation limit the lifetime at reduced voltage. For MOSFETs with reoxidized nitrided gate oxides, our results show that GIDL enhancement due to band-to-defect tunneling is a better reliability monitor than transconductance degradation at low operating voltages.

Effects of radiative processing steps on inversion layer mobility and channel hot carrier damage in reoxidized nitrided oxide mosfets

The effects of x-ray irradiation and a subsequent low temperature anneal on the properties of reoxidized nitrided oxide (RNO) MOSFET's were examined. Irradiation was found to degrade conventional SiO2 MOSFET lifetime under channel hot carrier stress far more strongly than RNO lifetime, particularly for p-channel devices. This is attributed to reduced bulk neutral electron trap generation in RNO. The inversion layer mobility of RNOn-MOSFET's (and, to a lesser degree,p-MOSFET's) was found toincrease after irradiation and anneal. 1/f noise measurements indicate that this change in mobility is due to a reduction in the density of near-interface electron traps.

Simulation of MOSFET lifetime under AC hot-electron stress

A substrate current model and a quasistatic hot-electron-induced MOSFET degradation model have been implemented using the Substrate Current And Lifetime Evaluator (SCALE) package. It is shown that quasistatic simulation is valid for a class of waveforms that includes those encountered in inverter-based logic circuits. The validity and limitations of the model are illustrated with experimental results. SCALE is linked to SPICE externally in a pre- and postprocessor fashion to form an independent simulator. The preprocessor interprets the input deck and requests SPICE to output the transient node voltages of the user-selected devices. The postprocessor then calculates the transient substrate current and makes a lifetime prediction.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Hot-electron-induced MOSFET degradation at low temperatures

The n-channel LDD MOSFET lifetime is observed to follow \tau=(A/I_{d})(I_{sub}/I_{d})^{-n} from 77 to 295 K when the device is stressed near the maximum I sub . Here I d is the drain current and A is the proportionality constant. The experimental result indicates that n is approximately 2.7 and is independent of temperature. However, the proportionality constant A follows A = A_{0} \exp (-E_{a}/kT) , with E_{a} = 39 meV. The smaller proportionality constant at low temperatures suggests that hot-electron injection (HEI) degradation is caused by the electron trapping in the oxide.