Lifetime Killer Research Articles

Characteristics of TIL GTO thyristors using no lifetime killers

The investigation reported in this work was focused on the main characteristics of the recently developed two interdigitation level (TIL) gate turn-off (GTO) thyristors, which use neither lifetime killers nor anode shorts. The advantages of these TIL GTO's with low on-state losses are outlined in comparison with their identical, yet gold-doped, counterparts. It is shown that, except for the turn-off time, the main electrical characteristics of TIL GTO's using no induced recombination centers are superior to those of similar gold-doped devices. The current-handling capability of the former under tough electrothermal ratings is also better than that of gold-doped devices up to a commutation frequency of 5 kHz. The results of this work demonstrated that sought-for benefits could be obtained in TIL GTO's which use neither induced recombination centers nor anode shorts.

High-power, TIL-type gate-assisted turn-off thyristors

The work reports the development of trial high-voltage (2000–2500 V), highcurrent (up to 500 A) gate-assisted turn-off (GAT) thyristors based on the novel, double-interdigitated or two interdigitation levels (TIL) gate-cathode configuration. The active cathode area of devices is only 1.7 cm2. The test TIL GATTs were both normal, i.e. using no lifetime killers and gold-diffused at several temperatures. The investigations revealed the high efficiency of the negative current pulse, applied to the gate during the time when the forward anode voltage is being reapplied, in the reduction of the turn-off time t q. Thus, the application of a peak gate current I GR of only 2.5 − 4 A leads to a two- to tenfold decrease of t q in TIL GATTs rated at an anode current i T of 200-500 A. Within the aforementioned levels of i T and at constant value of i GR the dependence of t q on i T was found to be relatively weak. The dependence of TIL GATT performance on gold-doping, junction temperature, n-base thickness and the rate of reapplied anode voltage rise is presented in detail. All trial TIL GATTs possess an excellent turn-on sensitivity accompanied by a high immunity to noise. The results presented reveal the ability of TIL patterns with a relatively coarse geometry to perform multiple-end roles in various modes of operation of high-power GATTs.

Argon ion implantation gettering of large area p-n junctions and schottky diodes

Heavy metal impurities such as Au and Cu have localized energy states near the centre of the bandgap of silicon, acting as effective minority carrier lifetime killers. This in turn has a detrimental effect on the quality of current-voltage characteristics. Gettering methods are therefore of importance for performance improvement of semiconductor devices. In this paper the gettering effect was achieved by implantation of argon into the backside of the wafer with a subsequent annealing step. Two new applications, large-area p-n junctions and Schottky-barrier diodes are discussed, together with a possible mechanism by which the getter action can be explained.

Ultrahigh-voltage high-current gate turn-off thyristors

High-power GTO's with ratings of 2500 V . 2000 A have been developed, and a 4500 V . 2000 A GTO was trial fabricated and performance tested, for use in traction motor control equipment. Their low ON-state voltage was attained by applying a unique anode emitter shorting structure which does not require doping of a lifetime killer such as gold to obtain suitable GTO characteristics. Their high interrupt current was obtained by introducing a ring-shaped gate structure which has uniform operation between many segments in the devices during turn-off process.

High-efficiency electroplated heterojunction solar cell

Over 9% efficiency is demonstrated in electroplated CdS/CdTe thin film solar cells. Processing of the devices is described. A brief heat treatment step first anneals out the deep lifetime killer centers in the material then converts the originally n-type film into solar cell grade p-CdTe.

The behaviour of selected impurities in Cd xHg 1−xTe

Although Cd xHg 1−xTe is generally considered to be a defect semiconductor, whose electrical properties are controlled by adjusting the balance of metal vacancies to metal interstitial atoms, electrically active impurities present at the 0.1 ppma level, or below, can dominate the electrical properties. The main tool used to study the behaviour of impurties is Hall effect measurements, however, this should be supported by measurements of minority carrier lifetime in the bulk material. Crystals doped deliberately with Li, Cu, Ag, Ay, Al, In, Si, P, As, Sb, Cl and Fe have been grown. Mass Spectrometry and Atomic Absorption Spectrometry have been used to determine segregation coefficients for these and other elements. Combining Hall effect measurements with these chemical data enables the electrical behaviour of each impurity to be determined at a known level. In these crystals Li, Ag, Cu, P, As and Sb are found to be acceptors, Si, In, Al and Cl are donors while Au and Fe are electrically inactive. In the deliberately doped crystals both acceptor and donor impurities are found to drastically reduce the bulk lifetime at the high concentrations added, as expected. Iron also acts as a lifetime killer, despite its electrical inactivity, but gold does not. For crystals doped with donor impurities lifetime measurements down to low temperatures have been carried out to study the recombination mechanisms and the results of this work suggest that Shockley-Read centres exist even in undoped CMT crystals.

A high-power gate-controlled switch (GCS) using new lifetime control method

A high-power gate-controlled switch (GCS) with high switching speed was developed using a new method for controlling minority-carrier lifetime where both iron and gold were doped into the device. An improved temperature dependence of the forward voltage drop of the device was obtained because each of the forward voltage drops determined by iron and gold has opposite temperature dependence. The lifetime was controlled reproducibly by two-step diffusion of lifetime killers, that is, iron diffusion at high temperature and gold diffusion at lower temperatures afterwards. The relation between the forward voltage drop and the lifetime was theoretically analyzed and the agreement between the theory and experimental results was fairly good. The GCS of 0.15-cm2active area has the ratings of blocking voltage of 1500 V, available turn-off current of 160 A, forward voltage drop of 3 V at anode current of 100 A, and turn-off gain of 9. The turnoff time and turn-on time of less than 2 µs could be obtained. The dv/dt and di/dt are 1000 V/µs and 500 A/µs, respectively. The operation of 50 kHz at 100 A/1000 V could be realized with the inductive load of 50 µH by the GCS. The SIPOS (SemiInsulating POlycrystalline-Silicon) passivation was applied to the GCS in order to obtain the high reliability.

Potential Applications of Poly-Silicon as an Electronic-Device Material

ABSTRACTPoly-crystalline silicon can be regarded as a true electronic material if good p-n junctions can be made in it or if its state of depletion can be altered by reasonable gate voltages. The degree of perfection with which it must exhibit these electronic-material properties depends on whether the application is as a technology in VLSI (or other bulk-Si substrate use) where devices with bulk-crystalline properties are available or as the principal active material in Large Area Integration (LAI), such as flat-panel display addressing circuits, where the competition is much less demanding. The three main detrimental effects of grain boundaries on electronic-device function are the action of grain boundary traps as (1) extra charge centers, (2) lifetime killers, and (3) mobility-reducing scattering centers. The current trend in reducing or almost eliminating grain boundaries by laser recrystallization or lateral epitaxy has the effect of reducing the average number of traps. In terms of potential applications of the material, the improvement derived from these procedures must be balanced against other contraints placed on the overall structure. For example, the thickness and quality of the lower oxide (and interface) in these processes will determine whether an electronically active lower gate function is practical. Some currently envisioned applications include load devices in inverters either as resistors or as depletion transistors, common-gate staked CMOS structures, dual-channel MOSFET's, and other “vertical VLSI” applications. The systems-level topological advantages of stacked structures and the circuit-performance improvement provided by the ground plane in dielectrically isolated devices must also be balanced against the extra cost and yield loss of additional masking level complexity and design complication.

Electron and hole capture cross-sections at deep centers in gallium arsenide

A method is presented, which combines optical excitation and electrical refilling of deep levels, allowing one to measure the majority carrier capture cross-section for minority carrier traps : e.g., σn for a hole trap in n-type material. This method has been used to characterize many deep levels in gallium arsenide. The following results are obtained : the main electron trap « EL 2 » is not a hole lifetime killer; the temperature coefficient of the ionization energy for several levels, including the Cr level used for compensation in semi-insulating crystals ; very large (10-15 cm 2 or more), and very small (10-21 cm2) electron capture cross-sections for two of the levels ; possible capture mechanisms for these last cases are mentioned.

Silver as a Lifetime Killer in p-Ge, and a Hole Trap in Ge(Li) Detectors

The temperature dependence of the lifetime in silver doped p-Ge, as measured by the PCD method, is shown to be in agreement with a model for recombination through multivalent flaws. New values of capture cross section are determined (σ o/n = 1.5×10-14 cm2, σn- = 0.75×10-16 cm2). Lifetimes of electrons and holes are also measured on a silver doped Ge(Li) detector, by means of two techniques, using a collimated beam of ∂-rays (137Cs). Silver causes preferential hole tarpping and therefore cannot be responsible for the preferential electron trapping usually observed.